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Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +02009
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020010#ifndef __ASSEMBLY__
11#include <stdlib.h>
12#endif
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013
14#include <arch.h>
15
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020016#include "rcar_def.h"
17
18/*******************************************************************************
19 * Platform binary types for linking
20 ******************************************************************************/
21#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
22#define PLATFORM_LINKER_ARCH aarch64
23
24/*******************************************************************************
25 * Generic platform constants
26 ******************************************************************************/
27 #define FIRMWARE_WELCOME_STR "Booting Rcar-gen3 Trusted Firmware\n"
28
29/* Size of cacheable stacks */
30#if IMAGE_BL1
31#if TRUSTED_BOARD_BOOT
32#define PLATFORM_STACK_SIZE U(0x1000)
33#else
34#define PLATFORM_STACK_SIZE U(0x440)
35#endif
36#elif IMAGE_BL2
37#if TRUSTED_BOARD_BOOT
38#define PLATFORM_STACK_SIZE U(0x1000)
39#else
40#define PLATFORM_STACK_SIZE U(0x400)
41#endif
42#elif IMAGE_BL31
43#define PLATFORM_STACK_SIZE U(0x400)
44#elif IMAGE_BL32
45#define PLATFORM_STACK_SIZE U(0x440)
46#endif
47
48#define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1)
49#define BL333_IMAGE_ID (NS_BL2U_IMAGE_ID + 2)
50#define BL334_IMAGE_ID (NS_BL2U_IMAGE_ID + 3)
51#define BL335_IMAGE_ID (NS_BL2U_IMAGE_ID + 4)
52#define BL336_IMAGE_ID (NS_BL2U_IMAGE_ID + 5)
53#define BL337_IMAGE_ID (NS_BL2U_IMAGE_ID + 6)
54#define BL338_IMAGE_ID (NS_BL2U_IMAGE_ID + 7)
55
56#define BL332_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 8)
57#define BL333_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 9)
58#define BL334_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 10)
59#define BL335_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 11)
60#define BL336_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 12)
61#define BL337_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 13)
62#define BL338_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 14)
63
64#define BL332_CERT_ID (NS_BL2U_IMAGE_ID + 15)
65#define BL333_CERT_ID (NS_BL2U_IMAGE_ID + 16)
66#define BL334_CERT_ID (NS_BL2U_IMAGE_ID + 17)
67#define BL335_CERT_ID (NS_BL2U_IMAGE_ID + 18)
68#define BL336_CERT_ID (NS_BL2U_IMAGE_ID + 19)
69#define BL337_CERT_ID (NS_BL2U_IMAGE_ID + 20)
70#define BL338_CERT_ID (NS_BL2U_IMAGE_ID + 21)
71
72/* io drivers id */
73#define FLASH_DEV_ID U(0)
74#define EMMC_DEV_ID U(1)
75
76/*
77 * R-Car H3 Cortex-A57
78 * L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way)
79 * Cortex-A53
80 * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
81 */
Marek Vasut2eb10fd2018-12-30 17:21:39 +010082#define PLATFORM_CACHE_LINE_SIZE 64
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +020083#define PLATFORM_CLUSTER_COUNT U(2)
84#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
85#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
86#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
87 PLATFORM_CLUSTER0_CORE_COUNT)
88#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
89
90#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
91#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
92 PLATFORM_CLUSTER_COUNT + 1)
93
94#define PLAT_MAX_RET_STATE U(1)
95#define PLAT_MAX_OFF_STATE U(2)
96
97#define MAX_IO_DEVICES U(3)
98#define MAX_IO_HANDLES U(4)
99
100/*******************************************************************************
101 * BL2 specific defines.
102 ******************************************************************************/
103/* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
104 * size plus a little space for growth. */
105#define RCAR_SYSRAM_BASE U(0xE6300000)
Marek Vasut4ae342c2019-01-05 13:56:03 +0100106#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
Marek Vasut2e032c02018-12-26 15:57:08 +0100107#define BL2_LIMIT U(0xE6320000)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200108#else
Marek Vasut2e032c02018-12-26 15:57:08 +0100109#define BL2_LIMIT U(0xE6360000)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200110#endif
111
Marek Vasut4ae342c2019-01-05 13:56:03 +0100112#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
Valentine Barshakf2184142018-10-30 02:06:17 +0300113#define BL2_BASE U(0xE6304000)
Marek Vasut2e032c02018-12-26 15:57:08 +0100114#define BL2_IMAGE_LIMIT U(0xE6318000)
Valentine Barshakf2184142018-10-30 02:06:17 +0300115#elif (RCAR_LSI == RCAR_V3M)
116#define BL2_BASE U(0xE6344000)
117#define BL2_IMAGE_LIMIT U(0xE636E800)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200118#else
Valentine Barshakf2184142018-10-30 02:06:17 +0300119#define BL2_BASE U(0xE6304000)
Marek Vasut2e032c02018-12-26 15:57:08 +0100120#define BL2_IMAGE_LIMIT U(0xE632E800)
Jorge Ramirez-Ortizbf084dc2018-09-23 09:36:13 +0200121#endif
122#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
123
124/*******************************************************************************
125 * BL31 specific defines.
126 ******************************************************************************/
127/* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
128 * current BL3-1 debug size plus a little space for growth. */
129#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
130#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
131 RCAR_TRUSTED_SRAM_SIZE)
132#define RCAR_BL31_LOG_BASE (0x44040000)
133#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
134#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
135#define BL31_SRAM_BASE (DEVICE_SRAM_BASE)
136#define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
137
138/*******************************************************************************
139 * BL32 specific defines.
140 ******************************************************************************/
141#ifndef SPD_NONE
142#define BL32_BASE U(0x44100000)
143#define BL32_LIMIT (BL32_BASE + U(0x100000))
144#endif
145
146/*******************************************************************************
147 * BL33
148 ******************************************************************************/
149#define BL33_BASE DRAM1_NS_BASE
150
151
152/*******************************************************************************
153 * Platform specific page table and MMU setup constants
154 ******************************************************************************/
155#if IMAGE_BL1
156#define MAX_XLAT_TABLES U(2)
157#elif IMAGE_BL2
158#define MAX_XLAT_TABLES U(5)
159#elif IMAGE_BL31
160#define MAX_XLAT_TABLES U(4)
161#elif IMAGE_BL32
162#define MAX_XLAT_TABLES U(3)
163#endif
164
165#if IMAGE_BL2
166#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
167#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
168#else
169#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
170#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
171#endif
172
173#define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS)
174
175/*******************************************************************************
176 * Declarations and constants to access the mailboxes safely. Each mailbox is
177 * aligned on the biggest cache line size in the platform. This is known only
178 * to the platform as it might have a combination of integrated and external
179 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
180 * line at any cache level. They could belong to different cpus/clusters &
181 * get written while being protected by different locks causing corruption of
182 * a valid mailbox address.
183 ******************************************************************************/
184#define CACHE_WRITEBACK_SHIFT (6)
185#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
186
187/*******************************************************************************
188 * Size of the per-cpu data in bytes that should be reserved in the generic
189 * per-cpu data structure for the RCAR port.
190 ******************************************************************************/
191#if !USE_COHERENT_MEM
192#define PLAT_PCPU_DATA_SIZE (2)
193#endif
194
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000195#endif /* PLATFORM_DEF_H */