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Andrew Thoelke8c28fe02014-06-02 11:40:35 +01001/*
Roberto Vargas05712702018-02-12 12:36:17 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01005 */
6
Antonio Nino Diaz9fe40fd2018-10-25 17:11:02 +01007#ifndef CPU_DATA_H
8#define CPU_DATA_H
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01009
Etienne Carriere97ad6ce2017-09-01 10:22:20 +020010#include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */
11
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <bl31/ehf.h>
13
Soby Mathew748be1d2016-05-05 14:10:46 +010014#ifdef AARCH32
15
16#if CRASH_REPORTING
17#error "Crash reporting is not supported in AArch32"
18#endif
19#define CPU_DATA_CPU_OPS_PTR 0x0
Etienne Carriere97ad6ce2017-09-01 10:22:20 +020020#define CPU_DATA_CRASH_BUF_OFFSET 0x4
Soby Mathew748be1d2016-05-05 14:10:46 +010021
22#else /* AARCH32 */
23
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010024/* Offsets for the cpu_data structure */
Soby Mathew523d6332015-01-08 18:02:19 +000025#define CPU_DATA_CRASH_BUF_OFFSET 0x18
Soby Mathew748be1d2016-05-05 14:10:46 +010026/* need enough space in crash buffer to save 8 registers */
27#define CPU_DATA_CRASH_BUF_SIZE 64
28#define CPU_DATA_CPU_OPS_PTR 0x10
29
30#endif /* AARCH32 */
31
Soby Mathewc1adbbc2014-06-25 10:07:40 +010032#if CRASH_REPORTING
dp-arm3cac7862016-09-19 11:18:44 +010033#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
34 CPU_DATA_CRASH_BUF_SIZE)
Soby Mathewc1adbbc2014-06-25 10:07:40 +010035#else
dp-arm3cac7862016-09-19 11:18:44 +010036#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
Soby Mathewc1adbbc2014-06-25 10:07:40 +010037#endif
Soby Mathewc704cbc2014-08-14 11:33:56 +010038
Etienne Carriere97ad6ce2017-09-01 10:22:20 +020039/* cpu_data size is the data size rounded up to the platform cache line size */
40#define CPU_DATA_SIZE (((CPU_DATA_CRASH_BUF_END + \
41 CACHE_WRITEBACK_GRANULE - 1) / \
42 CACHE_WRITEBACK_GRANULE) * \
43 CACHE_WRITEBACK_GRANULE)
44
dp-arm3cac7862016-09-19 11:18:44 +010045#if ENABLE_RUNTIME_INSTRUMENTATION
46/* Temporary space to store PMF timestamps from assembly code */
47#define CPU_DATA_PMF_TS_COUNT 1
48#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
49#define CPU_DATA_PMF_TS0_IDX 0
50#endif
51
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010052#ifndef __ASSEMBLY__
53
54#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000055#include <lib/cassert.h>
56#include <lib/psci/psci.h>
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010057#include <platform_def.h>
58#include <stdint.h>
59
Soby Mathew523d6332015-01-08 18:02:19 +000060/* Offsets for the cpu_data structure */
61#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\
62 (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info)
63
64#if PLAT_PCPU_DATA_SIZE
65#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\
66 (cpu_data_t, platform_cpu_data)
67#endif
68
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010069/*******************************************************************************
70 * Function & variable prototypes
71 ******************************************************************************/
72
73/*******************************************************************************
74 * Cache of frequently used per-cpu data:
Andrew Thoelkec02dbd62014-06-02 10:00:25 +010075 * Pointers to non-secure and secure security state contexts
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010076 * Address of the crash stack
77 * It is aligned to the cache line boundary to allow efficient concurrent
78 * manipulation of these pointers on different cpus
79 *
80 * TODO: Add other commonly used variables to this (tf_issues#90)
81 *
82 * The data structure and the _cpu_data accessors should not be used directly
83 * by components that have per-cpu members. The member access macros should be
84 * used for this.
85 ******************************************************************************/
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010086typedef struct cpu_data {
Soby Mathew748be1d2016-05-05 14:10:46 +010087#ifndef AARCH32
Andrew Thoelkec02dbd62014-06-02 10:00:25 +010088 void *cpu_context[2];
Soby Mathew748be1d2016-05-05 14:10:46 +010089#endif
Soby Mathewa0fedc42016-06-16 14:52:04 +010090 uintptr_t cpu_ops_ptr;
Soby Mathewc1adbbc2014-06-25 10:07:40 +010091#if CRASH_REPORTING
Soby Mathewa0fedc42016-06-16 14:52:04 +010092 u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
Soby Mathewc1adbbc2014-06-25 10:07:40 +010093#endif
dp-arm3cac7862016-09-19 11:18:44 +010094#if ENABLE_RUNTIME_INSTRUMENTATION
95 uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
96#endif
Soby Mathew523d6332015-01-08 18:02:19 +000097 struct psci_cpu_data psci_svc_cpu_data;
98#if PLAT_PCPU_DATA_SIZE
99 uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
100#endif
Jeenu Viswambharan10a67272017-09-22 08:32:10 +0100101#if defined(IMAGE_BL31) && EL3_EXCEPTION_HANDLING
102 pe_exc_data_t ehf_data;
103#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100104} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
105
Roberto Vargas05712702018-02-12 12:36:17 +0000106extern cpu_data_t percpu_data[PLATFORM_CORE_COUNT];
107
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100108#if CRASH_REPORTING
109/* verify assembler offsets match data structures */
110CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
111 (cpu_data_t, crash_buf),
112 assert_cpu_data_crash_stack_offset_mismatch);
113#endif
114
Etienne Carriere97ad6ce2017-09-01 10:22:20 +0200115CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t),
116 assert_cpu_data_size_mismatch);
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100117
Soby Mathewc704cbc2014-08-14 11:33:56 +0100118CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
119 (cpu_data_t, cpu_ops_ptr),
120 assert_cpu_data_cpu_ops_ptr_offset_mismatch);
121
dp-arm3cac7862016-09-19 11:18:44 +0100122#if ENABLE_RUNTIME_INSTRUMENTATION
123CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof
124 (cpu_data_t, cpu_data_pmf_ts[0]),
125 assert_cpu_data_pmf_ts0_offset_mismatch);
126#endif
127
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100128struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100129
Soby Mathew748be1d2016-05-05 14:10:46 +0100130#ifndef AARCH32
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100131/* Return the cpu_data structure for the current CPU. */
132static inline struct cpu_data *_cpu_data(void)
133{
134 return (cpu_data_t *)read_tpidr_el3();
135}
Soby Mathew748be1d2016-05-05 14:10:46 +0100136#else
137struct cpu_data *_cpu_data(void);
138#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100139
140/**************************************************************************
141 * APIs for initialising and accessing per-cpu data
142 *************************************************************************/
143
144void init_cpu_data_ptr(void);
Vikram Kanigiri9b38fc82015-01-29 18:27:38 +0000145void init_cpu_ops(void);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100146
147#define get_cpu_data(_m) _cpu_data()->_m
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000148#define set_cpu_data(_m, _v) _cpu_data()->_m = (_v)
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100149#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000150#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = (_v)
Joel Hutton43a4d572017-10-20 10:31:14 +0100151/* ((cpu_data_t *)0)->_m is a dummy to get the sizeof the struct member _m */
Soby Mathew24ab34f2016-05-03 17:11:42 +0100152#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
Joel Hutton43a4d572017-10-20 10:31:14 +0100153 &(_cpu_data()->_m), \
154 sizeof(((cpu_data_t *)0)->_m))
Soby Mathew24ab34f2016-05-03 17:11:42 +0100155#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
Joel Hutton43a4d572017-10-20 10:31:14 +0100156 &(_cpu_data()->_m), \
157 sizeof(((cpu_data_t *)0)->_m))
Soby Mathew7d861ea2014-11-18 10:14:14 +0000158#define flush_cpu_data_by_index(_ix, _m) \
Soby Mathewa0fedc42016-06-16 14:52:04 +0100159 flush_dcache_range((uintptr_t) \
Soby Mathew7d861ea2014-11-18 10:14:14 +0000160 &(_cpu_data_by_index(_ix)->_m), \
Joel Hutton43a4d572017-10-20 10:31:14 +0100161 sizeof(((cpu_data_t *)0)->_m))
Achin Guptae4b9fa42014-07-25 14:47:05 +0100162
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100163
164#endif /* __ASSEMBLY__ */
Antonio Nino Diaz9fe40fd2018-10-25 17:11:02 +0100165#endif /* CPU_DATA_H */