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Soby Mathewe063d3c2015-10-07 09:45:27 +01001/*
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Soby Mathewe063d3c2015-10-07 09:45:27 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewe063d3c2015-10-07 09:45:27 +01005 */
6
7#ifndef __GICV2_H__
8#define __GICV2_H__
9
10/*******************************************************************************
11 * GICv2 miscellaneous definitions
12 ******************************************************************************/
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +010013
14/* Interrupt group definitions */
15#define GICV2_INTR_GROUP0 0
16#define GICV2_INTR_GROUP1 1
17
Soby Mathewe063d3c2015-10-07 09:45:27 +010018/* Interrupt IDs reported by the HPPIR and IAR registers */
19#define PENDING_G1_INTID 1022
20
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +010021/* GICv2 can only target up to 8 PEs */
22#define GICV2_MAX_TARGET_PE 8
23
Soby Mathewe063d3c2015-10-07 09:45:27 +010024/*******************************************************************************
25 * GICv2 specific Distributor interface register offsets and constants.
26 ******************************************************************************/
27#define GICD_ITARGETSR 0x800
28#define GICD_SGIR 0xF00
29#define GICD_CPENDSGIR 0xF10
30#define GICD_SPENDSGIR 0xF20
31#define GICD_PIDR2_GICV2 0xFE8
32
33#define ITARGETSR_SHIFT 2
34#define GIC_TARGET_CPU_MASK 0xff
35
36#define CPENDSGIR_SHIFT 2
37#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
38
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010039#define SGIR_TGTLSTFLT_SHIFT 24
40#define SGIR_TGTLSTFLT_MASK 0x3
41#define SGIR_TGTLST_SHIFT 16
42#define SGIR_TGTLST_MASK 0xff
43#define SGIR_INTID_MASK 0xf
44
45#define SGIR_TGT_SPECIFIC 0
46
47#define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \
48 ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \
49 (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \
50 ((intid) & SGIR_INTID_MASK))
51
Soby Mathewe063d3c2015-10-07 09:45:27 +010052/*******************************************************************************
53 * GICv2 specific CPU interface register offsets and constants.
54 ******************************************************************************/
55/* Physical CPU Interface registers */
56#define GICC_CTLR 0x0
57#define GICC_PMR 0x4
58#define GICC_BPR 0x8
59#define GICC_IAR 0xC
60#define GICC_EOIR 0x10
61#define GICC_RPR 0x14
62#define GICC_HPPIR 0x18
63#define GICC_AHPPIR 0x28
64#define GICC_IIDR 0xFC
65#define GICC_DIR 0x1000
66#define GICC_PRIODROP GICC_EOIR
67
68/* GICC_CTLR bit definitions */
69#define EOI_MODE_NS (1 << 10)
70#define EOI_MODE_S (1 << 9)
71#define IRQ_BYP_DIS_GRP1 (1 << 8)
72#define FIQ_BYP_DIS_GRP1 (1 << 7)
73#define IRQ_BYP_DIS_GRP0 (1 << 6)
74#define FIQ_BYP_DIS_GRP0 (1 << 5)
75#define CBPR (1 << 4)
76#define FIQ_EN_SHIFT 3
77#define FIQ_EN_BIT (1 << FIQ_EN_SHIFT)
78#define ACK_CTL (1 << 2)
79
80/* GICC_IIDR bit masks and shifts */
81#define GICC_IIDR_PID_SHIFT 20
82#define GICC_IIDR_ARCH_SHIFT 16
83#define GICC_IIDR_REV_SHIFT 12
84#define GICC_IIDR_IMP_SHIFT 0
85
86#define GICC_IIDR_PID_MASK 0xfff
87#define GICC_IIDR_ARCH_MASK 0xf
88#define GICC_IIDR_REV_MASK 0xf
89#define GICC_IIDR_IMP_MASK 0xfff
90
91/* HYP view virtual CPU Interface registers */
92#define GICH_CTL 0x0
93#define GICH_VTR 0x4
94#define GICH_ELRSR0 0x30
95#define GICH_ELRSR1 0x34
96#define GICH_APR0 0xF0
97#define GICH_LR_BASE 0x100
98
99/* Virtual CPU Interface registers */
100#define GICV_CTL 0x0
101#define GICV_PRIMASK 0x4
102#define GICV_BP 0x8
103#define GICV_INTACK 0xC
104#define GICV_EOI 0x10
105#define GICV_RUNNINGPRI 0x14
106#define GICV_HIGHESTPEND 0x18
107#define GICV_DEACTIVATE 0x1000
108
109/* GICD_CTLR bit definitions */
110#define CTLR_ENABLE_G1_SHIFT 1
111#define CTLR_ENABLE_G1_MASK 0x1
112#define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT)
113
114/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
115#define INT_ID_MASK 0x3ff
116
117#ifndef __ASSEMBLY__
118
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100119#include <interrupt_props.h>
Soby Mathewe063d3c2015-10-07 09:45:27 +0100120#include <stdint.h>
121
122/*******************************************************************************
123 * This structure describes some of the implementation defined attributes of
124 * the GICv2 IP. It is used by the platform port to specify these attributes
125 * in order to initialize the GICv2 driver. The attributes are described
126 * below.
127 *
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100128 * The 'gicd_base' field contains the base address of the Distributor interface
129 * programmer's view.
Soby Mathewe063d3c2015-10-07 09:45:27 +0100130 *
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100131 * The 'gicc_base' field contains the base address of the CPU Interface
132 * programmer's view.
Soby Mathewe063d3c2015-10-07 09:45:27 +0100133 *
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100134 * The 'g0_interrupt_array' field is a pointer to an array in which each entry
135 * corresponds to an ID of a Group 0 interrupt. This field is ignored when
136 * 'interrupt_props' field is used. This field is deprecated.
Soby Mathewe063d3c2015-10-07 09:45:27 +0100137 *
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100138 * The 'g0_interrupt_num' field contains the number of entries in the
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100139 * 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
140 * used. This field is deprecated.
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100141 *
142 * The 'target_masks' is a pointer to an array containing 'target_masks_num'
143 * elements. The GIC driver will populate the array with per-PE target mask to
144 * use to when targeting interrupts.
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100145 *
146 * The 'interrupt_props' field is a pointer to an array that enumerates secure
147 * interrupts and their properties. If this field is not NULL, both
148 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
149 *
150 * The 'interrupt_props_num' field contains the number of entries in the
151 * 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is
152 * ignored.
Soby Mathewe063d3c2015-10-07 09:45:27 +0100153 ******************************************************************************/
154typedef struct gicv2_driver_data {
155 uintptr_t gicd_base;
156 uintptr_t gicc_base;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100157#if !ERROR_DEPRECATED
Soby Mathewe063d3c2015-10-07 09:45:27 +0100158 unsigned int g0_interrupt_num;
159 const unsigned int *g0_interrupt_array;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100160#endif
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100161 unsigned int *target_masks;
162 unsigned int target_masks_num;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100163 const interrupt_prop_t *interrupt_props;
164 unsigned int interrupt_props_num;
Soby Mathewe063d3c2015-10-07 09:45:27 +0100165} gicv2_driver_data_t;
166
167/*******************************************************************************
168 * Function prototypes
169 ******************************************************************************/
170void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data);
171void gicv2_distif_init(void);
172void gicv2_pcpu_distif_init(void);
173void gicv2_cpuif_enable(void);
174void gicv2_cpuif_disable(void);
175unsigned int gicv2_is_fiq_enabled(void);
176unsigned int gicv2_get_pending_interrupt_type(void);
177unsigned int gicv2_get_pending_interrupt_id(void);
178unsigned int gicv2_acknowledge_interrupt(void);
179void gicv2_end_of_interrupt(unsigned int id);
180unsigned int gicv2_get_interrupt_group(unsigned int id);
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100181unsigned int gicv2_get_running_priority(void);
Jeenu Viswambharan393fdd92017-09-22 08:32:09 +0100182void gicv2_set_pe_target_mask(unsigned int proc_num);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100183unsigned int gicv2_get_interrupt_active(unsigned int id);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100184void gicv2_enable_interrupt(unsigned int id);
185void gicv2_disable_interrupt(unsigned int id);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100186void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100187void gicv2_set_interrupt_type(unsigned int id, unsigned int type);
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100188void gicv2_raise_sgi(int sgi_num, int proc_num);
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100189void gicv2_set_spi_routing(unsigned int id, int proc_num);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100190void gicv2_set_interrupt_pending(unsigned int id);
191void gicv2_clear_interrupt_pending(unsigned int id);
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100192unsigned int gicv2_set_pmr(unsigned int mask);
Soby Mathewe063d3c2015-10-07 09:45:27 +0100193
194#endif /* __ASSEMBLY__ */
195#endif /* __GICV2_H__ */