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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautierac22dd52021-03-22 14:22:14 +01002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Yann Gautier4b0c72a2018-07-16 10:54:09 +020010#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <arch_helpers.h>
13#include <common/debug.h>
14#include <drivers/io/io_block.h>
15#include <drivers/io/io_driver.h>
16#include <drivers/io/io_dummy.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010017#include <drivers/io/io_mtd.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018#include <drivers/io/io_storage.h>
19#include <drivers/mmc.h>
20#include <drivers/partition/partition.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010021#include <drivers/raw_nand.h>
Lionel Debieve186b0462019-09-24 18:30:12 +020022#include <drivers/spi_nand.h>
Lionel Debievecb0dbc42019-09-25 09:11:31 +020023#include <drivers/spi_nor.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <drivers/st/io_mmc.h>
25#include <drivers/st/io_stm32image.h>
Lionel Debieve402a46b2019-11-04 12:28:15 +010026#include <drivers/st/stm32_fmc2_nand.h>
Lionel Debieve186b0462019-09-24 18:30:12 +020027#include <drivers/st/stm32_qspi.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028#include <drivers/st/stm32_sdmmc2.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000029#include <lib/mmio.h>
30#include <lib/utils.h>
31#include <plat/common/platform.h>
32
Yann Gautier4b0c72a2018-07-16 10:54:09 +020033/* IO devices */
Yann Gautier73b8b1c2021-06-03 10:48:57 +020034#ifndef AARCH32_SP_OPTEE
Yann Gautier4b0c72a2018-07-16 10:54:09 +020035static const io_dev_connector_t *dummy_dev_con;
36static uintptr_t dummy_dev_handle;
37static uintptr_t dummy_dev_spec;
Yann Gautier73b8b1c2021-06-03 10:48:57 +020038#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020039
Yann Gautier8244e1d2018-10-15 09:36:58 +020040static uintptr_t image_dev_handle;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +020041static uintptr_t storage_dev_handle;
Yann Gautier8244e1d2018-10-15 09:36:58 +020042
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +020043#if STM32MP_SDMMC || STM32MP_EMMC
Yann Gautierac22dd52021-03-22 14:22:14 +010044static struct mmc_device_info mmc_info;
Yann Gautier8244e1d2018-10-15 09:36:58 +020045static io_block_spec_t gpt_block_spec = {
46 .offset = 0,
47 .length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */
48};
49
Yann Gautierf9af3bc2018-11-09 15:57:18 +010050static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
Yann Gautier8244e1d2018-10-15 09:36:58 +020051
52static const io_block_dev_spec_t mmc_block_dev_spec = {
53 /* It's used as temp buffer in block driver */
54 .buffer = {
55 .offset = (size_t)&block_buffer,
56 .length = MMC_BLOCK_SIZE,
57 },
58 .ops = {
59 .read = mmc_read_blocks,
60 .write = NULL,
61 },
62 .block_size = MMC_BLOCK_SIZE,
63};
64
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +020065#if STM32MP_EMMC_BOOT
66static io_block_spec_t emmc_boot_ssbl_block_spec = {
67 .offset = PLAT_EMMC_BOOT_SSBL_OFFSET,
68 .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */
69};
70
71static const io_block_dev_spec_t mmc_block_dev_boot_part_spec = {
72 /* It's used as temp buffer in block driver */
73 .buffer = {
74 .offset = (size_t)&block_buffer,
75 .length = MMC_BLOCK_SIZE,
76 },
77 .ops = {
78 .read = mmc_boot_part_read_blocks,
79 .write = NULL,
80 },
81 .block_size = MMC_BLOCK_SIZE,
82};
83#endif
84
85static struct io_mmc_dev_spec mmc_device_spec = {
86 .use_boot_part = false,
87};
88
Yann Gautier8244e1d2018-10-15 09:36:58 +020089static const io_dev_connector_t *mmc_dev_con;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +020090#endif /* STM32MP_SDMMC || STM32MP_EMMC */
Yann Gautier8244e1d2018-10-15 09:36:58 +020091
Lionel Debievecb0dbc42019-09-25 09:11:31 +020092#if STM32MP_SPI_NOR
93static io_mtd_dev_spec_t spi_nor_dev_spec = {
94 .ops = {
95 .init = spi_nor_init,
96 .read = spi_nor_read,
97 },
98};
99#endif
100
Lionel Debieve402a46b2019-11-04 12:28:15 +0100101#if STM32MP_RAW_NAND
102static io_mtd_dev_spec_t nand_dev_spec = {
103 .ops = {
104 .init = nand_raw_init,
105 .read = nand_read,
106 },
107};
108
109static const io_dev_connector_t *nand_dev_con;
110#endif
111
Lionel Debieve186b0462019-09-24 18:30:12 +0200112#if STM32MP_SPI_NAND
113static io_mtd_dev_spec_t spi_nand_dev_spec = {
114 .ops = {
115 .init = spi_nand_init,
116 .read = nand_read,
117 },
118};
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200119#endif
Lionel Debieve186b0462019-09-24 18:30:12 +0200120
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200121#if STM32MP_SPI_NAND || STM32MP_SPI_NOR
Lionel Debieve186b0462019-09-24 18:30:12 +0200122static const io_dev_connector_t *spi_dev_con;
123#endif
124
Yann Gautierb3386f72019-04-19 09:41:01 +0200125#ifdef AARCH32_SP_OPTEE
126static const struct stm32image_part_info optee_header_partition_spec = {
127 .name = OPTEE_HEADER_IMAGE_NAME,
128 .binary_type = OPTEE_HEADER_BINARY_TYPE,
129};
130
Yann Gautierebf15ba2021-05-19 16:10:25 +0200131static const struct stm32image_part_info optee_core_partition_spec = {
132 .name = OPTEE_CORE_IMAGE_NAME,
133 .binary_type = OPTEE_CORE_BINARY_TYPE,
Yann Gautierb3386f72019-04-19 09:41:01 +0200134};
135
136static const struct stm32image_part_info optee_paged_partition_spec = {
137 .name = OPTEE_PAGED_IMAGE_NAME,
138 .binary_type = OPTEE_PAGED_BINARY_TYPE,
139};
140#else
Yann Gautierf9d40d52019-01-17 14:41:46 +0100141static const io_block_spec_t bl32_block_spec = {
142 .offset = BL32_BASE,
Yann Gautiera2e2a302019-02-14 11:13:39 +0100143 .length = STM32MP_BL32_SIZE
Yann Gautierf9d40d52019-01-17 14:41:46 +0100144};
Yann Gautierb3386f72019-04-19 09:41:01 +0200145#endif
Yann Gautierf9d40d52019-01-17 14:41:46 +0100146
Yann Gautier8244e1d2018-10-15 09:36:58 +0200147static const struct stm32image_part_info bl33_partition_spec = {
148 .name = BL33_IMAGE_NAME,
149 .binary_type = BL33_BINARY_TYPE,
150};
151
Yann Gautierf9d40d52019-01-17 14:41:46 +0100152enum {
153 IMG_IDX_BL33,
Yann Gautierb3386f72019-04-19 09:41:01 +0200154#ifdef AARCH32_SP_OPTEE
155 IMG_IDX_OPTEE_HEADER,
Yann Gautierebf15ba2021-05-19 16:10:25 +0200156 IMG_IDX_OPTEE_CORE,
Yann Gautierb3386f72019-04-19 09:41:01 +0200157 IMG_IDX_OPTEE_PAGED,
158#endif
Yann Gautierf9d40d52019-01-17 14:41:46 +0100159 IMG_IDX_NUM
160};
161
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200162static struct stm32image_device_info stm32image_dev_info_spec __unused = {
Yann Gautier8244e1d2018-10-15 09:36:58 +0200163 .lba_size = MMC_BLOCK_SIZE,
164 .part_info[IMG_IDX_BL33] = {
165 .name = BL33_IMAGE_NAME,
166 .binary_type = BL33_BINARY_TYPE,
167 },
Yann Gautierb3386f72019-04-19 09:41:01 +0200168#ifdef AARCH32_SP_OPTEE
169 .part_info[IMG_IDX_OPTEE_HEADER] = {
170 .name = OPTEE_HEADER_IMAGE_NAME,
171 .binary_type = OPTEE_HEADER_BINARY_TYPE,
172 },
Yann Gautierebf15ba2021-05-19 16:10:25 +0200173 .part_info[IMG_IDX_OPTEE_CORE] = {
174 .name = OPTEE_CORE_IMAGE_NAME,
175 .binary_type = OPTEE_CORE_BINARY_TYPE,
Yann Gautierb3386f72019-04-19 09:41:01 +0200176 },
177 .part_info[IMG_IDX_OPTEE_PAGED] = {
178 .name = OPTEE_PAGED_IMAGE_NAME,
179 .binary_type = OPTEE_PAGED_BINARY_TYPE,
180 },
181#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200182};
183
Yann Gautierf9d40d52019-01-17 14:41:46 +0100184static io_block_spec_t stm32image_block_spec = {
185 .offset = 0,
186 .length = 0,
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200187};
188
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200189static const io_dev_connector_t *stm32image_dev_con __unused;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200190
Yann Gautier73b8b1c2021-06-03 10:48:57 +0200191#ifndef AARCH32_SP_OPTEE
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200192static int open_dummy(const uintptr_t spec);
Yann Gautier73b8b1c2021-06-03 10:48:57 +0200193#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200194static int open_image(const uintptr_t spec);
195static int open_storage(const uintptr_t spec);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200196
197struct plat_io_policy {
198 uintptr_t *dev_handle;
199 uintptr_t image_spec;
200 int (*check)(const uintptr_t spec);
201};
202
203static const struct plat_io_policy policies[] = {
Yann Gautierb3386f72019-04-19 09:41:01 +0200204#ifdef AARCH32_SP_OPTEE
205 [BL32_IMAGE_ID] = {
206 .dev_handle = &image_dev_handle,
207 .image_spec = (uintptr_t)&optee_header_partition_spec,
208 .check = open_image
209 },
210 [BL32_EXTRA1_IMAGE_ID] = {
211 .dev_handle = &image_dev_handle,
Yann Gautierebf15ba2021-05-19 16:10:25 +0200212 .image_spec = (uintptr_t)&optee_core_partition_spec,
Yann Gautierb3386f72019-04-19 09:41:01 +0200213 .check = open_image
214 },
215 [BL32_EXTRA2_IMAGE_ID] = {
216 .dev_handle = &image_dev_handle,
217 .image_spec = (uintptr_t)&optee_paged_partition_spec,
218 .check = open_image
219 },
220#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200221 [BL32_IMAGE_ID] = {
222 .dev_handle = &dummy_dev_handle,
223 .image_spec = (uintptr_t)&bl32_block_spec,
224 .check = open_dummy
225 },
Yann Gautierb3386f72019-04-19 09:41:01 +0200226#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200227 [BL33_IMAGE_ID] = {
228 .dev_handle = &image_dev_handle,
229 .image_spec = (uintptr_t)&bl33_partition_spec,
230 .check = open_image
231 },
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200232#if STM32MP_SDMMC || STM32MP_EMMC
Yann Gautier8244e1d2018-10-15 09:36:58 +0200233 [GPT_IMAGE_ID] = {
234 .dev_handle = &storage_dev_handle,
235 .image_spec = (uintptr_t)&gpt_block_spec,
236 .check = open_storage
237 },
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200238#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200239 [STM32_IMAGE_ID] = {
240 .dev_handle = &storage_dev_handle,
241 .image_spec = (uintptr_t)&stm32image_block_spec,
242 .check = open_storage
243 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200244};
245
Yann Gautier73b8b1c2021-06-03 10:48:57 +0200246#ifndef AARCH32_SP_OPTEE
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200247static int open_dummy(const uintptr_t spec)
248{
249 return io_dev_init(dummy_dev_handle, 0);
250}
Yann Gautier73b8b1c2021-06-03 10:48:57 +0200251#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200252
Yann Gautier8244e1d2018-10-15 09:36:58 +0200253static int open_image(const uintptr_t spec)
254{
255 return io_dev_init(image_dev_handle, 0);
256}
257
258static int open_storage(const uintptr_t spec)
259{
260 return io_dev_init(storage_dev_handle, 0);
261}
262
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +0200263#if STM32MP_EMMC_BOOT
264static uint32_t get_boot_part_ssbl_header(void)
265{
266 uint32_t magic = 0;
267 int io_result;
268 size_t bytes_read;
269
270 io_result = register_io_dev_block(&mmc_dev_con);
271 if (io_result != 0) {
272 panic();
273 }
274
275 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_boot_part_spec,
276 &storage_dev_handle);
277 assert(io_result == 0);
278
279 io_result = io_open(storage_dev_handle, (uintptr_t) &emmc_boot_ssbl_block_spec,
280 &image_dev_handle);
281 assert(io_result == 0);
282
283 io_result = io_read(image_dev_handle, (uintptr_t) &magic, sizeof(magic),
284 &bytes_read);
285 assert(io_result == 0);
286 assert(bytes_read == sizeof(magic));
287
288 io_result = io_dev_close(storage_dev_handle);
289 assert(io_result == 0);
290
291 return magic;
292}
293#endif
294
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200295static void print_boot_device(boot_api_context_t *boot_context)
296{
297 switch (boot_context->boot_interface_selected) {
298 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
299 INFO("Using SDMMC\n");
300 break;
301 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
302 INFO("Using EMMC\n");
303 break;
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200304 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
305 INFO("Using QSPI NOR\n");
306 break;
Lionel Debieve402a46b2019-11-04 12:28:15 +0100307 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
308 INFO("Using FMC NAND\n");
309 break;
Lionel Debieve186b0462019-09-24 18:30:12 +0200310 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
311 INFO("Using SPI NAND\n");
312 break;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200313 default:
314 ERROR("Boot interface not found\n");
315 panic();
316 break;
317 }
318
319 if (boot_context->boot_interface_instance != 0U) {
320 INFO(" Instance %d\n", boot_context->boot_interface_instance);
321 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200322}
323
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200324#if STM32MP_SDMMC || STM32MP_EMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200325static void boot_mmc(enum mmc_device_type mmc_dev_type,
326 uint16_t boot_interface_instance)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200327{
328 int io_result __unused;
Yann Gautierf9d40d52019-01-17 14:41:46 +0100329 uint8_t idx;
330 struct stm32image_part_info *part;
Yann Gautier8244e1d2018-10-15 09:36:58 +0200331 struct stm32_sdmmc2_params params;
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +0200332 const partition_entry_t *entry __unused;
333 uint32_t magic __unused;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200334
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200335 zeromem(&params, sizeof(struct stm32_sdmmc2_params));
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200336
Yann Gautierac22dd52021-03-22 14:22:14 +0100337 mmc_info.mmc_dev_type = mmc_dev_type;
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200338
339 switch (boot_interface_instance) {
340 case 1:
341 params.reg_base = STM32MP_SDMMC1_BASE;
342 break;
343 case 2:
344 params.reg_base = STM32MP_SDMMC2_BASE;
345 break;
346 case 3:
347 params.reg_base = STM32MP_SDMMC3_BASE;
348 break;
349 default:
350 WARN("SDMMC instance not found, using default\n");
351 if (mmc_dev_type == MMC_IS_SD) {
352 params.reg_base = STM32MP_SDMMC1_BASE;
353 } else {
354 params.reg_base = STM32MP_SDMMC2_BASE;
355 }
356 break;
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200357 }
358
Yann Gautierac22dd52021-03-22 14:22:14 +0100359 params.device_info = &mmc_info;
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200360 if (stm32_sdmmc2_mmc_init(&params) != 0) {
361 ERROR("SDMMC%u init failed\n", boot_interface_instance);
362 panic();
363 }
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +0200364
365 stm32image_dev_info_spec.device_size =
366 stm32_sdmmc2_mmc_get_device_size();
367
368#if STM32MP_EMMC_BOOT
369 magic = get_boot_part_ssbl_header();
370
371 if (magic == BOOT_API_IMAGE_HEADER_MAGIC_NB) {
372 VERBOSE("%s, header found, jump to emmc load\n", __func__);
373 idx = IMG_IDX_BL33;
374 part = &stm32image_dev_info_spec.part_info[idx];
375 part->part_offset = PLAT_EMMC_BOOT_SSBL_OFFSET;
376 part->bkp_offset = 0U;
377 mmc_device_spec.use_boot_part = true;
378
379 goto emmc_boot;
380 } else {
381 WARN("%s: Can't find STM32 header on a boot partition\n", __func__);
382 }
383#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200384
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200385 /* Open MMC as a block device to read GPT table */
386 io_result = register_io_dev_block(&mmc_dev_con);
387 if (io_result != 0) {
388 panic();
389 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200390
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200391 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
392 &storage_dev_handle);
393 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200394
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200395 partition_init(GPT_IMAGE_ID);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200396
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200397 io_result = io_dev_close(storage_dev_handle);
398 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200399
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200400 for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
401 part = &stm32image_dev_info_spec.part_info[idx];
402 entry = get_partition_entry(part->name);
403 if (entry == NULL) {
404 ERROR("Partition %s not found\n", part->name);
Yann Gautier03f04682018-11-29 15:44:04 +0100405 panic();
406 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200407
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200408 part->part_offset = entry->start;
409 part->bkp_offset = 0U;
410 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200411
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +0200412#if STM32MP_EMMC_BOOT
413emmc_boot:
414#endif
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200415 /*
416 * Re-open MMC with io_mmc, for better perfs compared to
417 * io_block.
418 */
419 io_result = register_io_dev_mmc(&mmc_dev_con);
420 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200421
Vyacheslav Yurkove43a0802021-06-04 10:10:51 +0200422 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_device_spec,
423 &storage_dev_handle);
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200424 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200425
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200426 io_result = register_io_dev_stm32image(&stm32image_dev_con);
427 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200428
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200429 io_result = io_dev_open(stm32image_dev_con,
430 (uintptr_t)&stm32image_dev_info_spec,
431 &image_dev_handle);
432 assert(io_result == 0);
433}
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200434#endif /* STM32MP_SDMMC || STM32MP_EMMC */
Yann Gautier8244e1d2018-10-15 09:36:58 +0200435
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200436#if STM32MP_SPI_NOR
437static void boot_spi_nor(boot_api_context_t *boot_context)
438{
439 int io_result __unused;
440 uint8_t idx;
441 struct stm32image_part_info *part;
442
443 io_result = stm32_qspi_init();
444 assert(io_result == 0);
445
446 io_result = register_io_dev_mtd(&spi_dev_con);
447 assert(io_result == 0);
448
449 /* Open connections to device */
450 io_result = io_dev_open(spi_dev_con,
451 (uintptr_t)&spi_nor_dev_spec,
452 &storage_dev_handle);
453 assert(io_result == 0);
454
455 stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size;
456
457 idx = IMG_IDX_BL33;
458 part = &stm32image_dev_info_spec.part_info[idx];
459 part->part_offset = STM32MP_NOR_BL33_OFFSET;
460 part->bkp_offset = 0U;
461
462#ifdef AARCH32_SP_OPTEE
463 idx = IMG_IDX_OPTEE_HEADER;
464 part = &stm32image_dev_info_spec.part_info[idx];
465 part->part_offset = STM32MP_NOR_TEEH_OFFSET;
466 part->bkp_offset = 0U;
467
468 idx = IMG_IDX_OPTEE_PAGED;
469 part = &stm32image_dev_info_spec.part_info[idx];
470 part->part_offset = STM32MP_NOR_TEED_OFFSET;
471 part->bkp_offset = 0U;
472
Yann Gautierebf15ba2021-05-19 16:10:25 +0200473 idx = IMG_IDX_OPTEE_CORE;
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200474 part = &stm32image_dev_info_spec.part_info[idx];
475 part->part_offset = STM32MP_NOR_TEEX_OFFSET;
476 part->bkp_offset = 0U;
477#endif
478
479 io_result = register_io_dev_stm32image(&stm32image_dev_con);
480 assert(io_result == 0);
481
482 io_result = io_dev_open(stm32image_dev_con,
483 (uintptr_t)&stm32image_dev_info_spec,
484 &image_dev_handle);
485 assert(io_result == 0);
486}
487#endif /* STM32MP_SPI_NOR */
488
Lionel Debieve402a46b2019-11-04 12:28:15 +0100489#if STM32MP_RAW_NAND
490static void boot_fmc2_nand(boot_api_context_t *boot_context)
491{
492 int io_result __unused;
493 uint8_t idx;
494 struct stm32image_part_info *part;
495
496 io_result = stm32_fmc2_init();
497 assert(io_result == 0);
498
499 /* Register the IO device on this platform */
500 io_result = register_io_dev_mtd(&nand_dev_con);
501 assert(io_result == 0);
502
503 /* Open connections to device */
504 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
505 &storage_dev_handle);
506 assert(io_result == 0);
507
508 stm32image_dev_info_spec.device_size = nand_dev_spec.device_size;
509
510 idx = IMG_IDX_BL33;
511 part = &stm32image_dev_info_spec.part_info[idx];
512 part->part_offset = STM32MP_NAND_BL33_OFFSET;
513 part->bkp_offset = nand_dev_spec.erase_size;
514
515#ifdef AARCH32_SP_OPTEE
516 idx = IMG_IDX_OPTEE_HEADER;
517 part = &stm32image_dev_info_spec.part_info[idx];
518 part->part_offset = STM32MP_NAND_TEEH_OFFSET;
519 part->bkp_offset = nand_dev_spec.erase_size;
520
521 idx = IMG_IDX_OPTEE_PAGED;
522 part = &stm32image_dev_info_spec.part_info[idx];
523 part->part_offset = STM32MP_NAND_TEED_OFFSET;
524 part->bkp_offset = nand_dev_spec.erase_size;
525
Yann Gautierebf15ba2021-05-19 16:10:25 +0200526 idx = IMG_IDX_OPTEE_CORE;
Lionel Debieve402a46b2019-11-04 12:28:15 +0100527 part = &stm32image_dev_info_spec.part_info[idx];
528 part->part_offset = STM32MP_NAND_TEEX_OFFSET;
529 part->bkp_offset = nand_dev_spec.erase_size;
530#endif
531
532 io_result = register_io_dev_stm32image(&stm32image_dev_con);
533 assert(io_result == 0);
534
535 io_result = io_dev_open(stm32image_dev_con,
536 (uintptr_t)&stm32image_dev_info_spec,
537 &image_dev_handle);
538 assert(io_result == 0);
539}
540#endif /* STM32MP_RAW_NAND */
541
Lionel Debieve186b0462019-09-24 18:30:12 +0200542#if STM32MP_SPI_NAND
543static void boot_spi_nand(boot_api_context_t *boot_context)
544{
545 int io_result __unused;
546 uint8_t idx;
547 struct stm32image_part_info *part;
548
549 io_result = stm32_qspi_init();
550 assert(io_result == 0);
551
552 io_result = register_io_dev_mtd(&spi_dev_con);
553 assert(io_result == 0);
554
555 /* Open connections to device */
556 io_result = io_dev_open(spi_dev_con,
557 (uintptr_t)&spi_nand_dev_spec,
558 &storage_dev_handle);
559 assert(io_result == 0);
560
561 stm32image_dev_info_spec.device_size =
562 spi_nand_dev_spec.device_size;
563
564 idx = IMG_IDX_BL33;
565 part = &stm32image_dev_info_spec.part_info[idx];
566 part->part_offset = STM32MP_NAND_BL33_OFFSET;
567 part->bkp_offset = spi_nand_dev_spec.erase_size;
568
569#ifdef AARCH32_SP_OPTEE
570 idx = IMG_IDX_OPTEE_HEADER;
571 part = &stm32image_dev_info_spec.part_info[idx];
572 part->part_offset = STM32MP_NAND_TEEH_OFFSET;
573 part->bkp_offset = spi_nand_dev_spec.erase_size;
574
575 idx = IMG_IDX_OPTEE_PAGED;
576 part = &stm32image_dev_info_spec.part_info[idx];
577 part->part_offset = STM32MP_NAND_TEED_OFFSET;
578 part->bkp_offset = spi_nand_dev_spec.erase_size;
579
Yann Gautierebf15ba2021-05-19 16:10:25 +0200580 idx = IMG_IDX_OPTEE_CORE;
Lionel Debieve186b0462019-09-24 18:30:12 +0200581 part = &stm32image_dev_info_spec.part_info[idx];
582 part->part_offset = STM32MP_NAND_TEEX_OFFSET;
583 part->bkp_offset = spi_nand_dev_spec.erase_size;
584#endif
585
586 io_result = register_io_dev_stm32image(&stm32image_dev_con);
587 assert(io_result == 0);
588
589 io_result = io_dev_open(stm32image_dev_con,
590 (uintptr_t)&stm32image_dev_info_spec,
591 &image_dev_handle);
592 assert(io_result == 0);
593}
594#endif /* STM32MP_SPI_NAND */
595
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200596void stm32mp_io_setup(void)
597{
598 int io_result __unused;
599 boot_api_context_t *boot_context =
600 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautierf9d40d52019-01-17 14:41:46 +0100601
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200602 print_boot_device(boot_context);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200603
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200604 if ((boot_context->boot_partition_used_toboot == 1U) ||
605 (boot_context->boot_partition_used_toboot == 2U)) {
606 INFO("Boot used partition fsbl%d\n",
607 boot_context->boot_partition_used_toboot);
608 }
Yann Gautier8244e1d2018-10-15 09:36:58 +0200609
Yann Gautier73b8b1c2021-06-03 10:48:57 +0200610#ifndef AARCH32_SP_OPTEE
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200611 io_result = register_io_dev_dummy(&dummy_dev_con);
612 assert(io_result == 0);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200613
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200614 io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
615 &dummy_dev_handle);
616 assert(io_result == 0);
Yann Gautier73b8b1c2021-06-03 10:48:57 +0200617#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200618
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200619 switch (boot_context->boot_interface_selected) {
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200620#if STM32MP_SDMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200621 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
622 dmbsy();
623 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
624 break;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200625#endif
626#if STM32MP_EMMC
Yann Gautiereae3fbf2019-04-23 13:34:03 +0200627 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
628 dmbsy();
629 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
Yann Gautier8244e1d2018-10-15 09:36:58 +0200630 break;
Nicolas Le Bayon3f42cad2019-09-03 09:52:05 +0200631#endif
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200632#if STM32MP_SPI_NOR
633 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
634 dmbsy();
635 boot_spi_nor(boot_context);
636 break;
637#endif
Lionel Debieve402a46b2019-11-04 12:28:15 +0100638#if STM32MP_RAW_NAND
639 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
640 dmbsy();
641 boot_fmc2_nand(boot_context);
642 break;
643#endif
Lionel Debieve186b0462019-09-24 18:30:12 +0200644#if STM32MP_SPI_NAND
645 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
646 dmbsy();
647 boot_spi_nand(boot_context);
648 break;
649#endif
Yann Gautier8244e1d2018-10-15 09:36:58 +0200650
651 default:
652 ERROR("Boot interface %d not supported\n",
653 boot_context->boot_interface_selected);
654 break;
655 }
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200656}
657
658/*
659 * Return an IO device handle and specification which can be used to access
660 * an image. Use this to enforce platform load policy.
661 */
662int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
663 uintptr_t *image_spec)
664{
665 int rc;
666 const struct plat_io_policy *policy;
667
668 assert(image_id < ARRAY_SIZE(policies));
669
670 policy = &policies[image_id];
671 rc = policy->check(policy->image_spec);
672 if (rc == 0) {
673 *image_spec = policy->image_spec;
674 *dev_handle = *(policy->dev_handle);
675 }
676
677 return rc;
678}