blob: c01a1de9b6adb78eb8d36ca02fd85e4d6aac9250 [file] [log] [blame]
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02001/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02007#include <assert.h>
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +02008#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <arch_helpers.h>
12#include <common/debug.h>
13#include <lib/bakery_lock.h>
14#include <lib/mmio.h>
15#include <lib/xlat_tables/xlat_tables_v2.h>
16
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +020017#include "iic_dvfs.h"
18#include "rcar_def.h"
19#include "rcar_private.h"
20#include "pwrc.h"
21
22/*
23 * Someday there will be a generic power controller api. At the moment each
24 * platform has its own pwrc so just exporting functions should be acceptable.
25 */
26RCAR_INSTANTIATE_LOCK
27
28#define WUP_IRQ_SHIFT (0U)
29#define WUP_FIQ_SHIFT (8U)
30#define WUP_CSD_SHIFT (16U)
31#define BIT_SOFTRESET (1U<<15)
32#define BIT_CA53_SCU (1U<<21)
33#define BIT_CA57_SCU (1U<<12)
34#define REQ_RESUME (1U<<1)
35#define REQ_OFF (1U<<0)
36#define STATUS_PWRUP (1U<<4)
37#define STATUS_PWRDOWN (1U<<0)
38#define STATE_CA57_CPU (27U)
39#define STATE_CA53_CPU (22U)
40#define MODE_L2_DOWN (0x00000002U)
41#define CPU_PWR_OFF (0x00000003U)
42#define RCAR_PSTR_MASK (0x00000003U)
43#define ST_ALL_STANDBY (0x00003333U)
44/* Suspend to ram */
45#define DBSC4_REG_BASE (0xE6790000U)
46#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
47#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U)
48#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U)
49#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U)
50#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U)
51#define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U)
52#define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U)
53#define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U)
54#define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U)
55#define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U)
56#define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U)
57#define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U)
58#define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U)
59#define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U)
60#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0))
61#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0))
62#define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U)
63#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U)
64#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U)
65#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U)
66#define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U)
67#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U)
68#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U)
69#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U)
70#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U)
71#define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U)
72#define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U)
73#define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U)
74#define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU)
75#define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU)
76#define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U)
77#define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U)
78#define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U)
79#define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U)
80#define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U)
81#define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU)
82#define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU)
83#define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU)
84#define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU)
85#define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU)
86#define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU)
87#define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U)
88#define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U)
89#define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U)
90#define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U)
91#define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U)
92#define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U)
93#define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U)
94#define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U)
95#define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U)
96#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U)
97#define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U)
98#define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U)
99#define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U)
100#define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U)
101#define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U)
102#define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U)
103#define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U)
104#define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U)
105#define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U)
106#define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U)
107#define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U)
108#define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U)
109#define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U)
110#define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U)
111#define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U)
112#define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U)
113#define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U)
114#define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U)
115#define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U)
116#define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U)
117#define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U)
118#define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U)
119#define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U)
120#define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U)
121#define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U)
122#define RST_BASE (0xE6160000U)
123#define RST_MODEMR (RST_BASE + 0x0060U)
124#define RST_MODEMR_BIT0 (0x00000001U)
125#define RCAR_CONV_MICROSEC (1000000U)
126
127#if PMIC_ROHM_BD9571
128#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
129#define PMIC_BKUP_MODE_CNT (0x20U)
130#define PMIC_QLLM_CNT (0x27U)
131#define PMIC_RETRY_MAX (100U)
132#endif
133#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0)
134#define RCAR_CA53CPU_NUM_MAX (4U)
135#define RCAR_CA57CPU_NUM_MAX (4U)
136#define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57)
137#define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57)
138#define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53)
139
140#ifndef __ASSEMBLY__
141IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START);
142IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
143IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
144#endif
145
146#if RCAR_SYSTEM_SUSPEND
147static void __attribute__ ((section (".system_ram")))
148 rcar_pwrc_micro_delay(uint64_t micro_sec)
149{
150 uint64_t freq, base, val;
151 uint64_t wait_time = 0;
152
153 freq = read_cntfrq_el0();
154 base = read_cntpct_el0();
155
156 while (micro_sec > wait_time) {
157 val = read_cntpct_el0() - base;
158 wait_time = val * RCAR_CONV_MICROSEC / freq;
159 }
160}
161#endif
162
163uint32_t rcar_pwrc_status(uint64_t mpidr)
164{
165 uint32_t ret = 0;
166 uint64_t cm, cpu;
167 uint32_t reg;
168 uint32_t c;
169
170 rcar_lock_get();
171
172 c = rcar_pwrc_get_cluster();
173 cm = mpidr & MPIDR_CLUSTER_MASK;
174
175 if (!IS_A53A57(c) && cm != 0) {
176 ret = RCAR_INVALID;
177 goto done;
178 }
179
180 reg = mmio_read_32(RCAR_PRR);
181 cpu = mpidr & MPIDR_CPU_MASK;
182
183 if (IS_CA53(c))
184 if (reg & (1 << (STATE_CA53_CPU + cpu)))
185 ret = RCAR_INVALID;
186 if (IS_CA57(c))
187 if (reg & (1 << (STATE_CA57_CPU + cpu)))
188 ret = RCAR_INVALID;
189done:
190 rcar_lock_release();
191
192 return ret;
193}
194
195static void scu_power_up(uint64_t mpidr)
196{
197 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
198 uint32_t c, sysc_reg_bit;
199
200 c = rcar_pwrc_get_mpidr_cluster(mpidr);
201 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
202 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU;
203 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3;
204 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3;
205 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3;
206
207 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0)
208 return;
209
210 if (mmio_read_32(reg_cpumcr) != 0)
211 mmio_write_32(reg_cpumcr, 0);
212
213 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
214 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
215
216 do {
217 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0)
218 ;
219 mmio_write_32(reg_pwron, 1);
220 } while (mmio_read_32(reg_pwrer) & 1);
221
222 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
223 ;
224 mmio_write_32(RCAR_SYSCISR, sysc_reg_bit);
225 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
226 ;
227}
228
229void rcar_pwrc_cpuon(uint64_t mpidr)
230{
231 uint32_t res_data, on_data;
232 uintptr_t res_reg, on_reg;
233 uint32_t limit, c;
234 uint64_t cpu;
235
236 rcar_lock_get();
237
238 c = rcar_pwrc_get_mpidr_cluster(mpidr);
239 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT;
240 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR;
241 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000;
242
243 res_data = mmio_read_32(res_reg) | limit;
244 scu_power_up(mpidr);
245 cpu = mpidr & MPIDR_CPU_MASK;
246 on_data = 1 << cpu;
247 mmio_write_32(RCAR_CPGWPR, ~on_data);
248 mmio_write_32(on_reg, on_data);
249 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
250
251 rcar_lock_release();
252}
253
254void rcar_pwrc_cpuoff(uint64_t mpidr)
255{
256 uint32_t c;
257 uintptr_t reg;
258 uint64_t cpu;
259
260 rcar_lock_get();
261
262 cpu = mpidr & MPIDR_CPU_MASK;
263 c = rcar_pwrc_get_mpidr_cluster(mpidr);
264 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR;
265
266 if (read_mpidr_el1() != mpidr)
267 panic();
268
269 mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
270 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
271
272 rcar_lock_release();
273}
274
275void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
276{
277 uint32_t c, shift_irq, shift_fiq;
278 uintptr_t reg;
279 uint64_t cpu;
280
281 rcar_lock_get();
282
283 cpu = mpidr & MPIDR_CPU_MASK;
284 c = rcar_pwrc_get_mpidr_cluster(mpidr);
285 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
286
287 shift_irq = WUP_IRQ_SHIFT + cpu;
288 shift_fiq = WUP_FIQ_SHIFT + cpu;
289
290 mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) &
291 ~((uint32_t) 1 << shift_fiq));
292 rcar_lock_release();
293}
294
295void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
296{
297 uint32_t c, shift_irq, shift_fiq;
298 uintptr_t reg;
299 uint64_t cpu;
300
301 rcar_lock_get();
302
303 cpu = mpidr & MPIDR_CPU_MASK;
304 c = rcar_pwrc_get_mpidr_cluster(mpidr);
305 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57;
306
307 shift_irq = WUP_IRQ_SHIFT + cpu;
308 shift_fiq = WUP_FIQ_SHIFT + cpu;
309
310 mmio_write_32(reg, ((uint32_t) 1 << shift_irq) |
311 ((uint32_t) 1 << shift_fiq));
312 rcar_lock_release();
313}
314
315void rcar_pwrc_clusteroff(uint64_t mpidr)
316{
317 uint32_t c, product, cut, reg;
318 uintptr_t dst;
319
320 rcar_lock_get();
321
322 reg = mmio_read_32(RCAR_PRR);
323 product = reg & RCAR_PRODUCT_MASK;
324 cut = reg & RCAR_CUT_MASK;
325
326 c = rcar_pwrc_get_mpidr_cluster(mpidr);
327 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
328
329 if (RCAR_PRODUCT_M3 == product && cut <= RCAR_M3_CUT_VER11)
330 goto done;
331
332 if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20)
333 goto done;
334
335 /* all of the CPUs in the cluster is in the CoreStandby mode */
336 mmio_write_32(dst, MODE_L2_DOWN);
337done:
338 rcar_lock_release();
339}
340
341#if !PMIC_ROHM_BD9571
342void rcar_pwrc_system_reset(void)
343{
344 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET);
345}
346#endif /* PMIC_ROHM_BD9571 */
347
348#define RST_CA53_CPU0_BARH (0xE6160080U)
349#define RST_CA53_CPU0_BARL (0xE6160084U)
350#define RST_CA57_CPU0_BARH (0xE61600C0U)
351#define RST_CA57_CPU0_BARL (0xE61600C4U)
352
353void rcar_pwrc_setup(void)
354{
355 uintptr_t rst_barh;
356 uintptr_t rst_barl;
357 uint32_t i, j;
358 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF;
359
360 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
361 RCAR_CLUSTER_CA53,
362 RCAR_CLUSTER_CA57
363 };
364 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = {
365 RST_CA53_CPU0_BARH,
366 RST_CA57_CPU0_BARH
367 };
368 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = {
369 RST_CA53_CPU0_BARL,
370 RST_CA57_CPU0_BARL
371 };
372
373 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
374 rst_barh = reg_barh[i];
375 rst_barl = reg_barl[i];
376 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) {
377 mmio_write_32(rst_barh, 0);
378 mmio_write_32(rst_barl, (uint32_t) reset);
379 rst_barh += 0x10;
380 rst_barl += 0x10;
381 }
382 }
383
384 rcar_lock_init();
385}
386
387#if RCAR_SYSTEM_SUSPEND
388#define DBCAM_FLUSH(__bit) \
389do { \
390 ; \
391} while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0))
392
393
394static void __attribute__ ((section(".system_ram")))
395 rcar_pwrc_set_self_refresh(void)
396{
397 uint32_t reg = mmio_read_32(RCAR_PRR);
398 uint32_t cut, product;
399
400 product = reg & RCAR_PRODUCT_MASK;
401 cut = reg & RCAR_CUT_MASK;
402
403 if (product == RCAR_PRODUCT_M3)
404 goto self_refresh;
405
406 if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
407 goto self_refresh;
408
409 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
410
411self_refresh:
412
413 /* Set the Self-Refresh mode */
414 mmio_write_32(DBSC4_REG_DBACEN, 0);
415
416 if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
417 rcar_pwrc_micro_delay(100);
418 else if (product == RCAR_PRODUCT_H3) {
419 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
420 DBCAM_FLUSH(0);
421 DBCAM_FLUSH(1);
422 DBCAM_FLUSH(2);
423 DBCAM_FLUSH(3);
424 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
425 } else if (product == RCAR_PRODUCT_M3) {
426 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
427 DBCAM_FLUSH(0);
428 DBCAM_FLUSH(1);
429 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
430 } else {
431 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
432 DBCAM_FLUSH(0);
433 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
434 }
435
436 /* Set the SDRAM calibration configuration register */
437 mmio_write_32(DBSC4_REG_DBCALCNF, 0);
438
439 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
440 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
441 mmio_write_32(DBSC4_REG_DBCMD, reg);
442 while (mmio_read_32(DBSC4_REG_DBWAIT))
443 ;
444
445 /* Self-Refresh entry command */
446 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
447 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
448 mmio_write_32(DBSC4_REG_DBCMD, reg);
449 while (mmio_read_32(DBSC4_REG_DBWAIT))
450 ;
451
452 /* Mode Register Write command. (ODT disabled) */
453 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL |
454 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC;
455 mmio_write_32(DBSC4_REG_DBCMD, reg);
456 while (mmio_read_32(DBSC4_REG_DBWAIT))
457 ;
458
459 /* Power Down entry command */
460 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL |
461 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
462 mmio_write_32(DBSC4_REG_DBCMD, reg);
463 while (mmio_read_32(DBSC4_REG_DBWAIT))
464 ;
465
466 /* Set the auto-refresh enable register */
467 mmio_write_32(DBSC4_REG_DBRFEN, 0U);
468 rcar_pwrc_micro_delay(1U);
469
470 if (product == RCAR_PRODUCT_M3)
471 return;
472
473 if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
474 return;
475
476 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
477}
478
479static void __attribute__ ((section(".system_ram")))
480 rcar_pwrc_set_self_refresh_e3(void)
481{
482 uint32_t ddr_md;
483 uint32_t reg;
484
485 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0;
486
487 /* Write enable */
488 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
489 mmio_write_32(DBSC4_REG_DBACEN, 0);
490 DBCAM_FLUSH(0);
491
492 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL |
493 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL;
494 mmio_write_32(DBSC4_REG_DBCMD, reg);
495 while (mmio_read_32(DBSC4_REG_DBWAIT))
496 ;
497
498 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL |
499 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER;
500 mmio_write_32(DBSC4_REG_DBCMD, reg);
501 while (mmio_read_32(DBSC4_REG_DBWAIT))
502 ;
503
504 /* Set the auto-refresh enable register */
505 /* Set the ARFEN bit to 0 in the DBRFEN */
506 mmio_write_32(DBSC4_REG_DBRFEN, 0);
507
508 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS);
509
510 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0);
511 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0);
512
513 /* DDR_DXCCR */
514 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR);
515 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR);
516
517 /* DDR_PGCR1 */
518 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1);
519 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1);
520
521 /* DDR_ACIOCR1 */
522 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1);
523 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1);
524
525 /* DDR_ACIOCR3 */
526 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3);
527 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3);
528
529 /* DDR_ACIOCR5 */
530 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5);
531 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5);
532
533 /* DDR_DX0GCR2 */
534 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2);
535 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2);
536
537 /* DDR_DX1GCR2 */
538 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2);
539 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2);
540
541 /* DDR_DX2GCR2 */
542 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2);
543 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2);
544
545 /* DDR_DX3GCR2 */
546 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2);
547 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2);
548
549 /* DDR_ZQCR */
550 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR);
551
552 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ?
553 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 :
554 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1);
555
556 /* DDR_DX0GCR0 */
557 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0);
558 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0);
559
560 /* DDR_DX1GCR0 */
561 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0);
562 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0);
563
564 /* DDR_DX2GCR0 */
565 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0);
566 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0);
567
568 /* DDR_DX3GCR0 */
569 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0);
570 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0);
571
572 /* DDR_DX0GCR1 */
573 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1);
574 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1);
575
576 /* DDR_DX1GCR1 */
577 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1);
578 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1);
579
580 /* DDR_DX2GCR1 */
581 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1);
582 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1);
583
584 /* DDR_DX3GCR1 */
585 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1);
586 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1);
587
588 /* DDR_DX0GCR3 */
589 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3);
590 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3);
591
592 /* DDR_DX1GCR3 */
593 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3);
594 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3);
595
596 /* DDR_DX2GCR3 */
597 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3);
598 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3);
599
600 /* DDR_DX3GCR3 */
601 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3);
602 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3);
603
604 /* Write disable */
605 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
606}
607
608void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
609 rcar_pwrc_go_suspend_to_ram(void)
610{
611#if PMIC_ROHM_BD9571
612 int32_t rc = -1, qllm = -1;
613 uint8_t mode;
614 uint32_t i;
615#endif
616 uint32_t reg, product;
617
618 reg = mmio_read_32(RCAR_PRR);
619 product = reg & RCAR_PRODUCT_MASK;
620
621 if (product != RCAR_PRODUCT_E3)
622 rcar_pwrc_set_self_refresh();
623 else
624 rcar_pwrc_set_self_refresh_e3();
625
626#if PMIC_ROHM_BD9571
627 /* Set QLLM Cnt Disable */
628 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++)
629 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0);
630
631 /* Set trigger of power down to PMIV */
632 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) {
633 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode);
634 if (rc == 0) {
635 mode |= BIT_BKUP_CTRL_OUT;
636 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode);
637 }
638 }
639#endif
640 wfi();
641
642 while (1)
643 ;
644}
645
646void rcar_pwrc_set_suspend_to_ram(void)
647{
648 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram;
649 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE +
650 DEVICE_SRAM_STACK_SIZE);
651 uint32_t sctlr;
652
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200653 rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
654
655 /* disable MMU */
656 sctlr = (uint32_t) read_sctlr_el3();
657 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT;
658 write_sctlr_el3((uint64_t) sctlr);
659
660 rcar_pwrc_switch_stack(jump, stack, NULL);
661}
662
663void rcar_pwrc_init_suspend_to_ram(void)
664{
665#if PMIC_ROHM_BD9571
666 uint8_t mode;
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200667
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200668 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
669 panic();
670
671 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT);
672 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode))
673 panic();
674#endif
675}
676
677void rcar_pwrc_suspend_to_ram(void)
678{
679#if RCAR_SYSTEM_RESET_KEEPON_DDR
680 int32_t error;
681
Jorge Ramirez-Ortiz5ff5eee2018-09-23 09:41:10 +0200682 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
683 if (error) {
684 ERROR("Failed send KEEP10 init ret=%d \n", error);
685 return;
686 }
687#endif
688 rcar_pwrc_set_suspend_to_ram();
689}
690#endif
691
692void rcar_pwrc_code_copy_to_system_ram(void)
693{
694 int ret __attribute__ ((unused)); /* in assert */
695 uint32_t attr;
696 struct device_sram_t {
697 uintptr_t base;
698 size_t len;
699 } sram = {
700 .base = (uintptr_t) DEVICE_SRAM_BASE,
701 .len = DEVICE_SRAM_SIZE,
702 };
703 struct ddr_code_t {
704 void *base;
705 size_t len;
706 } code = {
707 .base = (void *) SRAM_COPY_START,
708 .len = SYSTEM_RAM_END - SYSTEM_RAM_START,
709 };
710
711 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER;
712 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
713 assert(ret == 0);
714
715 memcpy((void *)sram.base, code.base, code.len);
716 flush_dcache_range((uint64_t) sram.base, code.len);
717
718 /* Invalidate instruction cache */
719 plat_invalidate_icache();
720 dsb();
721 isb();
722
723 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE;
724 ret = xlat_change_mem_attributes(sram.base, sram.len, attr);
725 assert(ret == 0);
726}
727
728uint32_t rcar_pwrc_get_cluster(void)
729{
730 uint32_t reg;
731
732 reg = mmio_read_32(RCAR_PRR);
733
734 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
735 return RCAR_CLUSTER_CA57;
736
737 if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
738 return RCAR_CLUSTER_CA53;
739
740 return RCAR_CLUSTER_A53A57;
741}
742
743uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
744{
745 uint32_t c = rcar_pwrc_get_cluster();
746
747 if (IS_A53A57(c)) {
748 if (mpidr & MPIDR_CLUSTER_MASK)
749 return RCAR_CLUSTER_CA53;
750
751 return RCAR_CLUSTER_CA57;
752 }
753
754 return c;
755}
756
757uint32_t rcar_pwrc_get_cpu_num(uint32_t c)
758{
759 uint32_t reg = mmio_read_32(RCAR_PRR);
760 uint32_t count = 0, i;
761
762 if (IS_A53A57(c) || IS_CA53(c)) {
763 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX)))
764 goto count_ca57;
765
766 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) {
767 if (reg & (1 << (STATE_CA53_CPU + i)))
768 continue;
769 count++;
770 }
771 }
772
773count_ca57:
774 if (IS_A53A57(c) || IS_CA57(c)) {
775 if (reg & (1 << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX)))
776 goto done;
777
778 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) {
779 if (reg & (1 << (STATE_CA57_CPU + i)))
780 continue;
781 count++;
782 }
783 }
784
785done:
786 return count;
787}