Tejas Patel | 354fe57 | 2018-12-14 00:55:37 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, Xilinx, Inc. All rights reserved. |
Jay Buddhabhatti | 26e138a | 2022-12-21 23:03:35 -0800 | [diff] [blame] | 3 | * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. |
Tejas Patel | 354fe57 | 2018-12-14 00:55:37 -0800 | [diff] [blame] | 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | /* Versal PM nodes enums and defines */ |
| 9 | |
| 10 | #ifndef PM_NODE_H |
| 11 | #define PM_NODE_H |
| 12 | |
| 13 | /********************************************************************* |
| 14 | * Macro definitions |
| 15 | ********************************************************************/ |
| 16 | |
| 17 | #define NODE_CLASS_SHIFT 26U |
| 18 | #define NODE_SUBCLASS_SHIFT 20U |
| 19 | #define NODE_TYPE_SHIFT 14U |
| 20 | #define NODE_INDEX_SHIFT 0U |
| 21 | #define NODE_CLASS_MASK_BITS 0x3F |
| 22 | #define NODE_SUBCLASS_MASK_BITS 0x3F |
| 23 | #define NODE_TYPE_MASK_BITS 0x3F |
| 24 | #define NODE_INDEX_MASK_BITS 0x3FFF |
| 25 | #define NODE_CLASS_MASK (NODE_CLASS_MASK_BITS << NODE_CLASS_SHIFT) |
| 26 | #define NODE_SUBCLASS_MASK (NODE_SUBCLASS_MASK_BITS << NODE_SUBCLASS_SHIFT) |
| 27 | #define NODE_TYPE_MASK (NODE_TYPE_MASK_BITS << NODE_TYPE_SHIFT) |
| 28 | #define NODE_INDEX_MASK (NODE_INDEX_MASK_BITS << NODE_INDEX_SHIFT) |
| 29 | |
| 30 | #define NODEID(CLASS, SUBCLASS, TYPE, INDEX) \ |
| 31 | ((((CLASS) & NODE_CLASS_MASK_BITS) << NODE_CLASS_SHIFT) | \ |
| 32 | (((SUBCLASS) & NODE_SUBCLASS_MASK_BITS) << NODE_SUBCLASS_SHIFT) | \ |
| 33 | (((TYPE) & NODE_TYPE_MASK_BITS) << NODE_TYPE_SHIFT) | \ |
| 34 | (((INDEX) & NODE_INDEX_MASK_BITS) << NODE_INDEX_SHIFT)) |
| 35 | |
| 36 | #define NODECLASS(ID) (((ID) & NODE_CLASS_MASK) >> NODE_CLASS_SHIFT) |
| 37 | #define NODESUBCLASS(ID) (((ID) & NODE_SUBCLASS_MASK) >> \ |
| 38 | NODE_SUBCLASS_SHIFT) |
| 39 | #define NODETYPE(ID) (((ID) & NODE_TYPE_MASK) >> NODE_TYPE_SHIFT) |
| 40 | #define NODEINDEX(ID) (((ID) & NODE_INDEX_MASK) >> NODE_INDEX_SHIFT) |
| 41 | |
| 42 | /********************************************************************* |
| 43 | * Enum definitions |
| 44 | ********************************************************************/ |
| 45 | |
| 46 | /* Node class types */ |
| 47 | enum pm_node_class { |
| 48 | XPM_NODECLASS_MIN, |
| 49 | |
| 50 | XPM_NODECLASS_POWER, |
| 51 | XPM_NODECLASS_CLOCK, |
| 52 | XPM_NODECLASS_RESET, |
| 53 | XPM_NODECLASS_MEMIC, |
| 54 | XPM_NODECLASS_STMIC, |
| 55 | XPM_NODECLASS_DEVICE, |
| 56 | |
| 57 | XPM_NODECLASS_MAX |
| 58 | }; |
| 59 | |
| 60 | enum pm_device_node_subclass { |
| 61 | /* Device types */ |
| 62 | XPM_NODESUBCL_DEV_CORE = 1, |
| 63 | XPM_NODESUBCL_DEV_PERIPH, |
| 64 | XPM_NODESUBCL_DEV_MEM, |
| 65 | XPM_NODESUBCL_DEV_SOC, |
| 66 | XPM_NODESUBCL_DEV_MEM_CTRLR, |
| 67 | XPM_NODESUBCL_DEV_PHY, |
| 68 | }; |
| 69 | |
| 70 | enum pm_device_node_type { |
| 71 | /* Device types */ |
| 72 | XPM_NODETYPE_DEV_CORE_PMC = 1, |
| 73 | XPM_NODETYPE_DEV_CORE_PSM, |
| 74 | XPM_NODETYPE_DEV_CORE_APU, |
| 75 | XPM_NODETYPE_DEV_CORE_RPU, |
| 76 | XPM_NODETYPE_DEV_OCM, |
| 77 | XPM_NODETYPE_DEV_TCM, |
| 78 | XPM_NODETYPE_DEV_L2CACHE, |
| 79 | XPM_NODETYPE_DEV_DDR, |
| 80 | XPM_NODETYPE_DEV_PERIPH, |
| 81 | XPM_NODETYPE_DEV_SOC, |
| 82 | XPM_NODETYPE_DEV_GT, |
| 83 | }; |
| 84 | |
| 85 | /* Device node Indexes */ |
| 86 | enum pm_device_node_idx { |
| 87 | /* Device nodes */ |
| 88 | XPM_NODEIDX_DEV_MIN, |
| 89 | |
| 90 | /* Processor devices */ |
| 91 | XPM_NODEIDX_DEV_PMC_PROC, |
| 92 | XPM_NODEIDX_DEV_PSM_PROC, |
| 93 | XPM_NODEIDX_DEV_ACPU_0, |
| 94 | XPM_NODEIDX_DEV_ACPU_1, |
| 95 | XPM_NODEIDX_DEV_RPU0_0, |
| 96 | XPM_NODEIDX_DEV_RPU0_1, |
| 97 | |
| 98 | /* Memory devices */ |
| 99 | XPM_NODEIDX_DEV_OCM_0, |
| 100 | XPM_NODEIDX_DEV_OCM_1, |
| 101 | XPM_NODEIDX_DEV_OCM_2, |
| 102 | XPM_NODEIDX_DEV_OCM_3, |
| 103 | XPM_NODEIDX_DEV_TCM_0_A, |
| 104 | XPM_NODEIDX_DEV_TCM_0_B, |
| 105 | XPM_NODEIDX_DEV_TCM_1_A, |
| 106 | XPM_NODEIDX_DEV_TCM_1_B, |
| 107 | XPM_NODEIDX_DEV_L2_BANK_0, |
| 108 | XPM_NODEIDX_DEV_DDR_0, |
| 109 | XPM_NODEIDX_DEV_DDR_1, |
| 110 | XPM_NODEIDX_DEV_DDR_2, |
| 111 | XPM_NODEIDX_DEV_DDR_3, |
| 112 | XPM_NODEIDX_DEV_DDR_4, |
| 113 | XPM_NODEIDX_DEV_DDR_5, |
| 114 | XPM_NODEIDX_DEV_DDR_6, |
| 115 | XPM_NODEIDX_DEV_DDR_7, |
| 116 | |
| 117 | /* LPD Peripheral devices */ |
| 118 | XPM_NODEIDX_DEV_USB_0, |
| 119 | XPM_NODEIDX_DEV_GEM_0, |
| 120 | XPM_NODEIDX_DEV_GEM_1, |
| 121 | XPM_NODEIDX_DEV_SPI_0, |
| 122 | XPM_NODEIDX_DEV_SPI_1, |
| 123 | XPM_NODEIDX_DEV_I2C_0, |
| 124 | XPM_NODEIDX_DEV_I2C_1, |
| 125 | XPM_NODEIDX_DEV_CAN_FD_0, |
| 126 | XPM_NODEIDX_DEV_CAN_FD_1, |
| 127 | XPM_NODEIDX_DEV_UART_0, |
| 128 | XPM_NODEIDX_DEV_UART_1, |
| 129 | XPM_NODEIDX_DEV_GPIO, |
| 130 | XPM_NODEIDX_DEV_TTC_0, |
| 131 | XPM_NODEIDX_DEV_TTC_1, |
| 132 | XPM_NODEIDX_DEV_TTC_2, |
| 133 | XPM_NODEIDX_DEV_TTC_3, |
| 134 | XPM_NODEIDX_DEV_SWDT_LPD, |
| 135 | |
| 136 | /* FPD Peripheral devices */ |
| 137 | XPM_NODEIDX_DEV_SWDT_FPD, |
| 138 | |
| 139 | /* PMC Peripheral devices */ |
| 140 | XPM_NODEIDX_DEV_OSPI, |
| 141 | XPM_NODEIDX_DEV_QSPI, |
| 142 | XPM_NODEIDX_DEV_GPIO_PMC, |
| 143 | XPM_NODEIDX_DEV_I2C_PMC, |
| 144 | XPM_NODEIDX_DEV_SDIO_0, |
| 145 | XPM_NODEIDX_DEV_SDIO_1, |
| 146 | |
| 147 | XPM_NODEIDX_DEV_PL_0, |
| 148 | XPM_NODEIDX_DEV_PL_1, |
| 149 | XPM_NODEIDX_DEV_PL_2, |
| 150 | XPM_NODEIDX_DEV_PL_3, |
| 151 | XPM_NODEIDX_DEV_RTC, |
| 152 | XPM_NODEIDX_DEV_ADMA_0, |
| 153 | XPM_NODEIDX_DEV_ADMA_1, |
| 154 | XPM_NODEIDX_DEV_ADMA_2, |
| 155 | XPM_NODEIDX_DEV_ADMA_3, |
| 156 | XPM_NODEIDX_DEV_ADMA_4, |
| 157 | XPM_NODEIDX_DEV_ADMA_5, |
| 158 | XPM_NODEIDX_DEV_ADMA_6, |
| 159 | XPM_NODEIDX_DEV_ADMA_7, |
| 160 | XPM_NODEIDX_DEV_IPI_0, |
| 161 | XPM_NODEIDX_DEV_IPI_1, |
| 162 | XPM_NODEIDX_DEV_IPI_2, |
| 163 | XPM_NODEIDX_DEV_IPI_3, |
| 164 | XPM_NODEIDX_DEV_IPI_4, |
| 165 | XPM_NODEIDX_DEV_IPI_5, |
| 166 | XPM_NODEIDX_DEV_IPI_6, |
| 167 | |
| 168 | /* Entire SoC */ |
| 169 | XPM_NODEIDX_DEV_SOC, |
| 170 | |
| 171 | /* DDR memory controllers */ |
| 172 | XPM_NODEIDX_DEV_DDRMC_0, |
| 173 | XPM_NODEIDX_DEV_DDRMC_1, |
| 174 | XPM_NODEIDX_DEV_DDRMC_2, |
| 175 | XPM_NODEIDX_DEV_DDRMC_3, |
| 176 | |
| 177 | /* GT devices */ |
| 178 | XPM_NODEIDX_DEV_GT_0, |
| 179 | XPM_NODEIDX_DEV_GT_1, |
| 180 | XPM_NODEIDX_DEV_GT_2, |
| 181 | XPM_NODEIDX_DEV_GT_3, |
| 182 | XPM_NODEIDX_DEV_GT_4, |
| 183 | XPM_NODEIDX_DEV_GT_5, |
| 184 | XPM_NODEIDX_DEV_GT_6, |
| 185 | XPM_NODEIDX_DEV_GT_7, |
| 186 | XPM_NODEIDX_DEV_GT_8, |
| 187 | XPM_NODEIDX_DEV_GT_9, |
| 188 | XPM_NODEIDX_DEV_GT_10, |
| 189 | |
| 190 | XPM_NODEIDX_DEV_MAX |
| 191 | }; |
| 192 | |
| 193 | #endif /* PM_NODE_H */ |