johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 2 | * Copyright (c) 2022, ARM Limited. All rights reserved. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a510.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 16 | #error "Cortex-A510 must be compiled with HW_ASSISTED_COHERENCY enabled" |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 21 | #error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 22 | #endif |
| 23 | |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 24 | /* -------------------------------------------------- |
| 25 | * Errata Workaround for Cortex-A510 Errata #1922240. |
| 26 | * This applies only to revision r0p0 (fixed in r0p1) |
| 27 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 28 | * Shall clobber: x0, x1, x17 |
| 29 | * -------------------------------------------------- |
| 30 | */ |
| 31 | func errata_cortex_a510_1922240_wa |
| 32 | /* Check workaround compatibility. */ |
| 33 | mov x17, x30 |
| 34 | bl check_errata_1922240 |
| 35 | cbz x0, 1f |
| 36 | |
| 37 | /* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */ |
| 38 | mrs x0, CORTEX_A510_CMPXACTLR_EL1 |
| 39 | mov x1, #3 |
| 40 | bfi x0, x1, #10, #2 |
| 41 | msr CORTEX_A510_CMPXACTLR_EL1, x0 |
| 42 | |
| 43 | 1: |
| 44 | ret x17 |
| 45 | endfunc errata_cortex_a510_1922240_wa |
| 46 | |
| 47 | func check_errata_1922240 |
| 48 | /* Applies to r0p0 only */ |
| 49 | mov x1, #0x00 |
| 50 | b cpu_rev_var_ls |
| 51 | endfunc check_errata_1922240 |
| 52 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 53 | /* ---------------------------------------------------- |
| 54 | * HW will do the cache maintenance while powering down |
| 55 | * ---------------------------------------------------- |
| 56 | */ |
| 57 | func cortex_a510_core_pwr_dwn |
| 58 | /* --------------------------------------------------- |
| 59 | * Enable CPU power down bit in power control register |
| 60 | * --------------------------------------------------- |
| 61 | */ |
| 62 | mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 |
| 63 | orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 64 | msr CORTEX_A510_CPUPWRCTLR_EL1, x0 |
| 65 | isb |
| 66 | ret |
| 67 | endfunc cortex_a510_core_pwr_dwn |
| 68 | |
| 69 | /* |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 70 | * Errata printing function for Cortex-A510. Must follow AAPCS. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 71 | */ |
| 72 | #if REPORT_ERRATA |
| 73 | func cortex_a510_errata_report |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 74 | stp x8, x30, [sp, #-16]! |
| 75 | |
| 76 | bl cpu_get_rev_var |
| 77 | mov x8, x0 |
| 78 | |
| 79 | /* |
| 80 | * Report all errata. The revision-variant information is passed to |
| 81 | * checking functions of each errata. |
| 82 | */ |
| 83 | report_errata ERRATA_A510_1922240, cortex_a510, 1922240 |
| 84 | |
| 85 | ldp x8, x30, [sp], #16 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 86 | ret |
| 87 | endfunc cortex_a510_errata_report |
| 88 | #endif |
| 89 | |
| 90 | func cortex_a510_reset_func |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 91 | mov x19, x30 |
| 92 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 93 | /* Disable speculative loads */ |
| 94 | msr SSBS, xzr |
| 95 | isb |
johpow01 | de7b524 | 2022-01-04 16:15:18 -0600 | [diff] [blame^] | 96 | |
| 97 | /* Get the CPU revision and stash it in x18. */ |
| 98 | bl cpu_get_rev_var |
| 99 | mov x18, x0 |
| 100 | |
| 101 | #if ERRATA_A510_1922240 |
| 102 | mov x0, x18 |
| 103 | bl errata_cortex_a510_1922240_wa |
| 104 | #endif |
| 105 | |
| 106 | ret x19 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 107 | endfunc cortex_a510_reset_func |
| 108 | |
| 109 | /* --------------------------------------------- |
| 110 | * This function provides Cortex-A510 specific |
| 111 | * register information for crash reporting. |
| 112 | * It needs to return with x6 pointing to |
| 113 | * a list of register names in ascii and |
| 114 | * x8 - x15 having values of registers to be |
| 115 | * reported. |
| 116 | * --------------------------------------------- |
| 117 | */ |
| 118 | .section .rodata.cortex_a510_regs, "aS" |
| 119 | cortex_a510_regs: /* The ascii list of register names to be reported */ |
| 120 | .asciz "cpuectlr_el1", "" |
| 121 | |
| 122 | func cortex_a510_cpu_reg_dump |
| 123 | adr x6, cortex_a510_regs |
| 124 | mrs x8, CORTEX_A510_CPUECTLR_EL1 |
| 125 | ret |
| 126 | endfunc cortex_a510_cpu_reg_dump |
| 127 | |
| 128 | declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ |
| 129 | cortex_a510_reset_func, \ |
| 130 | cortex_a510_core_pwr_dwn |