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Varun Wadekar7a269e22015-06-10 14:04:32 +05301/*
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -08002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar7a269e22015-06-10 14:04:32 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar7a269e22015-06-10 14:04:32 +05305 */
6
Varun Wadekar7a269e22015-06-10 14:04:32 +05307#include <assert.h>
Varun Wadekar7a269e22015-06-10 14:04:32 +05308#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <common/runtime_svc.h>
15#include <lib/mmio.h>
16
Varun Wadekar7a269e22015-06-10 14:04:32 +053017#include <memctrl.h>
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -080018#include <tegra_platform.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010019#include <tegra_private.h>
Varun Wadekar7a269e22015-06-10 14:04:32 +053020
Varun Wadekar0f3baa02015-07-16 11:36:33 +053021/*******************************************************************************
Varun Wadekar923d04a2015-12-09 18:18:53 -080022 * Common Tegra SiP SMCs
Varun Wadekar0f3baa02015-07-16 11:36:33 +053023 ******************************************************************************/
Varun Wadekar7a269e22015-06-10 14:04:32 +053024#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
Varun Wadekardc799302015-12-28 16:36:42 -080025#define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005
26#define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -080027#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007
Varun Wadekar7a269e22015-06-10 14:04:32 +053028
29/*******************************************************************************
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -080030 * Fake system suspend mode control var
31 ******************************************************************************/
32extern uint8_t tegra_fake_system_suspend;
33
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -080034/*******************************************************************************
Varun Wadekar923d04a2015-12-09 18:18:53 -080035 * SoC specific SiP handler
36 ******************************************************************************/
37#pragma weak plat_sip_handler
Anthony Zhou035f24b2017-03-01 12:47:37 +080038int32_t plat_sip_handler(uint32_t smc_fid,
Varun Wadekar923d04a2015-12-09 18:18:53 -080039 uint64_t x1,
40 uint64_t x2,
41 uint64_t x3,
42 uint64_t x4,
Anthony Zhoue5bd3452017-03-01 12:47:37 +080043 const void *cookie,
Varun Wadekar923d04a2015-12-09 18:18:53 -080044 void *handle,
45 uint64_t flags)
46{
Anthony Zhoue5bd3452017-03-01 12:47:37 +080047 /* unused parameters */
48 (void)smc_fid;
49 (void)x1;
50 (void)x2;
51 (void)x3;
52 (void)x4;
53 (void)cookie;
54 (void)handle;
55 (void)flags;
56
Varun Wadekar923d04a2015-12-09 18:18:53 -080057 return -ENOTSUP;
58}
59
60/*******************************************************************************
Wayne Lin2330edd2016-03-31 13:49:09 -070061 * This function is responsible for handling all SiP calls
Varun Wadekar7a269e22015-06-10 14:04:32 +053062 ******************************************************************************/
Masahiro Yamada5ac9d962018-04-19 01:18:48 +090063uintptr_t tegra_sip_handler(uint32_t smc_fid,
64 u_register_t x1,
65 u_register_t x2,
66 u_register_t x3,
67 u_register_t x4,
68 void *cookie,
69 void *handle,
70 u_register_t flags)
Varun Wadekar7a269e22015-06-10 14:04:32 +053071{
Anthony Zhou4408e882017-07-07 14:29:51 +080072 uint32_t regval, local_x2_32 = (uint32_t)x2;
Anthony Zhoue5bd3452017-03-01 12:47:37 +080073 int32_t err;
Varun Wadekar7a269e22015-06-10 14:04:32 +053074
Varun Wadekar923d04a2015-12-09 18:18:53 -080075 /* Check if this is a SoC specific SiP */
76 err = plat_sip_handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags);
Anthony Zhou035f24b2017-03-01 12:47:37 +080077 if (err == 0) {
78
Varun Wadekar14f39572017-04-17 11:54:33 -070079 SMC_RET1(handle, (uint64_t)err);
Varun Wadekar923d04a2015-12-09 18:18:53 -080080
Anthony Zhou035f24b2017-03-01 12:47:37 +080081 } else {
Varun Wadekar7a269e22015-06-10 14:04:32 +053082
Anthony Zhou035f24b2017-03-01 12:47:37 +080083 switch (smc_fid) {
Varun Wadekar7a269e22015-06-10 14:04:32 +053084
Anthony Zhou035f24b2017-03-01 12:47:37 +080085 case TEGRA_SIP_NEW_VIDEOMEM_REGION:
Varun Wadekar0f3baa02015-07-16 11:36:33 +053086
Anthony Zhou035f24b2017-03-01 12:47:37 +080087 /*
88 * Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
89 * or falls outside of the valid DRAM range
90 */
Anthony Zhou4408e882017-07-07 14:29:51 +080091 err = bl31_check_ns_address(x1, local_x2_32);
Anthony Zhou035f24b2017-03-01 12:47:37 +080092 if (err != 0) {
93 SMC_RET1(handle, (uint64_t)err);
94 }
Varun Wadekara59a7c52017-04-26 08:31:50 -070095
Anthony Zhou035f24b2017-03-01 12:47:37 +080096 /*
97 * Check if Video Memory is aligned to 1MB.
98 */
Anthony Zhou4408e882017-07-07 14:29:51 +080099 if (((x1 & 0xFFFFFU) != 0U) || ((local_x2_32 & 0xFFFFFU) != 0U)) {
Anthony Zhou035f24b2017-03-01 12:47:37 +0800100 ERROR("Unaligned Video Memory base address!\n");
Anthony Zhou0e07e452017-07-26 17:16:54 +0800101 SMC_RET1(handle, (uint64_t)-ENOTSUP);
Anthony Zhou035f24b2017-03-01 12:47:37 +0800102 }
Varun Wadekar7a269e22015-06-10 14:04:32 +0530103
Anthony Zhou035f24b2017-03-01 12:47:37 +0800104 /*
105 * The GPU is the user of the Video Memory region. In order to
106 * transition to the new memory region smoothly, we program the
107 * new base/size ONLY if the GPU is in reset mode.
108 */
109 regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
110 TEGRA_GPU_RESET_REG_OFFSET);
Anthony Zhou0e07e452017-07-26 17:16:54 +0800111 if ((regval & GPU_RESET_BIT) == 0U) {
Anthony Zhou035f24b2017-03-01 12:47:37 +0800112 ERROR("GPU not in reset! Video Memory setup failed\n");
Anthony Zhou0e07e452017-07-26 17:16:54 +0800113 SMC_RET1(handle, (uint64_t)-ENOTSUP);
Anthony Zhou035f24b2017-03-01 12:47:37 +0800114 }
Varun Wadekar7a269e22015-06-10 14:04:32 +0530115
Anthony Zhou035f24b2017-03-01 12:47:37 +0800116 /* new video memory carveout settings */
Anthony Zhou4408e882017-07-07 14:29:51 +0800117 tegra_memctrl_videomem_setup(x1, local_x2_32);
Varun Wadekardc799302015-12-28 16:36:42 -0800118
Anthony Zhou035f24b2017-03-01 12:47:37 +0800119 SMC_RET1(handle, 0);
Varun Wadekardc799302015-12-28 16:36:42 -0800120
121 /*
Anthony Zhou035f24b2017-03-01 12:47:37 +0800122 * The NS world registers the address of its handler to be
123 * used for processing the FIQ. This is normally used by the
124 * NS FIQ debugger driver to detect system hangs by programming
125 * a watchdog timer to fire a FIQ interrupt.
Varun Wadekardc799302015-12-28 16:36:42 -0800126 */
Anthony Zhou035f24b2017-03-01 12:47:37 +0800127 case TEGRA_SIP_FIQ_NS_ENTRYPOINT:
Varun Wadekardc799302015-12-28 16:36:42 -0800128
Anthony Zhou035f24b2017-03-01 12:47:37 +0800129 if (x1 == 0U) {
130 SMC_RET1(handle, SMC_UNK);
131 }
Varun Wadekardc799302015-12-28 16:36:42 -0800132
Anthony Zhou035f24b2017-03-01 12:47:37 +0800133 /*
134 * TODO: Check if x1 contains a valid DRAM address
135 */
Varun Wadekardc799302015-12-28 16:36:42 -0800136
Anthony Zhou035f24b2017-03-01 12:47:37 +0800137 /* store the NS world's entrypoint */
138 tegra_fiq_set_ns_entrypoint(x1);
Varun Wadekardc799302015-12-28 16:36:42 -0800139
Anthony Zhou035f24b2017-03-01 12:47:37 +0800140 SMC_RET1(handle, 0);
Varun Wadekardc799302015-12-28 16:36:42 -0800141
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800142 /*
Anthony Zhou035f24b2017-03-01 12:47:37 +0800143 * The NS world's FIQ handler issues this SMC to get the NS EL1/EL0
144 * CPU context when the FIQ interrupt was triggered. This allows the
145 * NS world to understand the CPU state when the watchdog interrupt
146 * triggered.
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800147 */
Anthony Zhou035f24b2017-03-01 12:47:37 +0800148 case TEGRA_SIP_FIQ_NS_GET_CONTEXT:
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800149
Anthony Zhou035f24b2017-03-01 12:47:37 +0800150 /* retrieve context registers when FIQ triggered */
151 (void)tegra_fiq_get_intr_context();
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800152
Anthony Zhou035f24b2017-03-01 12:47:37 +0800153 SMC_RET0(handle);
154
155 case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND:
156 /*
157 * System suspend fake mode is set if we are on VDK and we make
158 * a debug SIP call. This mode ensures that we excercise debug
159 * path instead of the regular code path to suit the pre-silicon
160 * platform needs. These include replacing the call to WFI by
161 * a warm reset request.
162 */
163 if (tegra_platform_is_virt_dev_kit() != false) {
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800164
Anthony Zhou035f24b2017-03-01 12:47:37 +0800165 tegra_fake_system_suspend = 1;
166 SMC_RET1(handle, 0);
167 }
168
169 /*
170 * We return to the external world as if this SIP is not
171 * implemented in case, we are not running on VDK.
172 */
173 break;
174
175 default:
176 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
177 break;
178 }
Varun Wadekar7a269e22015-06-10 14:04:32 +0530179 }
180
181 SMC_RET1(handle, SMC_UNK);
182}
183
184/* Define a runtime service descriptor for fast SMC calls */
185DECLARE_RT_SVC(
Varun Wadekar923d04a2015-12-09 18:18:53 -0800186 tegra_sip_fast,
Varun Wadekar7a269e22015-06-10 14:04:32 +0530187
Anthony Zhoue5bd3452017-03-01 12:47:37 +0800188 (OEN_SIP_START),
189 (OEN_SIP_END),
190 (SMC_TYPE_FAST),
191 (NULL),
192 (tegra_sip_handler)
Varun Wadekar7a269e22015-06-10 14:04:32 +0530193);