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git01.mediatek.com / filogic / atf / bda11cb3b118c5f511b4d49ccba80a097cda4f97 / . / drivers / staging / renesas / rcar / qos / qos_init.c
blob: 1d1bcd59f15c2f6019650d2ffd3ccce0156e179e [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
9#include <common/debug.h>
10#include <lib/mmio.h>
11
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]12#include "qos_init.h"
13#include "qos_common.h"
14#if RCAR_LSI == RCAR_AUTO
15#include "H3/qos_init_h3_v10.h"
16#include "H3/qos_init_h3_v11.h"
17#include "H3/qos_init_h3_v20.h"
18#include "H3/qos_init_h3_v30.h"
19#include "M3/qos_init_m3_v10.h"
20#include "M3/qos_init_m3_v11.h"
21#include "M3N/qos_init_m3n_v10.h"
22#endif
23#if RCAR_LSI == RCAR_H3 /* H3 */
24#include "H3/qos_init_h3_v10.h"
25#include "H3/qos_init_h3_v11.h"
26#include "H3/qos_init_h3_v20.h"
27#include "H3/qos_init_h3_v30.h"
28#endif
29#if RCAR_LSI == RCAR_H3N /* H3 */
30#include "H3/qos_init_h3n_v30.h"
31#endif
32#if RCAR_LSI == RCAR_M3 /* M3 */
33#include "M3/qos_init_m3_v10.h"
34#include "M3/qos_init_m3_v11.h"
35#endif
36#if RCAR_LSI == RCAR_M3N /* M3N */
37#include "M3N/qos_init_m3n_v10.h"
38#endif
39#if RCAR_LSI == RCAR_E3 /* E3 */
40#include "E3/qos_init_e3_v10.h"
41#endif
42
43 /* Product Register */
44#define PRR (0xFFF00044U)
45#define PRR_PRODUCT_MASK (0x00007F00U)
46#define PRR_CUT_MASK (0x000000FFU)
47#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */
48#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */
49#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */
50#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */
51#define PRR_PRODUCT_10 (0x00U)
52#define PRR_PRODUCT_11 (0x01U)
53#define PRR_PRODUCT_20 (0x10U)
54#define PRR_PRODUCT_30 (0x20U)
55
56#if !(RCAR_LSI == RCAR_E3)
57
58#define DRAM_CH_CNT 0x04
59uint32_t qos_init_ddr_ch;
60uint8_t qos_init_ddr_phyvalid;
61
62#endif
63
64#define PRR_PRODUCT_ERR(reg) \
65 do{ \
66 ERROR("LSI Product ID(PRR=0x%x) QoS " \
67 "initialize not supported.\n",reg); \
68 panic(); \
69 } while(0)
70
71#define PRR_CUT_ERR(reg) \
72 do{ \
73 ERROR("LSI Cut ID(PRR=0x%x) QoS " \
74 "initialize not supported.\n",reg); \
75 panic(); \
76 } while(0)
77
78void rcar_qos_init(void)
79{
80 uint32_t reg;
81#if !(RCAR_LSI == RCAR_E3)
82 uint32_t i;
83
84 qos_init_ddr_ch = 0;
85 qos_init_ddr_phyvalid = get_boardcnf_phyvalid();
86 for (i = 0; i < DRAM_CH_CNT; i++) {
87 if ((qos_init_ddr_phyvalid & (1 << i))) {
88 qos_init_ddr_ch++;
89 }
90 }
91#endif
92
93 reg = mmio_read_32(PRR);
94#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
95 switch (reg & PRR_PRODUCT_MASK) {
96 case PRR_PRODUCT_H3:
97#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
98 switch (reg & PRR_CUT_MASK) {
99 case PRR_PRODUCT_10:
100 qos_init_h3_v10();
101 break;
102 case PRR_PRODUCT_11:
103 qos_init_h3_v11();
104 break;
105 case PRR_PRODUCT_20:
106 qos_init_h3_v20();
107 break;
108 case PRR_PRODUCT_30:
109 default:
110 qos_init_h3_v30();
111 break;
112 }
113#elif (RCAR_LSI == RCAR_H3N)
114 switch (reg & PRR_CUT_MASK) {
115 case PRR_PRODUCT_30:
116 default:
117 qos_init_h3n_v30();
118 break;
119 }
120#else
121 PRR_PRODUCT_ERR(reg);
122#endif
123 break;
124 case PRR_PRODUCT_M3:
125#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
126 switch (reg & PRR_CUT_MASK) {
127 case PRR_PRODUCT_10:
128 qos_init_m3_v10();
129 break;
130 case PRR_PRODUCT_20: /* M3 Cut 11 */
131 default:
132 qos_init_m3_v11();
133 break;
134 }
135#else
136 PRR_PRODUCT_ERR(reg);
137#endif
138 break;
139 case PRR_PRODUCT_M3N:
140#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
141 switch (reg & PRR_CUT_MASK) {
142 case PRR_PRODUCT_10:
143 default:
144 qos_init_m3n_v10();
145 break;
146 }
147#else
148 PRR_PRODUCT_ERR(reg);
149#endif
150 break;
151 case PRR_PRODUCT_E3:
152#if (RCAR_LSI == RCAR_E3)
153 switch (reg & PRR_CUT_MASK) {
154 case PRR_PRODUCT_10:
155 default:
156 qos_init_e3_v10();
157 break;
158 }
159#else
160 PRR_PRODUCT_ERR(reg);
161#endif
162 break;
163 default:
164 PRR_PRODUCT_ERR(reg);
165 break;
166 }
167#else
168#if RCAR_LSI == RCAR_H3 /* H3 */
169#if RCAR_LSI_CUT == RCAR_CUT_10
170 /* H3 Cut 10 */
171 if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10)
172 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
173 PRR_PRODUCT_ERR(reg);
174 }
175 qos_init_h3_v10();
176#elif RCAR_LSI_CUT == RCAR_CUT_11
177 /* H3 Cut 11 */
178 if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11)
179 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
180 PRR_PRODUCT_ERR(reg);
181 }
182 qos_init_h3_v11();
183#elif RCAR_LSI_CUT == RCAR_CUT_20
184 /* H3 Cut 20 */
185 if ((PRR_PRODUCT_H3 | PRR_PRODUCT_20)
186 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
187 PRR_PRODUCT_ERR(reg);
188 }
189 qos_init_h3_v20();
190#else
191 /* H3 Cut 30 or later */
192 if ((PRR_PRODUCT_H3)
193 != (reg & (PRR_PRODUCT_MASK))) {
194 PRR_PRODUCT_ERR(reg);
195 }
196 qos_init_h3_v30();
197#endif
198#elif RCAR_LSI == RCAR_H3N /* H3 */
199 /* H3N Cut 30 or later */
200 if ((PRR_PRODUCT_H3)
201 != (reg & (PRR_PRODUCT_MASK))) {
202 PRR_PRODUCT_ERR(reg);
203 }
204 qos_init_h3n_v30();
205#elif RCAR_LSI == RCAR_M3 /* M3 */
206#if RCAR_LSI_CUT == RCAR_CUT_10
207 /* M3 Cut 10 */
208 if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10)
209 != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) {
210 PRR_PRODUCT_ERR(reg);
211 }
212 qos_init_m3_v10();
213#else
214 /* M3 Cut 11 or later */
215 if ((PRR_PRODUCT_M3)
216 != (reg & (PRR_PRODUCT_MASK))) {
217 PRR_PRODUCT_ERR(reg);
218 }
219 qos_init_m3_v11();
220#endif
221#elif RCAR_LSI == RCAR_M3N /* M3N */
222 /* M3N Cut 10 or later */
223 if ((PRR_PRODUCT_M3N)
224 != (reg & (PRR_PRODUCT_MASK))) {
225 PRR_PRODUCT_ERR(reg);
226 }
227 qos_init_m3n_v10();
228#elif RCAR_LSI == RCAR_E3 /* E3 */
229 /* E3 Cut 10 or later */
230 if ((PRR_PRODUCT_E3)
231 != (reg & (PRR_PRODUCT_MASK))) {
232 PRR_PRODUCT_ERR(reg);
233 }
234 qos_init_e3_v10();
235#else
236#error "Don't have QoS initialize routine(Unknown chip)."
237#endif
238#endif
239}
240
241uint32_t get_refperiod(void)
242{
243 uint32_t refperiod = QOSWT_WTSET0_CYCLE;
244
245#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
246 uint32_t reg;
247
248 reg = mmio_read_32(PRR);
249 switch (reg & PRR_PRODUCT_MASK) {
250#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3)
251 case PRR_PRODUCT_H3:
252 switch (reg & PRR_CUT_MASK) {
253 case PRR_PRODUCT_10:
254 case PRR_PRODUCT_11:
255 break;
256 case PRR_PRODUCT_20:
257 refperiod = QOSWT_WTSET0_CYCLE_H3_20;
258 break;
259 case PRR_PRODUCT_30:
260 default:
261 refperiod = QOSWT_WTSET0_CYCLE_H3_30;
262 break;
263 }
264 break;
265#elif (RCAR_LSI == RCAR_H3N)
266 case PRR_PRODUCT_H3:
267 switch (reg & PRR_CUT_MASK) {
268 case PRR_PRODUCT_30:
269 default:
270 refperiod = QOSWT_WTSET0_CYCLE_H3N;
271 break;
272 }
273 break;
274#endif
275#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
276 case PRR_PRODUCT_M3:
277 switch (reg & PRR_CUT_MASK) {
278 case PRR_PRODUCT_10:
279 break;
280 case PRR_PRODUCT_20: /* M3 Cut 11 */
281 default:
282 refperiod = QOSWT_WTSET0_CYCLE_M3_11;
283 break;
284 }
285 break;
286#endif
287#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
288 case PRR_PRODUCT_M3N:
289 refperiod = QOSWT_WTSET0_CYCLE_M3N;
290 break;
291#endif
292#if (RCAR_LSI == RCAR_E3)
293 case PRR_PRODUCT_E3:
294 refperiod = QOSWT_WTSET0_CYCLE_E3;
295 break;
296#endif
297 default:
298 break;
299 }
300#elif RCAR_LSI == RCAR_H3
301#if RCAR_LSI_CUT == RCAR_CUT_10
302 /* H3 Cut 10 */
303#elif RCAR_LSI_CUT == RCAR_CUT_11
304 /* H3 Cut 11 */
305#elif RCAR_LSI_CUT == RCAR_CUT_20
306 /* H3 Cut 20 */
307 refperiod = QOSWT_WTSET0_CYCLE_H3_20;
308#else
309 /* H3 Cut 30 or later */
310 refperiod = QOSWT_WTSET0_CYCLE_H3_30;
311#endif
312#elif RCAR_LSI == RCAR_H3N
313 /* H3N Cut 30 or later */
314 refperiod = QOSWT_WTSET0_CYCLE_H3N;
315#elif RCAR_LSI == RCAR_M3
316#if RCAR_LSI_CUT == RCAR_CUT_10
317 /* M3 Cut 10 */
318#else
319 /* M3 Cut 11 or later */
320 refperiod = QOSWT_WTSET0_CYCLE_M3_11;
321#endif
322#elif RCAR_LSI == RCAR_M3N /* for M3N */
323 refperiod = QOSWT_WTSET0_CYCLE_M3N;
324#elif RCAR_LSI == RCAR_E3 /* for E3 */
325 refperiod = QOSWT_WTSET0_CYCLE_E3;
326#endif
327
328 return refperiod;
329}