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Mikael Olsson7da66192021-02-12 17:30:22 +01001/*
Joshua Pimm6bc80672022-10-19 15:46:27 +01002 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Mikael Olsson7da66192021-02-12 17:30:22 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef ETHOSN_H
8#define ETHOSN_H
9
10#include <lib/smccc.h>
11
12/* Function numbers */
13#define ETHOSN_FNUM_VERSION U(0x50)
14#define ETHOSN_FNUM_IS_SEC U(0x51)
15#define ETHOSN_FNUM_HARD_RESET U(0x52)
16#define ETHOSN_FNUM_SOFT_RESET U(0x53)
17/* 0x54-0x5F reserved for future use */
18
19/* SMC64 function IDs */
20#define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num)
21#define ETHOSN_FID_VERSION_64 ETHOSN_FID_64(ETHOSN_FNUM_VERSION)
22#define ETHOSN_FID_IS_SEC_64 ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC)
23#define ETHOSN_FID_HARD_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET)
24#define ETHOSN_FID_SOFT_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET)
25
26/* SMC32 function IDs */
27#define ETHOSN_FID_32(func_num) U(0x82000000 | func_num)
28#define ETHOSN_FID_VERSION_32 ETHOSN_FID_32(ETHOSN_FNUM_VERSION)
29#define ETHOSN_FID_IS_SEC_32 ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC)
30#define ETHOSN_FID_HARD_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET)
31#define ETHOSN_FID_SOFT_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET)
32
33#define ETHOSN_NUM_SMC_CALLS 8
34
35/* Macro to identify function calls */
36#define ETHOSN_FID_MASK U(0xFFF0)
37#define ETHOSN_FID_VALUE U(0x50)
38#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
39
40/* Service version */
Mikael Olsson3288b462022-08-15 17:12:58 +020041#define ETHOSN_VERSION_MAJOR U(2)
Joshua Pimm6bc80672022-10-19 15:46:27 +010042#define ETHOSN_VERSION_MINOR U(1)
Mikael Olsson7da66192021-02-12 17:30:22 +010043
44/* Return codes for function calls */
45#define ETHOSN_SUCCESS 0
46#define ETHOSN_NOT_SUPPORTED -1
47/* -2 Reserved for NOT_REQUIRED */
Joshua Pimm6bc80672022-10-19 15:46:27 +010048#define ETHOSN_INVALID_PARAMETER -3
Mikael Olsson7da66192021-02-12 17:30:22 +010049#define ETHOSN_FAILURE -4
Laurent Carlier5205df22021-09-16 15:10:35 +010050#define ETHOSN_UNKNOWN_CORE_ADDRESS -5
Mikael Olsson3288b462022-08-15 17:12:58 +020051#define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6
Mikael Olsson7da66192021-02-12 17:30:22 +010052
Joshua Pimm6bc80672022-10-19 15:46:27 +010053/*
54 * Argument types for soft and hard resets to indicate whether to reset
55 * and reconfigure the NPU or only halt it
56 */
57#define ETHOSN_RESET_TYPE_FULL U(0)
58#define ETHOSN_RESET_TYPE_HALT U(1)
59
Mikael Olsson7da66192021-02-12 17:30:22 +010060uintptr_t ethosn_smc_handler(uint32_t smc_fid,
Laurent Carlier5205df22021-09-16 15:10:35 +010061 u_register_t core_addr,
Mikael Olsson3288b462022-08-15 17:12:58 +020062 u_register_t asset_alloc_idx,
Joshua Pimm6bc80672022-10-19 15:46:27 +010063 u_register_t reset_type,
Mikael Olsson7da66192021-02-12 17:30:22 +010064 u_register_t x4,
65 void *cookie,
66 void *handle,
67 u_register_t flags);
68
69#endif /* ETHOSN_H */