Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / b0eb988b1d8ff6d596731b016e63b7aa9b0adc08 / . / drivers / staging / renesas / rcar / qos / H3 / qos_init_h3_v10.c
blob: 29ef0b6db2b4d5ee6f9e14162f4016a252ac71aa [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]2 * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
9#include <common/debug.h>
10
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]11#include "../qos_common.h"
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]12#include "../qos_reg.h"
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]13#include "qos_init_h3_v10.h"
14
15#define RCAR_QOS_VERSION "rev.0.36"
16
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]17#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
18static const mstat_slot_t mstat_fix[] = {
19 {0x0000U, 0x0000000000000000UL},
20 {0x0008U, 0x0000000000000000UL},
21 {0x0010U, 0x0000000000000000UL},
22 {0x0018U, 0x0000000000000000UL},
23 {0x0020U, 0x0000000000000000UL},
24 {0x0028U, 0x0000000000000000UL},
25 {0x0030U, 0x0000000000000000UL},
26 {0x0038U, 0x0000000000000000UL},
27 {0x0040U, 0x00140C050000FFFFUL},
28 {0x0048U, 0x0000000000000000UL},
29 {0x0050U, 0x0000000000000000UL},
30 {0x0058U, 0x001404030000FFFFUL},
31 {0x0060U, 0x001408060000FFFFUL},
32 {0x0068U, 0x0000000000000000UL},
33 {0x0070U, 0x0000000000000000UL},
34 {0x0078U, 0x0000000000000000UL},
35 {0x0080U, 0x0000000000000000UL},
36 {0x0088U, 0x00140C050000FFFFUL},
37 {0x0090U, 0x001408060000FFFFUL},
38 {0x0098U, 0x001404020000FFFFUL},
39 {0x00A0U, 0x0000000000000000UL},
40 {0x00A8U, 0x0000000000000000UL},
41 {0x00B0U, 0x0000000000000000UL},
42 {0x00B8U, 0x0000000000000000UL},
43 {0x00C0U, 0x0000000000000000UL},
44 {0x00C8U, 0x0000000000000000UL},
45 {0x00D0U, 0x0000000000000000UL},
46 {0x00D8U, 0x0000000000000000UL},
47 {0x00E0U, 0x0000000000000000UL},
48 {0x00E8U, 0x0000000000000000UL},
49 {0x00F0U, 0x0000000000000000UL},
50 {0x00F8U, 0x0000000000000000UL},
51 {0x0100U, 0x0000000000000000UL},
52 {0x0108U, 0x0000000000000000UL},
53 {0x0110U, 0x0000000000000000UL},
54 {0x0118U, 0x0000000000000000UL},
55 {0x0120U, 0x0000000000000000UL},
56 {0x0128U, 0x0000000000000000UL},
57 {0x0130U, 0x0000000000000000UL},
58 {0x0138U, 0x001004020000FFFFUL},
59 {0x0140U, 0x001004020000FFFFUL},
60 {0x0148U, 0x001004020000FFFFUL},
61 {0x0150U, 0x001008050000FFFFUL},
62 {0x0158U, 0x001008050000FFFFUL},
63 {0x0160U, 0x001008050000FFFFUL},
64 {0x0168U, 0x001008050000FFFFUL},
65 {0x0170U, 0x001008050000FFFFUL},
66 {0x0178U, 0x001004030000FFFFUL},
67 {0x0180U, 0x001004030000FFFFUL},
68 {0x0188U, 0x001004030000FFFFUL},
69 {0x0190U, 0x001014140000FFFFUL},
70 {0x0198U, 0x001014140000FFFFUL},
71 {0x01A0U, 0x001008060000FFFFUL},
72 {0x01A8U, 0x001008060000FFFFUL},
73 {0x01B0U, 0x001008060000FFFFUL},
74 {0x01B8U, 0x0000000000000000UL},
75 {0x01C0U, 0x0000000000000000UL},
76 {0x01C8U, 0x0000000000000000UL},
77 {0x01D0U, 0x0000000000000000UL},
78 {0x01D8U, 0x0000000000000000UL},
79 {0x01E0U, 0x0000000000000000UL},
80 {0x01E8U, 0x0000000000000000UL},
81 {0x01F0U, 0x0000000000000000UL},
82 {0x01F8U, 0x0000000000000000UL},
83 {0x0200U, 0x0000000000000000UL},
84 {0x0208U, 0x0000000000000000UL},
85 {0x0210U, 0x0000000000000000UL},
86 {0x0218U, 0x0000000000000000UL},
87 {0x0220U, 0x0000000000000000UL},
88 {0x0228U, 0x0000000000000000UL},
89 {0x0230U, 0x0000000000000000UL},
90 {0x0238U, 0x0000000000000000UL},
91 {0x0240U, 0x0000000000000000UL},
92 {0x0248U, 0x0000000000000000UL},
93 {0x0250U, 0x0000000000000000UL},
94 {0x0258U, 0x0000000000000000UL},
95 {0x0260U, 0x0000000000000000UL},
96 {0x0268U, 0x0000000000000000UL},
97 {0x0270U, 0x0000000000000000UL},
98 {0x0278U, 0x0000000000000000UL},
99 {0x0280U, 0x0000000000000000UL},
100 {0x0288U, 0x0000000000000000UL},
101 {0x0290U, 0x0000000000000000UL},
102 {0x0298U, 0x0000000000000000UL},
103 {0x02A0U, 0x0000000000000000UL},
104 {0x02A8U, 0x0000000000000000UL},
105 {0x02B0U, 0x0000000000000000UL},
106 {0x02B8U, 0x0000000000000000UL},
107 {0x02C0U, 0x0000000000000000UL},
108 {0x02C8U, 0x0000000000000000UL},
109 {0x02D0U, 0x0000000000000000UL},
110 {0x02D8U, 0x0000000000000000UL},
111 {0x02E0U, 0x0000000000000000UL},
112 {0x02E8U, 0x0000000000000000UL},
113 {0x02F0U, 0x0000000000000000UL},
114 {0x02F8U, 0x0000000000000000UL},
115 {0x0300U, 0x0000000000000000UL},
116 {0x0308U, 0x0000000000000000UL},
117 {0x0310U, 0x0000000000000000UL},
118 {0x0318U, 0x0000000000000000UL},
119 {0x0320U, 0x0000000000000000UL},
120 {0x0328U, 0x0000000000000000UL},
121 {0x0330U, 0x0000000000000000UL},
122 {0x0338U, 0x0000000000000000UL},
123};
124
125static const mstat_slot_t mstat_be[] = {
126 {0x0000U, 0x001000100C8FFC01UL},
127 {0x0008U, 0x001000100C8FFC01UL},
128 {0x0010U, 0x001000100C8FFC01UL},
129 {0x0018U, 0x001000100C8FFC01UL},
130 {0x0020U, 0x001000100C8FFC01UL},
131 {0x0028U, 0x001000100C8FFC01UL},
132 {0x0030U, 0x001000100C8FFC01UL},
133 {0x0038U, 0x001000100C8FFC01UL},
134 {0x0040U, 0x0000000000000000UL},
135 {0x0048U, 0x0000000000000000UL},
136 {0x0050U, 0x001000100C8FFC01UL},
137 {0x0058U, 0x0000000000000000UL},
138 {0x0060U, 0x0000000000000000UL},
139 {0x0068U, 0x001000100C8FFC01UL},
140 {0x0070U, 0x001000100C8FFC01UL},
141 {0x0078U, 0x001000100C8FFC01UL},
142 {0x0080U, 0x001000100C8FFC01UL},
143 {0x0088U, 0x0000000000000000UL},
144 {0x0090U, 0x0000000000000000UL},
145 {0x0098U, 0x0000000000000000UL},
146 {0x00A0U, 0x001000100C8FFC01UL},
147 {0x00A8U, 0x001000100C8FFC01UL},
148 {0x00B0U, 0x001000100C8FFC01UL},
149 {0x00B8U, 0x001000100C8FFC01UL},
150 {0x00C0U, 0x001000100C8FFC01UL},
151 {0x00C8U, 0x001000100C8FFC01UL},
152 {0x00D0U, 0x001000100C8FFC01UL},
153 {0x00D8U, 0x002000200C8FFC01UL},
154 {0x00E0U, 0x002000200C8FFC01UL},
155 {0x00E8U, 0x001000100C8FFC01UL},
156 {0x00F0U, 0x001000100C8FFC01UL},
157 {0x00F8U, 0x001000100C8FFC01UL},
158 {0x0100U, 0x0000000000000000UL},
159 {0x0108U, 0x002000200C8FFC01UL},
160 {0x0110U, 0x001000100C8FFC01UL},
161 {0x0118U, 0x001000100C8FFC01UL},
162 {0x0120U, 0x0000000000000000UL},
163 {0x0128U, 0x002000200C8FFC01UL},
164 {0x0130U, 0x001000100C8FFC01UL},
165 {0x0138U, 0x0000000000000000UL},
166 {0x0140U, 0x0000000000000000UL},
167 {0x0148U, 0x0000000000000000UL},
168 {0x0150U, 0x0000000000000000UL},
169 {0x0158U, 0x0000000000000000UL},
170 {0x0160U, 0x0000000000000000UL},
171 {0x0168U, 0x0000000000000000UL},
172 {0x0170U, 0x0000000000000000UL},
173 {0x0178U, 0x0000000000000000UL},
174 {0x0180U, 0x0000000000000000UL},
175 {0x0188U, 0x0000000000000000UL},
176 {0x0190U, 0x0000000000000000UL},
177 {0x0198U, 0x0000000000000000UL},
178 {0x01A0U, 0x0000000000000000UL},
179 {0x01A8U, 0x0000000000000000UL},
180 {0x01B0U, 0x0000000000000000UL},
181 {0x01B8U, 0x001000100C8FFC01UL},
182 {0x01C0U, 0x001000200C8FFC01UL},
183 {0x01C8U, 0x001000200C8FFC01UL},
184 {0x01D0U, 0x001000200C8FFC01UL},
185 {0x01D8U, 0x001000200C8FFC01UL},
186 {0x01E0U, 0x001000100C8FFC01UL},
187 {0x01E8U, 0x001000100C8FFC01UL},
188 {0x01F0U, 0x001000100C8FFC01UL},
189 {0x01F8U, 0x001000100C8FFC01UL},
190 {0x0200U, 0x001000100C8FFC01UL},
191 {0x0208U, 0x001000100C8FFC01UL},
192 {0x0210U, 0x001000100C8FFC01UL},
193 {0x0218U, 0x001000100C8FFC01UL},
194 {0x0220U, 0x001000100C8FFC01UL},
195 {0x0228U, 0x001000100C8FFC01UL},
196 {0x0230U, 0x001000100C8FFC01UL},
197 {0x0238U, 0x001000100C8FFC01UL},
198 {0x0240U, 0x001000100C8FFC01UL},
199 {0x0248U, 0x001000100C8FFC01UL},
200 {0x0250U, 0x001000100C8FFC01UL},
201 {0x0258U, 0x001000100C8FFC01UL},
202 {0x0260U, 0x001000100C8FFC01UL},
203 {0x0268U, 0x001000100C8FFC01UL},
204 {0x0270U, 0x001000100C8FFC01UL},
205 {0x0278U, 0x001000100C8FFC01UL},
206 {0x0280U, 0x001000100C8FFC01UL},
207 {0x0288U, 0x001000100C8FFC01UL},
208 {0x0290U, 0x001000100C8FFC01UL},
209 {0x0298U, 0x001000100C8FFC01UL},
210 {0x02A0U, 0x001000100C8FFC01UL},
211 {0x02A8U, 0x001000100C8FFC01UL},
212 {0x02B0U, 0x001000100C8FFC01UL},
213 {0x02B8U, 0x001000100C8FFC01UL},
214 {0x02C0U, 0x001000100C8FFC01UL},
215 {0x02C8U, 0x001000100C8FFC01UL},
216 {0x02D0U, 0x001000100C8FFC01UL},
217 {0x02D8U, 0x001000100C8FFC01UL},
218 {0x02E0U, 0x001000100C8FFC01UL},
219 {0x02E8U, 0x001000100C8FFC01UL},
220 {0x02F0U, 0x001000200C8FFC01UL},
221 {0x02F8U, 0x001000300C8FFC01UL},
222 {0x0300U, 0x0000000000000000UL},
223 {0x0308U, 0x001000200C8FFC01UL},
224 {0x0310U, 0x001000300C8FFC01UL},
225 {0x0318U, 0x0000000000000000UL},
226 {0x0320U, 0x001000200C8FFC01UL},
227 {0x0328U, 0x001000300C8FFC01UL},
228 {0x0330U, 0x001000200C8FFC01UL},
229 {0x0338U, 0x001000300C8FFC01UL},
230};
231#endif
232
233void qos_init_h3_v10(void)
234{
235 /* DRAM Split Address mapping */
236#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH) || \
237 (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
238 NOTICE("BL2: DRAM Split is 4ch\n");
239 io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT
240 | ADSPLCR0_SPLITSEL(0xFFU)
241 | ADSPLCR0_AREA(0x1BU)
242 | ADSPLCR0_SWP);
243 io_write_32(AXI_ADSPLCR1, 0x00000000U);
244 io_write_32(AXI_ADSPLCR2, 0xA8A90000U);
245 io_write_32(AXI_ADSPLCR3, 0x00000000U);
246#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH
247 NOTICE("BL2: DRAM Split is 2ch\n");
248 io_write_32(AXI_ADSPLCR0, 0x00000000U);
249 io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
250 | ADSPLCR0_SPLITSEL(0xFFU)
251 | ADSPLCR0_AREA(0x1BU)
252 | ADSPLCR0_SWP);
253 io_write_32(AXI_ADSPLCR2, 0x00000000U);
254 io_write_32(AXI_ADSPLCR3, 0x00000000U);
255#else
256 NOTICE("BL2: DRAM Split is OFF\n");
257#endif
258
259#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
260#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
261 NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
262#endif
263
264 /* AR Cache setting */
265 io_write_32(0xE67D1000U, 0x00000100U);
266 io_write_32(0xE67D1008U, 0x00000100U);
267
268 /* Resource Alloc setting */
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]269 io_write_32(QOSCTRL_RAS, 0x00000040U);
270 io_write_32(QOSCTRL_FIXTH, 0x000F0005U);
271 io_write_32(QOSCTRL_REGGD, 0x00000004U);
272 io_write_64(QOSCTRL_DANN, 0x0202000004040404UL);
273 io_write_32(QOSCTRL_DANT, 0x003C1110U);
274 io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
275 io_write_64(QOSCTRL_EMS, 0x0000000000000000UL);
276 io_write_32(QOSCTRL_INSFC, 0xC7840001U);
277 io_write_32(QOSCTRL_BERR, 0x00000000U);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]278
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]279 /* QOSBW setting */
280 io_write_32(QOSCTRL_SL_INIT,
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]281 SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK);
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]282 io_write_32(QOSCTRL_REF_ARS, 0x00330000U);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]283
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]284 /* QOSBW SRAM setting */
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]285 for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]286 io_write_64(QOSBW_FIX_QOS_BANK0 + mstat_fix[i].addr,
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]287 mstat_fix[i].value);
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]288 io_write_64(QOSBW_FIX_QOS_BANK1 + mstat_fix[i].addr,
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]289 mstat_fix[i].value);
290 }
291 for (uint32_t i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]292 io_write_64(QOSBW_BE_QOS_BANK0 + mstat_be[i].addr,
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]293 mstat_be[i].value);
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]294 io_write_64(QOSBW_BE_QOS_BANK1 + mstat_be[i].addr,
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]295 mstat_be[i].value);
296 }
297
298 /* 3DG bus Leaf setting */
299 io_write_32(0xFD820808U, 0x00001234U);
300 io_write_32(0xFD820800U, 0x0000003FU);
301 io_write_32(0xFD821800U, 0x0000003FU);
302 io_write_32(0xFD822800U, 0x0000003FU);
303 io_write_32(0xFD823800U, 0x0000003FU);
304 io_write_32(0xFD824800U, 0x0000003FU);
305 io_write_32(0xFD825800U, 0x0000003FU);
306 io_write_32(0xFD826800U, 0x0000003FU);
307 io_write_32(0xFD827800U, 0x0000003FU);
308
309 /* Resource Alloc start */
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]310 io_write_32(QOSCTRL_RAEN, 0x00000001U);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]311
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]312 /* QOSBW start */
313 io_write_32(QOSCTRL_STATQC, 0x00000001U);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]314#else
315 NOTICE("BL2: QoS is None\n");
316
317 /* Resource Alloc setting */
Marek Vasutb0eb9882019-06-14 01:22:38 +0200[diff] [blame^]318 io_write_32(QOSCTRL_EC, 0x00080001U); /* need for H3 v1.* */
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]319#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
320}