Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 1 | /* |
Yann Gautier | 682a064 | 2024-01-10 16:28:20 +0100 | [diff] [blame] | 2 | * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <asm_macros.S> |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 8 | #include <drivers/st/stm32_gpio.h> |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 12 | #define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1) |
| 13 | |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 14 | .globl platform_mem_init |
| 15 | .globl plat_secondary_cold_boot_setup |
| 16 | .globl plat_is_my_cpu_primary |
Yann Gautier | 26a2c0a | 2023-09-22 13:58:11 +0200 | [diff] [blame^] | 17 | .globl plat_my_core_pos |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 18 | .globl plat_crash_console_init |
| 19 | .globl plat_crash_console_flush |
| 20 | .globl plat_crash_console_putc |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 21 | .globl plat_report_exception |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 22 | |
| 23 | func platform_mem_init |
| 24 | /* Nothing to do, don't need to init SYSRAM */ |
| 25 | ret |
| 26 | endfunc platform_mem_init |
| 27 | |
| 28 | /* --------------------------------------------- |
| 29 | * void plat_secondary_cold_boot_setup (void); |
| 30 | * |
| 31 | * Set secondary core in WFI waiting for core reset. |
| 32 | * --------------------------------------------- |
| 33 | */ |
| 34 | func plat_secondary_cold_boot_setup |
| 35 | dsb sy |
| 36 | wfi |
| 37 | /* This shouldn't be reached */ |
| 38 | b . |
| 39 | endfunc plat_secondary_cold_boot_setup |
| 40 | |
| 41 | /* ---------------------------------------------- |
| 42 | * unsigned int plat_is_my_cpu_primary(void); |
| 43 | * This function checks if this is the primary CPU |
| 44 | * ---------------------------------------------- |
| 45 | */ |
| 46 | func plat_is_my_cpu_primary |
| 47 | mrs x0, mpidr_el1 |
| 48 | and x0, x0, #(MPIDR_CPU_MASK) |
| 49 | cmp x0, #STM32MP_PRIMARY_CPU |
| 50 | cset x0, eq |
| 51 | ret |
| 52 | endfunc plat_is_my_cpu_primary |
| 53 | |
Yann Gautier | 26a2c0a | 2023-09-22 13:58:11 +0200 | [diff] [blame^] | 54 | /* ----------------------------------------------------------- |
| 55 | * unsigned int plat_stm32mp_get_core_pos(u_register_t mpidr) |
| 56 | * Helper function to calculate the core position. |
| 57 | * With this function: CorePos = (ClusterId * 4) + |
| 58 | * CoreId |
| 59 | * ----------------------------------------------------------- |
| 60 | */ |
| 61 | func plat_stm32mp_get_core_pos |
| 62 | and x1, x0, #MPIDR_CPU_MASK |
| 63 | and x0, x0, #MPIDR_CLUSTER_MASK |
| 64 | add x0, x1, x0, LSR #6 |
| 65 | ret |
| 66 | endfunc plat_stm32mp_get_core_pos |
| 67 | |
| 68 | /* ----------------------------------------------------- |
| 69 | * unsigned int plat_my_core_pos(void) |
| 70 | * This function uses the plat_stm32mp_get_core_pos() |
| 71 | * definition to get the index of the calling CPU. |
| 72 | * ----------------------------------------------------- |
| 73 | */ |
| 74 | func plat_my_core_pos |
| 75 | mrs x0, mpidr_el1 |
| 76 | b plat_stm32mp_get_core_pos |
| 77 | endfunc plat_my_core_pos |
| 78 | |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 79 | /* --------------------------------------------- |
| 80 | * int plat_crash_console_init(void) |
| 81 | * |
| 82 | * Initialize the crash console without a C Runtime stack. |
| 83 | * --------------------------------------------- |
| 84 | */ |
| 85 | func plat_crash_console_init |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 86 | /* Reset UART peripheral */ |
| 87 | mov_imm x1, (RCC_BASE + DEBUG_UART_RST_REG) |
| 88 | ldr x2, =DEBUG_UART_RST_BIT |
| 89 | ldr x0, [x1] |
| 90 | orr x0, x0, x2 |
| 91 | str x0, [x1] |
| 92 | 1: |
| 93 | ldr x0, [x1] |
Yann Gautier | 682a064 | 2024-01-10 16:28:20 +0100 | [diff] [blame] | 94 | tst x0, #DEBUG_UART_RST_BIT |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 95 | beq 1b |
Yann Gautier | 682a064 | 2024-01-10 16:28:20 +0100 | [diff] [blame] | 96 | bic x0, x0, #DEBUG_UART_RST_BIT |
| 97 | str x0, [x1] |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 98 | 2: |
| 99 | ldr x0, [x1] |
Yann Gautier | 682a064 | 2024-01-10 16:28:20 +0100 | [diff] [blame] | 100 | tst x0, #DEBUG_UART_RST_BIT |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 101 | bne 2b |
| 102 | /* Enable GPIOs for UART TX */ |
| 103 | mov_imm x1, (RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG) |
| 104 | ldr w2, [x1] |
| 105 | /* Configure GPIO */ |
| 106 | orr w2, w2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN |
| 107 | str w2, [x1] |
| 108 | mov_imm x1, DEBUG_UART_TX_GPIO_BANK_ADDRESS |
| 109 | /* Set GPIO mode alternate */ |
| 110 | ldr w2, [x1, #GPIO_MODE_OFFSET] |
| 111 | bic w2, w2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT) |
| 112 | orr w2, w2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT) |
| 113 | str w2, [x1, #GPIO_MODE_OFFSET] |
| 114 | /* Set GPIO speed low */ |
| 115 | ldr w2, [x1, #GPIO_SPEED_OFFSET] |
| 116 | bic w2, w2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT) |
| 117 | str w2, [x1, #GPIO_SPEED_OFFSET] |
| 118 | /* Set no-pull */ |
| 119 | ldr w2, [x1, #GPIO_PUPD_OFFSET] |
| 120 | bic w2, w2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT) |
| 121 | str w2, [x1, #GPIO_PUPD_OFFSET] |
| 122 | /* Set alternate */ |
| 123 | #if DEBUG_UART_TX_GPIO_PORT >= GPIO_ALT_LOWER_LIMIT |
| 124 | ldr w2, [x1, #GPIO_AFRH_OFFSET] |
| 125 | bic w2, w2, #(GPIO_ALTERNATE_MASK << \ |
| 126 | ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) |
| 127 | orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << \ |
| 128 | ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) |
| 129 | str w2, [x1, #GPIO_AFRH_OFFSET] |
| 130 | #else |
| 131 | ldr w2, [x1, #GPIO_AFRL_OFFSET] |
| 132 | bic w2, w2, #(GPIO_ALTERNATE_MASK << (DEBUG_UART_TX_GPIO_PORT << 2)) |
| 133 | orr w2, w2, #(DEBUG_UART_TX_GPIO_ALTERNATE << (DEBUG_UART_TX_GPIO_PORT << 2)) |
| 134 | str w2, [x1, #GPIO_AFRL_OFFSET] |
| 135 | #endif |
| 136 | /* Clear UART clock flexgen divisors, keep enable bit */ |
| 137 | mov_imm x1, (RCC_BASE + DEBUG_UART_PREDIV_CFGR) |
| 138 | mov x2, #0 |
| 139 | str w2, [x1] |
| 140 | mov_imm x1, (RCC_BASE + DEBUG_UART_FINDIV_CFGR) |
| 141 | mov x2, #0x40 |
| 142 | str w2, [x1] |
| 143 | /* Enable UART clock, with its source */ |
| 144 | mov_imm x1, (RCC_BASE + DEBUG_UART_TX_CLKSRC_REG) |
| 145 | mov_imm w2, (DEBUG_UART_TX_CLKSRC | RCC_XBARxCFGR_XBARxEN) |
| 146 | str w2, [x1] |
| 147 | mov_imm x1, (RCC_BASE + DEBUG_UART_TX_EN_REG) |
| 148 | ldr w2, [x1] |
| 149 | orr w2, w2, #DEBUG_UART_TX_EN |
| 150 | str w2, [x1] |
| 151 | |
| 152 | mov_imm x0, STM32MP_DEBUG_USART_BASE |
| 153 | mov_imm x1, STM32MP_DEBUG_USART_CLK_FRQ |
| 154 | mov_imm x2, STM32MP_UART_BAUDRATE |
| 155 | b console_stm32_core_init |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 156 | endfunc plat_crash_console_init |
| 157 | |
| 158 | func plat_crash_console_flush |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 159 | mov_imm x0, STM32MP_DEBUG_USART_BASE |
| 160 | b console_stm32_core_flush |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 161 | endfunc plat_crash_console_flush |
| 162 | |
| 163 | func plat_crash_console_putc |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 164 | mov_imm x1, STM32MP_DEBUG_USART_BASE |
| 165 | cmp x0, #'\n' |
| 166 | b.ne 1f |
| 167 | mov x15, x30 |
| 168 | mov x0, #'\r' |
| 169 | bl console_stm32_core_putc |
| 170 | mov x30, x15 |
| 171 | mov x0, #'\n' |
| 172 | 1: |
| 173 | b console_stm32_core_putc |
Yann Gautier | a3f4638 | 2023-06-14 10:40:59 +0200 | [diff] [blame] | 174 | endfunc plat_crash_console_putc |
| 175 | |
Yann Gautier | eb91af5 | 2023-06-14 18:05:47 +0200 | [diff] [blame] | 176 | #ifdef IMAGE_BL2 |
| 177 | /* --------------------------------------------- |
| 178 | * void plat_report_exception(unsigned int type) |
| 179 | * Function to report an unhandled exception |
| 180 | * with platform-specific means. |
| 181 | * --------------------------------------------- |
| 182 | */ |
| 183 | func plat_report_exception |
| 184 | mov x8, x30 |
| 185 | |
| 186 | adr x4, plat_err_str |
| 187 | bl asm_print_str |
| 188 | |
| 189 | adr x4, esr_el3_str |
| 190 | bl asm_print_str |
| 191 | |
| 192 | mrs x4, esr_el3 |
| 193 | bl asm_print_hex |
| 194 | |
| 195 | adr x4, elr_el3_str |
| 196 | bl asm_print_str |
| 197 | |
| 198 | mrs x4, elr_el3 |
| 199 | bl asm_print_hex |
| 200 | |
| 201 | adr x4, far_el3_str |
| 202 | bl asm_print_str |
| 203 | |
| 204 | mrs x4, far_el3 |
| 205 | bl asm_print_hex |
| 206 | |
| 207 | mov x30, x8 |
| 208 | ret |
| 209 | endfunc plat_report_exception |
| 210 | |
| 211 | .section .rodata.rev_err_str, "aS" |
| 212 | plat_err_str: |
| 213 | .asciz "\nPlatform exception reporting:" |
| 214 | esr_el3_str: |
| 215 | .asciz "\nESR_EL3: " |
| 216 | elr_el3_str: |
| 217 | .asciz "\nELR_EL3: " |
| 218 | far_el3_str: |
| 219 | .asciz "\nFAR_EL3: " |
| 220 | #endif /* IMAGE_BL2 */ |