Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. |
| 4 | * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. |
| 5 | * |
| 6 | * SPDX-License-Identifier: BSD-3-Clause |
| 7 | */ |
| 8 | |
| 9 | #ifndef VERSAL_NET_DEF_H |
| 10 | #define VERSAL_NET_DEF_H |
| 11 | |
| 12 | #include <plat/arm/common/smccc_def.h> |
| 13 | #include <plat/common/common_def.h> |
| 14 | |
Jay Buddhabhatti | c6daff0 | 2022-09-05 02:56:32 -0700 | [diff] [blame] | 15 | #define MAX_INTR_EL3 2 |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 16 | /* This part is taken from U-Boot project under GPL that's why dual license above */ |
| 17 | #define __bf_shf(x) (__builtin_ffsll(x) - 1U) |
| 18 | #define FIELD_GET(_mask, _reg) \ |
| 19 | ({ \ |
| 20 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ |
| 21 | }) |
| 22 | |
| 23 | /* List all consoles */ |
| 24 | #define VERSAL_NET_CONSOLE_ID_pl011 U(1) |
| 25 | #define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) |
| 26 | #define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) |
| 27 | |
| 28 | #define VERSAL_NET_CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) |
| 29 | |
| 30 | /* List all platforms */ |
| 31 | #define VERSAL_NET_SILICON U(0) |
| 32 | #define VERSAL_NET_SPP U(1) |
| 33 | #define VERSAL_NET_EMU U(2) |
| 34 | #define VERSAL_NET_QEMU U(3) |
Sai Pavan Boddu | 7524b22 | 2022-09-08 16:09:04 +0530 | [diff] [blame] | 35 | #define VERSAL_NET_QEMU_COSIM U(7) |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 36 | |
| 37 | /* For platform detection */ |
| 38 | #define PMC_TAP U(0xF11A0000) |
| 39 | #define PMC_TAP_VERSION (PMC_TAP + 0x4U) |
| 40 | # define PLATFORM_MASK GENMASK(27U, 24U) |
| 41 | # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) |
| 42 | |
| 43 | /* Global timer reset */ |
| 44 | #define PSX_CRF U(0xEC200000) |
Michal Simek | dc708ac | 2022-09-19 13:52:54 +0200 | [diff] [blame] | 45 | #define ACPU0_CLK_CTRL U(0x10C) |
| 46 | #define ACPU_CLK_CTRL_CLKACT BIT(25) |
| 47 | |
| 48 | #define RST_APU0_OFFSET U(0x300) |
| 49 | #define RST_APU_COLD_RESET BIT(0) |
| 50 | #define RST_APU_WARN_RESET BIT(4) |
| 51 | #define RST_APU_CLUSTER_COLD_RESET BIT(8) |
| 52 | #define RST_APU_CLUSTER_WARM_RESET BIT(9) |
| 53 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 54 | #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) |
| 55 | |
Michal Simek | dc708ac | 2022-09-19 13:52:54 +0200 | [diff] [blame] | 56 | #define APU_PCLI U(0xECB10000) |
| 57 | #define APU_PCLI_CPU_STEP U(0x30) |
| 58 | #define APU_PCLI_CLUSTER_CPU_STEP (4U * APU_PCLI_CPU_STEP) |
| 59 | #define APU_PCLI_CLUSTER_OFFSET U(0x8000) |
| 60 | #define APU_PCLI_CLUSTER_STEP U(0x1000) |
| 61 | #define PCLI_PREQ_OFFSET U(0x4) |
| 62 | #define PREQ_CHANGE_REQUEST BIT(0) |
| 63 | #define PCLI_PSTATE_OFFSET U(0x8) |
| 64 | #define PCLI_PSTATE_VAL_SET U(0x48) |
| 65 | #define PCLI_PSTATE_VAL_CLEAR U(0x38) |
| 66 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 67 | /* Firmware Image Package */ |
| 68 | #define VERSAL_NET_PRIMARY_CPU U(0) |
| 69 | |
Jay Buddhabhatti | c6daff0 | 2022-09-05 02:56:32 -0700 | [diff] [blame] | 70 | #define CORE_0_IEN_POWER_OFFSET (0x00000018U) |
| 71 | #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ |
| 72 | (0x30 * cpu_id))) |
| 73 | #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) |
| 74 | #define CORE_0_IDS_POWER_OFFSET (0x0000001CU) |
| 75 | #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ |
| 76 | (0x30 * cpu_id))) |
| 77 | #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) |
| 78 | #define CORE_PWRDN_EN_BIT_MASK (0x1U) |
| 79 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 80 | /******************************************************************************* |
| 81 | * memory map related constants |
| 82 | ******************************************************************************/ |
| 83 | /* IPP 1.2/SPP 0.9 mapping */ |
| 84 | #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ |
| 85 | #define DEVICE0_SIZE U(0x08000000) |
| 86 | #define DEVICE1_BASE U(0xE2000000) /* gic */ |
| 87 | #define DEVICE1_SIZE U(0x00800000) |
| 88 | #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ |
| 89 | #define DEVICE2_SIZE U(0x01000000) |
| 90 | #define CRF_BASE U(0xFD1A0000) |
| 91 | #define CRF_SIZE U(0x00600000) |
Michal Simek | aa5443e | 2022-09-19 14:04:55 +0200 | [diff] [blame] | 92 | #define IPI_BASE U(0xEB300000) |
| 93 | #define IPI_SIZE U(0x00100000) |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 94 | |
| 95 | /* CRL */ |
| 96 | #define VERSAL_NET_CRL U(0xEB5E0000) |
| 97 | #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) |
| 98 | #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) |
| 99 | |
| 100 | #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) |
| 101 | |
| 102 | /* IOU SCNTRS */ |
| 103 | #define VERSAL_NET_IOU_SCNTRS U(0xEC920000) |
| 104 | #define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) |
| 105 | #define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) |
| 106 | |
| 107 | #define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1) |
| 108 | |
Michal Simek | dc708ac | 2022-09-19 13:52:54 +0200 | [diff] [blame] | 109 | #define APU_CLUSTER0 U(0xECC00000) |
| 110 | #define APU_RVBAR_L_0 U(0x40) |
| 111 | #define APU_RVBAR_H_0 U(0x44) |
| 112 | #define APU_CLUSTER_STEP U(0x100000) |
| 113 | |
| 114 | #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) |
| 115 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 116 | /******************************************************************************* |
| 117 | * IRQ constants |
| 118 | ******************************************************************************/ |
| 119 | #define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) |
| 120 | |
| 121 | /******************************************************************************* |
| 122 | * UART related constants |
| 123 | ******************************************************************************/ |
| 124 | #define VERSAL_NET_UART0_BASE U(0xF1920000) |
| 125 | #define VERSAL_NET_UART_BAUDRATE 115200 |
| 126 | |
| 127 | #define VERSAL_NET_UART_BASE VERSAL_NET_UART0_BASE |
| 128 | |
| 129 | #define PLAT_VERSAL_NET_CRASH_UART_BASE VERSAL_NET_UART_BASE |
| 130 | #define PLAT_VERSAL_NET_CRASH_UART_CLK_IN_HZ VERSAL_NET_UART_CLOCK |
| 131 | #define VERSAL_NET_CONSOLE_BAUDRATE VERSAL_NET_UART_BAUDRATE |
| 132 | |
Jay Buddhabhatti | c6daff0 | 2022-09-05 02:56:32 -0700 | [diff] [blame] | 133 | /******************************************************************************* |
| 134 | * IPI registers and bitfields |
| 135 | ******************************************************************************/ |
| 136 | #define IPI0_REG_BASE (0xEB330000U) |
| 137 | #define IPI0_TRIG_BIT (1 << 2) |
| 138 | #define PMC_IPI_TRIG_BIT (1 << 1) |
| 139 | #define IPI1_REG_BASE (0xEB340000U) |
| 140 | #define IPI1_TRIG_BIT (1 << 3) |
| 141 | #define IPI2_REG_BASE (0xEB350000U) |
| 142 | #define IPI2_TRIG_BIT (1 << 4) |
| 143 | #define IPI3_REG_BASE (0xEB360000U) |
| 144 | #define IPI3_TRIG_BIT (1 << 5) |
| 145 | #define IPI4_REG_BASE (0xEB370000U) |
| 146 | #define IPI4_TRIG_BIT (1 << 6) |
| 147 | #define IPI5_REG_BASE (0xEB380000U) |
| 148 | #define IPI5_TRIG_BIT (1 << 7) |
| 149 | |
| 150 | /* Processor core device IDs */ |
| 151 | #define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) |
| 152 | #define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) |
| 153 | #define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) |
| 154 | #define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) |
| 155 | |
| 156 | #define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) |
| 157 | #define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) |
| 158 | #define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) |
| 159 | #define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) |
| 160 | |
| 161 | #define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) |
| 162 | #define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) |
| 163 | #define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) |
| 164 | #define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) |
| 165 | |
| 166 | #define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) |
| 167 | #define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) |
| 168 | #define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) |
| 169 | #define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) |
| 170 | |
Michal Simek | 9179436 | 2022-08-31 16:45:14 +0200 | [diff] [blame] | 171 | #endif /* VERSAL_NET_DEF_H */ |