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Soby Mathewec8ac1c2016-05-05 14:32:05 +01001/*
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00002 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathewec8ac1c2016-05-05 14:32:05 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewec8ac1c2016-05-05 14:32:05 +01005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <bl_common.h>
Dimitris Papastamos9fb79122017-06-07 12:22:01 +010011#include <console.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010012#include <context.h>
13#include <context_mgmt.h>
14#include <debug.h>
15#include <platform.h>
16#include <platform_def.h>
17#include <platform_sp_min.h>
18#include <psci.h>
19#include <runtime_svc.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000020#include <smccc_helpers.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010021#include <stddef.h>
22#include <stdint.h>
Roberto Vargas4d59eb42018-02-12 12:36:17 +000023#include <std_svc.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010024#include <stdint.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010025#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000026#include <utils.h>
Soby Mathewec8ac1c2016-05-05 14:32:05 +010027#include "sp_min_private.h"
28
29/* Pointers to per-core cpu contexts */
30static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT];
31
32/* SP_MIN only stores the non secure smc context */
33static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT];
34
35/******************************************************************************
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000036 * Define the smccc helper library API's
Soby Mathewec8ac1c2016-05-05 14:32:05 +010037 *****************************************************************************/
Etienne Carrierebfe12d32017-06-07 16:45:42 +020038void *smc_get_ctx(unsigned int security_state)
Soby Mathewec8ac1c2016-05-05 14:32:05 +010039{
40 assert(security_state == NON_SECURE);
41 return &sp_min_smc_context[plat_my_core_pos()];
42}
43
Etienne Carrierebfe12d32017-06-07 16:45:42 +020044void smc_set_next_ctx(unsigned int security_state)
Soby Mathewec8ac1c2016-05-05 14:32:05 +010045{
46 assert(security_state == NON_SECURE);
47 /* SP_MIN stores only non secure smc context. Nothing to do here */
48}
49
50void *smc_get_next_ctx(void)
51{
52 return &sp_min_smc_context[plat_my_core_pos()];
53}
54
55/*******************************************************************************
56 * This function returns a pointer to the most recent 'cpu_context' structure
57 * for the calling CPU that was set as the context for the specified security
58 * state. NULL is returned if no such structure has been specified.
59 ******************************************************************************/
60void *cm_get_context(uint32_t security_state)
61{
62 assert(security_state == NON_SECURE);
63 return sp_min_cpu_ctx_ptr[plat_my_core_pos()];
64}
65
66/*******************************************************************************
67 * This function sets the pointer to the current 'cpu_context' structure for the
68 * specified security state for the calling CPU
69 ******************************************************************************/
70void cm_set_context(void *context, uint32_t security_state)
71{
72 assert(security_state == NON_SECURE);
73 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context;
74}
75
76/*******************************************************************************
77 * This function returns a pointer to the most recent 'cpu_context' structure
78 * for the CPU identified by `cpu_idx` that was set as the context for the
79 * specified security state. NULL is returned if no such structure has been
80 * specified.
81 ******************************************************************************/
82void *cm_get_context_by_index(unsigned int cpu_idx,
83 unsigned int security_state)
84{
85 assert(security_state == NON_SECURE);
86 return sp_min_cpu_ctx_ptr[cpu_idx];
87}
88
89/*******************************************************************************
90 * This function sets the pointer to the current 'cpu_context' structure for the
91 * specified security state for the CPU identified by CPU index.
92 ******************************************************************************/
93void cm_set_context_by_index(unsigned int cpu_idx, void *context,
94 unsigned int security_state)
95{
96 assert(security_state == NON_SECURE);
97 sp_min_cpu_ctx_ptr[cpu_idx] = context;
98}
99
100static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx,
101 smc_ctx_t *next_smc_ctx)
102{
103 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
104 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
105 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
Soby Mathewf3e3a432017-03-30 14:42:54 +0100106 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100107}
108
109/*******************************************************************************
110 * This function invokes the PSCI library interface to initialize the
111 * non secure cpu context and copies the relevant cpu context register values
112 * to smc context. These registers will get programmed during `smc_exit`.
113 ******************************************************************************/
114static void sp_min_prepare_next_image_entry(void)
115{
116 entry_point_info_t *next_image_info;
Soby Mathewf3e3a432017-03-30 14:42:54 +0100117 cpu_context_t *ctx = cm_get_context(NON_SECURE);
118 u_register_t ns_sctlr;
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100119
120 /* Program system registers to proceed to non-secure */
121 next_image_info = sp_min_plat_get_bl33_ep_info();
122 assert(next_image_info);
123 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr));
124
125 INFO("SP_MIN: Preparing exit to normal world\n");
126
127 psci_prepare_next_non_secure_ctx(next_image_info);
128 smc_set_next_ctx(NON_SECURE);
129
130 /* Copy r0, lr and spsr from cpu context to SMC context */
131 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
132 smc_get_next_ctx());
Soby Mathewf3e3a432017-03-30 14:42:54 +0100133
134 /* Temporarily set the NS bit to access NS SCTLR */
135 write_scr(read_scr() | SCR_NS_BIT);
136 isb();
137 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
138 write_sctlr(ns_sctlr);
139 isb();
140
141 write_scr(read_scr() & ~SCR_NS_BIT);
142 isb();
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100143}
144
145/******************************************************************************
Soby Mathew8da89662016-09-19 17:21:15 +0100146 * Implement the ARM Standard Service function to get arguments for a
147 * particular service.
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100148 *****************************************************************************/
Soby Mathew8da89662016-09-19 17:21:15 +0100149uintptr_t get_arm_std_svc_args(unsigned int svc_mask)
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100150{
Soby Mathew89256b82016-09-13 14:19:08 +0100151 /* Setup the arguments for PSCI Library */
152 DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint);
153
Soby Mathew8da89662016-09-19 17:21:15 +0100154 /* PSCI is the only ARM Standard Service implemented */
155 assert(svc_mask == PSCI_FID_MASK);
156
157 return (uintptr_t)&psci_args;
158}
159
160/******************************************************************************
161 * The SP_MIN main function. Do the platform and PSCI Library setup. Also
162 * initialize the runtime service framework.
163 *****************************************************************************/
164void sp_min_main(void)
165{
Soby Mathew89256b82016-09-13 14:19:08 +0100166 NOTICE("SP_MIN: %s\n", version_string);
167 NOTICE("SP_MIN: %s\n", build_message);
168
169 /* Perform the SP_MIN platform setup */
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100170 sp_min_platform_setup();
171
Soby Mathew8da89662016-09-19 17:21:15 +0100172 /* Initialize the runtime services e.g. psci */
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100173 INFO("SP_MIN: Initializing runtime services\n");
174 runtime_svc_init();
175
176 /*
177 * We are ready to enter the next EL. Prepare entry into the image
178 * corresponding to the desired security state after the next ERET.
179 */
180 sp_min_prepare_next_image_entry();
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100181
182 /*
183 * Perform any platform specific runtime setup prior to cold boot exit
184 * from SP_MIN.
185 */
186 sp_min_plat_runtime_setup();
Dimitris Papastamos9fb79122017-06-07 12:22:01 +0100187
188 console_flush();
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100189}
190
191/******************************************************************************
192 * This function is invoked during warm boot. Invoke the PSCI library
193 * warm boot entry point which takes care of Architectural and platform setup/
194 * restore. Copy the relevant cpu_context register values to smc context which
195 * will get programmed during `smc_exit`.
196 *****************************************************************************/
197void sp_min_warm_boot(void)
198{
199 smc_ctx_t *next_smc_ctx;
David Cunadoa31bcde2017-09-04 16:41:37 +0100200 cpu_context_t *ctx = cm_get_context(NON_SECURE);
201 u_register_t ns_sctlr;
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100202
203 psci_warmboot_entrypoint();
204
205 smc_set_next_ctx(NON_SECURE);
206
207 next_smc_ctx = smc_get_next_ctx();
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000208 zeromem(next_smc_ctx, sizeof(smc_ctx_t));
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100209
210 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)),
211 next_smc_ctx);
David Cunadoa31bcde2017-09-04 16:41:37 +0100212
213 /* Temporarily set the NS bit to access NS SCTLR */
214 write_scr(read_scr() | SCR_NS_BIT);
215 isb();
216 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
217 write_sctlr(ns_sctlr);
218 isb();
219
220 write_scr(read_scr() & ~SCR_NS_BIT);
221 isb();
Soby Mathewec8ac1c2016-05-05 14:32:05 +0100222}
Etienne Carrieredc0fea72017-08-09 15:48:53 +0200223
224#if SP_MIN_WITH_SECURE_FIQ
225/******************************************************************************
226 * This function is invoked on secure interrupts. By construction of the
227 * SP_MIN, secure interrupts can only be handled when core executes in non
228 * secure state.
229 *****************************************************************************/
230void sp_min_fiq(void)
231{
232 uint32_t id;
233
234 id = plat_ic_acknowledge_interrupt();
235 sp_min_plat_fiq_handler(id);
236 plat_ic_end_of_interrupt(id);
237}
238#endif /* SP_MIN_WITH_SECURE_FIQ */