blob: a7f14a477418e8cdd98d355cd3555f588051b70b [file] [log] [blame]
Rajan Vaja5529a012018-01-17 02:39:23 -08001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * ZynqMP system level PM-API functions for pin control.
9 */
10
11#ifndef _PM_API_IOCTL_H_
12#define _PM_API_IOCTL_H_
13
14#include "pm_common.h"
15
16enum pm_ioctl_id {
17 IOCTL_GET_RPU_OPER_MODE,
18 IOCTL_SET_RPU_OPER_MODE,
19 IOCTL_RPU_BOOT_ADDR_CONFIG,
20 IOCTL_TCM_COMB_CONFIG,
Rajan Vajaaea41bb2018-01-17 02:39:24 -080021 IOCTL_SET_TAPDELAY_BYPASS,
22 IOCTL_SET_SGMII_MODE,
23 IOCTL_SD_DLL_RESET,
24 IOCTL_SET_SD_TAPDELAY,
Rajan Vaja5529a012018-01-17 02:39:23 -080025};
26
27enum rpu_oper_mode {
28 PM_RPU_MODE_LOCKSTEP,
29 PM_RPU_MODE_SPLIT,
30};
31
32enum rpu_boot_mem {
33 PM_RPU_BOOTMEM_LOVEC,
34 PM_RPU_BOOTMEM_HIVEC,
35};
36
37enum rpu_tcm_comb {
38 PM_RPU_TCM_SPLIT,
39 PM_RPU_TCM_COMB,
40};
41
Rajan Vajaaea41bb2018-01-17 02:39:24 -080042enum tap_delay_signal_type {
43 PM_TAPDELAY_NAND_DQS_IN,
44 PM_TAPDELAY_NAND_DQS_OUT,
45 PM_TAPDELAY_QSPI,
46 PM_TAPDELAY_MAX,
47};
48
49enum tap_delay_bypass_ctrl {
50 PM_TAPDELAY_BYPASS_DISABLE,
51 PM_TAPDELAY_BYPASS_ENABLE,
52};
53
54enum sgmii_mode {
55 PM_SGMII_DISABLE,
56 PM_SGMII_ENABLE,
57};
58
59enum tap_delay_type {
60 PM_TAPDELAY_INPUT,
61 PM_TAPDELAY_OUTPUT,
62};
63
64enum dll_reset_type {
65 PM_DLL_RESET_ASSERT,
66 PM_DLL_RESET_RELEASE,
67 PM_DLL_RESET_PULSE,
68};
69
Rajan Vaja5529a012018-01-17 02:39:23 -080070enum pm_ret_status pm_api_ioctl(enum pm_node_id nid,
71 unsigned int ioctl_id,
72 unsigned int arg1,
73 unsigned int arg2,
74 unsigned int *value);
75#endif /* _PM_API_IOCTL_H_ */