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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <platform.h>
33#include <assert.h>
34
35/*******************************************************************************
36 * Function that does the first bit of architectural setup that affects
37 * execution in the non-secure address space.
38 ******************************************************************************/
39void bl1_arch_setup(void)
40{
41 unsigned long tmp_reg = 0;
Achin Gupta4f6ad662013-10-25 09:08:21 +010042
43 /* Enable alignment checks and set the exception endianess to LE */
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000044 tmp_reg = read_sctlr_el3();
Achin Gupta4f6ad662013-10-25 09:08:21 +010045 tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
46 tmp_reg &= ~SCTLR_EE_BIT;
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000047 write_sctlr_el3(tmp_reg);
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
49 /*
Sandrine Bailleux37382742013-11-18 17:26:59 +000050 * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
51 * external abort and SError interrupts to EL3
Achin Gupta4f6ad662013-10-25 09:08:21 +010052 */
Sandrine Bailleux37382742013-11-18 17:26:59 +000053 tmp_reg = SCR_RES1_BITS | SCR_RW_BIT | SCR_HCE_BIT | SCR_EA_BIT |
54 SCR_FIQ_BIT;
Achin Gupta4f6ad662013-10-25 09:08:21 +010055 write_scr(tmp_reg);
56
Sandrine Bailleux37382742013-11-18 17:26:59 +000057 /*
58 * Enable SError and Debug exceptions
59 */
60 enable_serror();
61 enable_debug_exceptions();
Achin Gupta4f6ad662013-10-25 09:08:21 +010062}
63
64/*******************************************************************************
65 * Set the Secure EL1 required architectural state
66 ******************************************************************************/
67void bl1_arch_next_el_setup(void) {
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000068 unsigned long next_sctlr;
Achin Gupta4f6ad662013-10-25 09:08:21 +010069
70 /* Use the same endianness than the current BL */
Vikram Kanigiri78a6e0c2014-03-11 17:41:00 +000071 next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +010072
73 /* Set SCTLR Secure EL1 */
74 next_sctlr |= SCTLR_EL1_RES1;
75
76 write_sctlr_el1(next_sctlr);
77}