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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <platform.h>
32
33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
34OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
35
36MEMORY {
Achin Gupta4f6ad662013-10-25 09:08:21 +010037 RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
38}
39
40
41SECTIONS
42{
43 . = BL2_BASE;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000044 ASSERT(. == ALIGN(4096),
45 "BL2_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010046
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000047 ro . : {
48 __RO_START__ = .;
49 *bl2_entrypoint.o(.text)
50 *(.text)
51 *(.rodata*)
Achin Guptab739f222014-01-18 16:50:09 +000052 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000053 __RO_END_UNALIGNED__ = .;
54 /*
55 * Memory page(s) mapped to this section will be marked as
56 * read-only, executable. No RW data from the next section must
57 * creep in. Ensure the rest of the current memory page is unused.
58 */
59 . = NEXT(4096);
60 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010061 } >RAM
62
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000063 .data . : {
64 __DATA_START__ = .;
65 *(.data)
66 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010067 } >RAM
68
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000069 stacks (NOLOAD) : {
70 __STACKS_START__ = .;
71 *(tzfw_normal_stacks)
72 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010073 } >RAM
74
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000075 /*
76 * The .bss section gets initialised to 0 at runtime.
77 * Its base address must be 16-byte aligned.
78 */
79 .bss : ALIGN(16) {
80 __BSS_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010081 *(SORT_BY_ALIGNMENT(.bss))
82 *(COMMON)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000083 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010084 } >RAM
85
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000086 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +000087 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +000088 * Removing them from .bss avoids forcing 4K alignment on
89 * the .bss section and eliminates the unecessary zero init
90 */
91 xlat_table (NOLOAD) : {
92 *(xlat_table)
93 } >RAM
94
95 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000096 * The base address of the coherent memory section must be page-aligned (4K)
97 * to guarantee that the coherent data are stored on their own pages and
98 * are not mixed with normal data. This is required to set up the correct
99 * memory attributes for the coherent data page tables.
100 */
101 coherent_ram (NOLOAD) : ALIGN(4096) {
102 __COHERENT_RAM_START__ = .;
103 *(tzfw_coherent_mem)
104 __COHERENT_RAM_END_UNALIGNED__ = .;
105 /*
106 * Memory page(s) mapped to this section will be marked
107 * as device memory. No other unexpected data must creep in.
108 * Ensure the rest of the current memory page is unused.
109 */
110 . = NEXT(4096);
111 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100112 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000114 __BL2_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000116 __BSS_SIZE__ = SIZEOF(.bss);
117 __COHERENT_RAM_UNALIGNED_SIZE__ =
118 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119}