blob: 94a6bad4e5d26cb5c3674cc3acbe634c45f37fe8 [file] [log] [blame]
Valentine Barshakf2184142018-10-30 02:06:17 +03001/*
Marek Vasuta75f8262019-07-14 08:55:27 +02002 * Copyright (c) 2015-2019, Renesas Electronics Corporation
Valentine Barshakf2184142018-10-30 02:06:17 +03003 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
Marek Vasuta75f8262019-07-14 08:55:27 +02008#include <lib/utils_def.h>
Valentine Barshakf2184142018-10-30 02:06:17 +03009#include <stdint.h>
10#include "boot_init_dram.h"
11#include "boot_init_dram_regdef_v3m.h"
12
13static void WriteReg_32(uintptr_t a, uint32_t v)
14{
15 *(volatile uint32_t*)a = v;
16}
17
18static uint32_t ReadReg_32(uintptr_t a)
19{
20 uint32_t w = *(volatile uint32_t*)a;
21 return w;
22}
23
24static uint32_t init_ddr_v3m_1600(void)
25{
26 // last modified 2016.12.16
27
28 uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12;
29
30 WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234);
31 WriteReg_32(DBSC_V3M_DBKIND,0x00000007);
32#if RCAR_DRAM_DDR3L_MEMCONF == 0
33 WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle
34#else
35 WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK
36#endif
37 WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001);
38 WriteReg_32(DBSC_V3M_DBTR0,0x0000000B);
39 WriteReg_32(DBSC_V3M_DBTR1,0x00000008);
40 WriteReg_32(DBSC_V3M_DBTR3,0x0000000B);
41 WriteReg_32(DBSC_V3M_DBTR4,0x000B000B);
42 WriteReg_32(DBSC_V3M_DBTR5,0x00000027);
43 WriteReg_32(DBSC_V3M_DBTR6,0x0000001C);
44 WriteReg_32(DBSC_V3M_DBTR7,0x00060006);
45 WriteReg_32(DBSC_V3M_DBTR8,0x00000020);
46 WriteReg_32(DBSC_V3M_DBTR9,0x00000006);
47 WriteReg_32(DBSC_V3M_DBTR10,0x0000000C);
48 WriteReg_32(DBSC_V3M_DBTR11,0x0000000B);
49 WriteReg_32(DBSC_V3M_DBTR12,0x00120012);
50 WriteReg_32(DBSC_V3M_DBTR13,0x01180118);
51 WriteReg_32(DBSC_V3M_DBTR14,0x00140005);
52 WriteReg_32(DBSC_V3M_DBTR15,0x00050004);
53 WriteReg_32(DBSC_V3M_DBTR16,0x071D0305);
54 WriteReg_32(DBSC_V3M_DBTR17,0x040C0010);
55 WriteReg_32(DBSC_V3M_DBTR18,0x00000200);
56 WriteReg_32(DBSC_V3M_DBTR19,0x01000040);
57 WriteReg_32(DBSC_V3M_DBTR20,0x02000120);
58 WriteReg_32(DBSC_V3M_DBTR21,0x00040004);
59 WriteReg_32(DBSC_V3M_DBBL,0x00000000);
60 WriteReg_32(DBSC_V3M_DBODT0,0x00000001);
61 WriteReg_32(DBSC_V3M_DBADJ0,0x00000001);
62 WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010);
63 WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000);
64 WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f);
65 WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010);
66 WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001);
67 WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200);
68 WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040);
69 WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600);
70 WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480);
71 WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300);
72 WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180);
73 WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400);
74 WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300);
75 WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200);
76 WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100);
77 WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300);
78 WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240);
79 WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180);
80 WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0);
81 WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200);
82 WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180);
83 WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100);
84 WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080);
85 WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100);
86 WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0);
87 WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080);
88 WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040);
89 WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002);
90 WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04);
91 WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4);
92 WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003);
93 WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080);
94 WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010);
95
96 WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A);
97 WriteReg_32(DBSC_V3M_DBCMD,0x01000001);
98 WriteReg_32(DBSC_V3M_DBCMD,0x08000000);
99 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
100 WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000);
101 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200102 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300103
104 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008);
105 WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000);
106 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
107 WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904);
108 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091);
109 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
110 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095);
111 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B);
112 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099);
113 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D);
114 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
115 WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
116 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
117 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E);
118 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
119 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073);
120 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200121 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300122
123 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
124 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900);
125 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090);
126 WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900);
127 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200128 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300129
130 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
131 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700);
132 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
Marek Vasuta75f8262019-07-14 08:55:27 +0200133 while ( (BIT(30)& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300134
135 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004);
136 WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170);
137 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022);
138 WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B);
139 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023);
140 WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66);
141 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024);
142 WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400);
143 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025);
144 WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200);
145 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026);
146 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9);
147 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027);
148 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70);
149 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028);
150 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004);
151 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029);
152 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018);
153 WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
154 WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047);
155 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020);
156 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884);
157 WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A);
158 WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10);
159 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200160 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300161
162 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7);
163 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
164 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8);
165 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
166 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9);
167 WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
168 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7);
169 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
170 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8);
171 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
172 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9);
173 WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
174 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7);
175 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
176 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8);
177 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
178 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9);
179 WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
180 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107);
181 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
182 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108);
183 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D);
184 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109);
185 WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D);
186 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
187 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181);
188 WriteReg_32(DBSC_V3M_DBCMD,0x08000001);
189 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200190 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300191
192 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
193 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601);
194 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200195 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300196
197 for (uint32_t i = 0; i<4; i++)
198 {
199 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20);
200 RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8;
201 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20);
202 RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ;
203 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20);
204 RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ;
205 if ( RegVal_R6 > 0 )
206 {
207 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
208 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
209
210 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
211 WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2);
212 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
213 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
214 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
215 WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6);
216 } else {
217 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
218 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ;
219 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20);
220 WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7);
221
222 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
223 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ;
224 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20);
225 WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2);
226 }
227 }
228
229 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
230 WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0);
231 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
232 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
233 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
234 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
235 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
236 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
237 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
238 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
239 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
240 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801);
241 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200242 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300243
244 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005);
245 WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8);
246 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
247 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001);
248 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200249 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300250
251 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
252 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
253 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
254 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
255 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
256 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
257 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
258 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285);
259 WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C);
260 WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087);
261 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
262 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401);
263 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200264 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300265
266 for (uint32_t i = 0; i < 4; i++)
267 {
268 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20);
269 RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8;
270 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20);
271 RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF);
272
273 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20);
274 RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007);
275 RegVal_R12 = (RegVal_R5 >> 2);
276 if (RegVal_R6 - RegVal_R12 > 0)
277 {
278 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
279 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
280
281 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
282 WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2);
283 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
284 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
285
286 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
287 WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2);
288 }
289 else
290 {
291 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
292 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8);
293 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20);
294 WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2);
295 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
296 RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00);
297 WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20);
298 WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2);
299 }
300 }
301
302 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0);
303 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
304 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0);
305 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
306 WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0);
307 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
308 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100);
309 WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5);
310 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001);
311 WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001);
312 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006);
Marek Vasuta75f8262019-07-14 08:55:27 +0200313 while ( (BIT(0) & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300314
315 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003);
316 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700);
317 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007);
Marek Vasuta75f8262019-07-14 08:55:27 +0200318 while ( (BIT(30)& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 );
Valentine Barshakf2184142018-10-30 02:06:17 +0300319 WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021);
320 WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E);
321
322 WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000);
323 WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001);
324 WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E);
325 WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860);
326 WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);
327 WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001);
328 WriteReg_32(DBSC_V3M_DBRFEN,0x00000001);
329 WriteReg_32(DBSC_V3M_DBACEN,0x00000001);
330 WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000);
331 WriteReg_32(0xE67F0024, 0x00000001);
332 WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000);
333
334 return 1;
335}
336
337int32_t rcar_dram_init(void)
338{
339 return init_ddr_v3m_1600() ? INITDRAM_OK : INITDRAM_NG;
340}