| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <cpu_macros.S> |
| 10 | #include <neoverse_n2.h> |
| 11 | |
| 12 | /* Hardware handled coherency */ |
| 13 | #if HW_ASSISTED_COHERENCY == 0 |
| 14 | #error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 15 | #endif |
| 16 | |
| 17 | /* 64-bit only core */ |
| 18 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 19 | #error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 20 | #endif |
| 21 | |
| 22 | /* ------------------------------------------------- |
| 23 | * The CPU Ops reset function for Neoverse N2. |
| 24 | * ------------------------------------------------- |
| 25 | */ |
| 26 | func neoverse_n2_reset_func |
| 27 | /* Check if the PE implements SSBS */ |
| 28 | mrs x0, id_aa64pfr1_el1 |
| 29 | tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) |
| 30 | b.eq 1f |
| 31 | |
| 32 | /* Disable speculative loads */ |
| 33 | msr SSBS, xzr |
| 34 | 1: |
| 35 | /* Force all cacheable atomic instructions to be near */ |
| 36 | mrs x0, NEOVERSE_N2_CPUACTLR2_EL1 |
| 37 | orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 |
| 38 | msr NEOVERSE_N2_CPUACTLR2_EL1, x0 |
| 39 | |
| 40 | #if ENABLE_AMU |
| 41 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 42 | mrs x0, cptr_el3 |
| 43 | orr x0, x0, #TAM_BIT |
| 44 | msr cptr_el3, x0 |
| 45 | |
| 46 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
| 47 | mrs x0, cptr_el2 |
| 48 | orr x0, x0, #TAM_BIT |
| 49 | msr cptr_el2, x0 |
| 50 | |
| 51 | /* No need to enable the counters as this would be done at el3 exit */ |
| 52 | #endif |
| 53 | |
| 54 | #if NEOVERSE_Nx_EXTERNAL_LLC |
| 55 | /* Some systems may have External LLC, core needs to be made aware */ |
| 56 | mrs x0, NEOVERSE_N2_CPUECTLR_EL1 |
| 57 | orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT |
| 58 | msr NEOVERSE_N2_CPUECTLR_EL1, x0 |
| 59 | #endif |
| 60 | |
| 61 | isb |
| 62 | ret |
| 63 | endfunc neoverse_n2_reset_func |
| 64 | |
| 65 | func neoverse_n2_core_pwr_dwn |
| 66 | /* --------------------------------------------- |
| 67 | * Enable CPU power down bit in power control register |
| 68 | * No need to do cache maintenance here. |
| 69 | * --------------------------------------------- |
| 70 | */ |
| 71 | mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 |
| 72 | orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT |
| 73 | msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0 |
| 74 | isb |
| 75 | ret |
| 76 | endfunc neoverse_n2_core_pwr_dwn |
| 77 | |
| 78 | #if REPORT_ERRATA |
| 79 | /* |
| 80 | * Errata printing function for Neoverse N2 cores. Must follow AAPCS. |
| 81 | */ |
| 82 | func neoverse_n2_errata_report |
| 83 | /* No errata reported for Neoverse N2 cores */ |
| 84 | ret |
| 85 | endfunc neoverse_n2_errata_report |
| 86 | #endif |
| 87 | |
| 88 | /* --------------------------------------------- |
| 89 | * This function provides Neoverse N2 specific |
| 90 | * register information for crash reporting. |
| 91 | * It needs to return with x6 pointing to |
| 92 | * a list of register names in ASCII and |
| 93 | * x8 - x15 having values of registers to be |
| 94 | * reported. |
| 95 | * --------------------------------------------- |
| 96 | */ |
| 97 | .section .rodata.neoverse_n2_regs, "aS" |
| 98 | neoverse_n2_regs: /* The ASCII list of register names to be reported */ |
| 99 | .asciz "cpupwrctlr_el1", "" |
| 100 | |
| 101 | func neoverse_n2_cpu_reg_dump |
| 102 | adr x6, neoverse_n2_regs |
| 103 | mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1 |
| 104 | ret |
| 105 | endfunc neoverse_n2_cpu_reg_dump |
| 106 | |
| 107 | declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \ |
| 108 | neoverse_n2_reset_func, \ |
| 109 | neoverse_n2_core_pwr_dwn |