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Usama Arifbec5afd2020-04-17 16:13:39 +01001/*
Yann Gautier9b0ccd72024-10-04 18:49:35 +02002 * Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
Usama Arifbec5afd2020-04-17 16:13:39 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8
9#include <libfdt.h>
Usama Ariff1513622021-04-09 17:07:41 +010010#include <tc_plat.h>
Usama Arifbec5afd2020-04-17 16:13:39 +010011
Manish V Badarkheb241efb2023-10-18 14:11:45 +010012#include <arch_helpers.h>
Usama Arifbec5afd2020-04-17 16:13:39 +010013#include <common/bl_common.h>
14#include <common/debug.h>
15#include <drivers/arm/css/css_mhu_doorbell.h>
16#include <drivers/arm/css/scmi.h>
Madhukar Pappireddye108df22023-03-22 15:40:40 -050017#include <drivers/arm/sbsa.h>
Usama Arifa49bd492021-08-17 17:57:10 +010018#include <lib/fconf/fconf.h>
19#include <lib/fconf/fconf_dyn_cfg_getter.h>
Usama Arifbec5afd2020-04-17 16:13:39 +010020#include <plat/arm/common/plat_arm.h>
21#include <plat/common/platform.h>
22
Manish V Badarkheb20ca822023-12-06 09:16:08 +000023#ifdef PLATFORM_TEST_TFM_TESTSUITE
Manish V Badarkheb241efb2023-10-18 14:11:45 +010024#include <psa/crypto_platform.h>
25#include <psa/crypto_types.h>
26#include <psa/crypto_values.h>
Manish V Badarkheb20ca822023-12-06 09:16:08 +000027#endif /* PLATFORM_TEST_TFM_TESTSUITE */
Manish V Badarkhe2bdcb152024-12-15 18:26:15 +000028#include <psa/error.h>
Manish V Badarkheb241efb2023-10-18 14:11:45 +010029
Leo Yanb0bfa5b2024-05-21 16:33:01 +000030#include <plat/common/platform.h>
Yann Gautier9b0ccd72024-10-04 18:49:35 +020031#include <tc_rse_comms.h>
Leo Yanb0bfa5b2024-05-21 16:33:01 +000032
Manish V Badarkheb241efb2023-10-18 14:11:45 +010033#ifdef PLATFORM_TEST_TFM_TESTSUITE
34/*
35 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
36 * mbedTLS config option) so we need to provide an implementation of
37 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not
38 * actually use any of external RNG and this function is only needed during
39 * the execution of TF-M testsuite during exporting the public part of the
40 * delegated attestation key.
41 */
42psa_status_t mbedtls_psa_external_get_random(
43 mbedtls_psa_external_random_context_t *context,
44 uint8_t *output, size_t output_size,
45 size_t *output_length)
46{
47 for (size_t i = 0U; i < output_size; i++) {
48 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU);
49 }
50
51 *output_length = output_size;
52
53 return PSA_SUCCESS;
54}
55#endif /* PLATFORM_TEST_TFM_TESTSUITE */
56
Leo Yan8dd7d432024-05-22 15:41:37 +010057static scmi_channel_plat_info_t tc_scmi_plat_info = {
58 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
Leo Yan7d51bf82024-05-22 15:42:46 +010059 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0),
60 .db_preserve_mask = 0xfffffffe,
61 .db_modify_mask = 0x1,
62 .ring_doorbell = &mhu_ring_doorbell,
63};
Jagdish Gediya5ae7c382023-12-18 05:56:00 +000064
Boyan Karatotevb2953472024-11-06 14:55:35 +000065/* the bottom 3 AMU group 1 counters */
66#define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2))
67
68uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT] = {
69 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS,
70 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS,
71#if PLATFORM_CORE_COUNT == 14
72 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS,
73 MPMM_GEARS, MPMM_GEARS
74#endif
75};
76
Jagdish Gediya35173432024-06-19 08:57:47 +000077#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
Jagdish Gediya5ae7c382023-12-18 05:56:00 +000078static void enable_ns_mcn_pmu(void)
79{
80 /*
81 * Enable non-secure access to MCN PMU registers
82 */
83 for (int i = 0; i < MCN_INSTANCES; i++) {
Jagdish Gediya5e386592024-06-19 08:50:45 +000084 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) +
85 MCN_SCR_OFFSET;
Jagdish Gediya5ae7c382023-12-18 05:56:00 +000086 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT);
87 }
88}
Jagdish Gediya35173432024-06-19 08:57:47 +000089#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */
Jagdish Gediyaebaa6bf2024-01-11 10:49:46 +000090
Jagdish Gediya35173432024-06-19 08:57:47 +000091#if TARGET_PLATFORM == 3
Jagdish Gediyaebaa6bf2024-01-11 10:49:46 +000092static void set_mcn_slc_alloc_mode(void)
93{
94 /*
95 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to
96 * 0b01 (always alloc), configure both to 0b10 (use bus signal
97 * attribute from interface).
98 */
99 for (int i = 0; i < MCN_INSTANCES; i++) {
Jagdish Gediya5e386592024-06-19 08:50:45 +0000100 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) +
101 MPAM_SLCCFG_CTL_OFFSET;
102 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) +
103 MPAM_SLCCFG_CTL_OFFSET;
Jagdish Gediyaebaa6bf2024-01-11 10:49:46 +0000104
105 mmio_clrsetbits_32(slccfg_ctl_ns,
106 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
107 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
108 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
109 mmio_clrsetbits_32(slccfg_ctl_s,
110 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK),
111 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) |
112 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT));
113 }
114}
Leo Yan7d51bf82024-05-22 15:42:46 +0100115#endif
Usama Arifbec5afd2020-04-17 16:13:39 +0100116
117void bl31_platform_setup(void)
118{
Leo Yan01c72432024-05-31 13:57:36 +0100119 psa_status_t status;
120
Usama Ariff1513622021-04-09 17:07:41 +0100121 tc_bl31_common_platform_setup();
Jagdish Gediya35173432024-06-19 08:57:47 +0000122#if (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4)
Jagdish Gediya5ae7c382023-12-18 05:56:00 +0000123 enable_ns_mcn_pmu();
Jagdish Gediya35173432024-06-19 08:57:47 +0000124#endif /* (TARGET_PLATFORM == 3) || (TARGET_PLATFORM == 4) */
125#if TARGET_PLATFORM == 3
Jagdish Gediyaebaa6bf2024-01-11 10:49:46 +0000126 set_mcn_slc_alloc_mode();
Jagdish Gediya16a0f1c2024-02-02 06:01:44 +0000127 plat_arm_ni_setup(NCI_BASE_ADDR);
Jagdish Gediya5ae7c382023-12-18 05:56:00 +0000128#endif
Leo Yan01c72432024-05-31 13:57:36 +0100129
130 /* Initialise RSE communication channel */
Yann Gautier9b0ccd72024-10-04 18:49:35 +0200131 status = plat_rse_comms_init();
Leo Yan01c72432024-05-31 13:57:36 +0100132 if (status != PSA_SUCCESS) {
133 ERROR("Failed to initialize RSE communication channel - psa_status = %d\n", status);
134 }
Usama Arifbec5afd2020-04-17 16:13:39 +0100135}
136
Leo Yan8dd7d432024-05-22 15:41:37 +0100137scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused)
Usama Arifbec5afd2020-04-17 16:13:39 +0100138{
139
Leo Yan8dd7d432024-05-22 15:41:37 +0100140 return &tc_scmi_plat_info;
Usama Arifbec5afd2020-04-17 16:13:39 +0100141
142}
143
144void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
145 u_register_t arg2, u_register_t arg3)
146{
Jayanth Dodderi Chidanand14db0d52025-03-20 12:06:08 +0000147 /* Initialize the console to provide early debug support */
148 arm_console_boot_init();
149
150 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
Usama Arifa49bd492021-08-17 17:57:10 +0100151
Jayanth Dodderi Chidanandcdb732c2025-03-01 18:17:23 +0000152#if !TRANSFER_LIST
Usama Arifa49bd492021-08-17 17:57:10 +0100153 /* Fill the properties struct with the info from the config dtb */
154 fconf_populate("FW_CONFIG", arg1);
Jayanth Dodderi Chidanandcdb732c2025-03-01 18:17:23 +0000155#endif
Usama Arifbec5afd2020-04-17 16:13:39 +0100156}
157
laurenw-arm4c4181c2023-05-04 14:55:37 -0500158#ifdef PLATFORM_TESTS
Sandrine Bailleux27fba522023-05-05 15:44:26 +0200159static __dead2 void tc_run_platform_tests(void)
Usama Arifbec5afd2020-04-17 16:13:39 +0100160{
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200161 int tests_failed;
162
163 printf("\nStarting platform tests...\n");
Mate Toth-Pal14ba4af2022-10-21 14:24:49 +0200164
Tamas Ban15b79da2023-04-21 09:31:48 +0200165#ifdef PLATFORM_TEST_NV_COUNTERS
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200166 tests_failed = nv_counter_test();
laurenw-arm116f10c2023-06-13 16:43:39 -0500167#elif PLATFORM_TEST_ROTPK
168 tests_failed = rotpk_test();
Tamas Ban15b79da2023-04-21 09:31:48 +0200169#elif PLATFORM_TEST_TFM_TESTSUITE
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200170 tests_failed = run_platform_tests();
laurenw-arm2ce1e352023-02-07 13:40:05 -0600171#endif
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200172
173 printf("Platform tests %s.\n",
174 (tests_failed != 0) ? "failed" : "succeeded");
175
Sandrine Bailleuxe1da6c42023-05-05 13:59:07 +0200176 /* Suspend booting, no matter the tests outcome. */
Sandrine Bailleuxf0f42fb2023-05-05 15:59:00 +0200177 printf("Suspend booting...\n");
Mate Toth-Pal14ba4af2022-10-21 14:24:49 +0200178 plat_error_handler(-1);
Sandrine Bailleux27fba522023-05-05 15:44:26 +0200179}
180#endif
181
182void tc_bl31_common_platform_setup(void)
183{
184 arm_bl31_platform_setup();
185
186#ifdef PLATFORM_TESTS
187 tc_run_platform_tests();
laurenw-arm481ac282023-05-03 12:48:55 -0500188#endif
Usama Arifbec5afd2020-04-17 16:13:39 +0100189}
190
191const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
192{
193 return css_scmi_override_pm_ops(ops);
194}
Usama Arifa49bd492021-08-17 17:57:10 +0100195
196void __init bl31_plat_arch_setup(void)
197{
198 arm_bl31_plat_arch_setup();
199
Jayanth Dodderi Chidanandcdb732c2025-03-01 18:17:23 +0000200 /*
201 * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List
202 * as an entry with the tag TL_TAG_FDT. In this case, the configuration
203 * is already available, so the fconf_populate mechanism is not needed.
204 * The code block below is only required when TRANSFER_LIST is not used.
205 */
206#if !TRANSFER_LIST
Usama Arifa49bd492021-08-17 17:57:10 +0100207 /* HW_CONFIG was also loaded by BL2 */
208 const struct dyn_cfg_dtb_info_t *hw_config_info;
209
210 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
211 assert(hw_config_info != NULL);
212
213 fconf_populate("HW_CONFIG", hw_config_info->config_addr);
Jayanth Dodderi Chidanandcdb732c2025-03-01 18:17:23 +0000214#endif
Usama Arifa49bd492021-08-17 17:57:10 +0100215}
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500216
Govindraj Raja436ea5e2023-05-10 14:50:36 -0500217#if defined(SPD_spmd) && (SPMC_AT_EL3 == 0)
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500218void tc_bl31_plat_runtime_setup(void)
219{
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500220 /* Start secure watchdog timer. */
221 plat_arm_secure_wdt_start();
Salman Nabi442b0752024-02-19 17:03:44 +0000222
223 arm_bl31_plat_runtime_setup();
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500224}
225
226void bl31_plat_runtime_setup(void)
227{
228 tc_bl31_plat_runtime_setup();
229}
230
231/*
232 * Platform handler for Group0 secure interrupt.
233 */
234int plat_spmd_handle_group0_interrupt(uint32_t intid)
235{
236 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */
237 if (intid == SBSA_SECURE_WDOG_INTID) {
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500238 /* Refresh the timer. */
239 plat_arm_secure_wdt_refresh();
240
Madhukar Pappireddye108df22023-03-22 15:40:40 -0500241 return 0;
242 }
243
244 return -1;
245}
Govindraj Raja436ea5e2023-05-10 14:50:36 -0500246#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/