Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <assert.h> |
Varun Wadekar | 66ff012 | 2016-04-26 11:34:54 -0700 | [diff] [blame] | 32 | #include <bl_common.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 33 | #include <debug.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 34 | #include <platform_def.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 35 | #include <smmu.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 36 | #include <string.h> |
| 37 | #include <tegra_private.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 38 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 39 | /* |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 40 | * Save SMMU settings before "System Suspend" to TZDRAM |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 41 | */ |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 42 | void tegra_smmu_save_context(uint64_t smmu_ctx_addr) |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 43 | { |
| 44 | uint32_t i; |
Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame^] | 45 | smmu_regs_t *smmu_ctx_regs; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 46 | #if DEBUG |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 47 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 48 | uint64_t tzdram_base = params_from_bl2->tzdram_base; |
| 49 | uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 50 | uint32_t reg_id1, pgshift, cb_size; |
| 51 | |
| 52 | /* sanity check SMMU settings c*/ |
| 53 | reg_id1 = mmio_read_32((TEGRA_SMMU_BASE + SMMU_GNSR0_IDR1)); |
| 54 | pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12; |
| 55 | cb_size = (2 << pgshift) * \ |
| 56 | (1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1)); |
| 57 | |
| 58 | assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE))); |
| 59 | #endif |
| 60 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 61 | assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end)); |
| 62 | |
Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame^] | 63 | /* get SMMU context table */ |
| 64 | smmu_ctx_regs = plat_get_smmu_ctx(); |
| 65 | assert(smmu_ctx_regs); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 66 | |
| 67 | /* save SMMU register values */ |
Pritesh Raithatha | c88654f | 2017-01-02 20:11:32 +0530 | [diff] [blame^] | 68 | for (i = 1; i < smmu_ctx_regs[0].val; i++) |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 69 | smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg); |
| 70 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 71 | /* Save SMMU config settings */ |
| 72 | memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs, |
| 73 | sizeof(smmu_ctx_regs)); |
| 74 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 75 | /* save the SMMU table address */ |
| 76 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 77 | (uint32_t)smmu_ctx_addr); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 78 | mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI, |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 79 | (uint32_t)(smmu_ctx_addr >> 32)); |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 80 | } |
| 81 | |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 82 | #define SMMU_NUM_CONTEXTS 64 |
| 83 | #define SMMU_CONTEXT_BANK_MAX_IDX 64 |
| 84 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 85 | /* |
| 86 | * Init SMMU during boot or "System Suspend" exit |
| 87 | */ |
| 88 | void tegra_smmu_init(void) |
| 89 | { |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 90 | uint32_t val, i, ctx_base; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 91 | |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 92 | /* Program the SMMU pagesize and reset CACHE_LOCK bit */ |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 93 | val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR); |
| 94 | val |= SMMU_GSR0_PGSIZE_64K; |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 95 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 96 | tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val); |
| 97 | |
| 98 | /* reset CACHE LOCK bit for NS Aux. Config. Register */ |
| 99 | val = tegra_smmu_read_32(SMMU_GNSR_ACR); |
| 100 | val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 101 | tegra_smmu_write_32(SMMU_GNSR_ACR, val); |
| 102 | |
| 103 | /* disable TCU prefetch for all contexts */ |
| 104 | ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) + SMMU_CBn_ACTLR; |
| 105 | for (i = 0; i < SMMU_CONTEXT_BANK_MAX_IDX; i++) { |
| 106 | val = tegra_smmu_read_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i)); |
| 107 | val &= ~SMMU_CBn_ACTLR_CPRE_BIT; |
| 108 | tegra_smmu_write_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i), val); |
| 109 | } |
| 110 | |
| 111 | /* set CACHE LOCK bit for NS Aux. Config. Register */ |
| 112 | val = tegra_smmu_read_32(SMMU_GNSR_ACR); |
| 113 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
| 114 | tegra_smmu_write_32(SMMU_GNSR_ACR, val); |
| 115 | |
| 116 | /* set CACHE LOCK bit for S Aux. Config. Register */ |
| 117 | val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR); |
| 118 | val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 119 | tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val); |
| 120 | } |