Okash Khawaja | f5445fd | 2022-04-21 10:59:34 +0100 | [diff] [blame] | 1 | /* |
Govindraj Raja | 615e9d6 | 2023-06-15 11:07:31 -0500 | [diff] [blame] | 2 | * Copyright (c) 2022-2023, Google LLC. All rights reserved. |
Okash Khawaja | f5445fd | 2022-04-21 10:59:34 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <asm_macros.S> |
| 8 | #include <cortex_x1.h> |
| 9 | #include <cpu_macros.S> |
Okash Khawaja | bc6167c | 2022-04-21 13:15:56 +0100 | [diff] [blame] | 10 | #include "wa_cve_2022_23960_bhb_vector.S" |
Okash Khawaja | f5445fd | 2022-04-21 10:59:34 +0100 | [diff] [blame] | 11 | |
| 12 | /* Hardware handled coherency */ |
| 13 | #if HW_ASSISTED_COHERENCY == 0 |
| 14 | #error "Cortex-X1 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 15 | #endif |
| 16 | |
| 17 | /* 64-bit only core */ |
| 18 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 19 | #error "Cortex-X1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 20 | #endif |
| 21 | |
Okash Khawaja | bc6167c | 2022-04-21 13:15:56 +0100 | [diff] [blame] | 22 | #if WORKAROUND_CVE_2022_23960 |
| 23 | wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1 |
| 24 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 25 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 26 | workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305 |
Govindraj Raja | 615e9d6 | 2023-06-15 11:07:31 -0500 | [diff] [blame] | 27 | mrs x0, CORTEX_X1_ACTLR2_EL1 |
| 28 | orr x0, x0, #BIT(1) |
| 29 | msr CORTEX_X1_ACTLR2_EL1, x0 |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 30 | workaround_reset_end cortex_x1, ERRATUM(1688305) |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 31 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 32 | check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0) |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 33 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 34 | workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534 |
Govindraj Raja | 615e9d6 | 2023-06-15 11:07:31 -0500 | [diff] [blame] | 35 | mrs x1, CORTEX_X1_ACTLR2_EL1 |
| 36 | orr x1, x1, #BIT(2) |
| 37 | msr CORTEX_X1_ACTLR2_EL1, x1 |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 38 | workaround_reset_end cortex_x1, ERRATUM(1821534) |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 39 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 40 | check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0) |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 41 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 42 | workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429 |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 43 | mrs x0, CORTEX_X1_CPUECTLR_EL1 |
Okash Khawaja | 8b9850e | 2023-04-28 13:18:28 +0100 | [diff] [blame] | 44 | orr x0, x0, #BIT(53) |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 45 | msr CORTEX_X1_CPUECTLR_EL1, x0 |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 46 | workaround_reset_end cortex_x1, ERRATUM(1827429) |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 47 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 48 | check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0) |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 49 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 50 | check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Okash Khawaja | baee390 | 2022-04-21 12:20:21 +0100 | [diff] [blame] | 51 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 52 | workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 53 | #if IMAGE_BL31 |
Okash Khawaja | bc6167c | 2022-04-21 13:15:56 +0100 | [diff] [blame] | 54 | /* |
| 55 | * The Cortex-X1 generic vectors are overridden to apply errata |
| 56 | * mitigation on exception entry from lower ELs. |
| 57 | */ |
| 58 | adr x0, wa_cve_vbar_cortex_x1 |
| 59 | msr vbar_el3, x0 |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 60 | #endif /* IMAGE_BL31 */ |
| 61 | workaround_reset_end cortex_x1, CVE(2022, 23960) |
Okash Khawaja | bc6167c | 2022-04-21 13:15:56 +0100 | [diff] [blame] | 62 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 63 | cpu_reset_func_start cortex_x1 |
| 64 | cpu_reset_func_end cortex_x1 |
Okash Khawaja | f5445fd | 2022-04-21 10:59:34 +0100 | [diff] [blame] | 65 | |
| 66 | /* --------------------------------------------- |
| 67 | * HW will do the cache maintenance while powering down |
| 68 | * --------------------------------------------- |
| 69 | */ |
| 70 | func cortex_x1_core_pwr_dwn |
| 71 | /* --------------------------------------------- |
| 72 | * Enable CPU power down bit in power control register |
| 73 | * --------------------------------------------- |
| 74 | */ |
| 75 | mrs x0, CORTEX_X1_CPUPWRCTLR_EL1 |
| 76 | orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK |
| 77 | msr CORTEX_X1_CPUPWRCTLR_EL1, x0 |
| 78 | isb |
| 79 | ret |
| 80 | endfunc cortex_x1_core_pwr_dwn |
| 81 | |
Govindraj Raja | 8cb6c5b | 2023-06-15 11:18:20 -0500 | [diff] [blame^] | 82 | errata_report_shim cortex_x1 |
Okash Khawaja | f5445fd | 2022-04-21 10:59:34 +0100 | [diff] [blame] | 83 | |
| 84 | /* --------------------------------------------- |
| 85 | * This function provides Cortex X1 specific |
| 86 | * register information for crash reporting. |
| 87 | * It needs to return with x6 pointing to |
| 88 | * a list of register names in ascii and |
| 89 | * x8 - x15 having values of registers to be |
| 90 | * reported. |
| 91 | * --------------------------------------------- |
| 92 | */ |
| 93 | .section .rodata.cortex_x1_regs, "aS" |
| 94 | cortex_x1_regs: /* The ascii list of register names to be reported */ |
| 95 | .asciz "cpuectlr_el1", "" |
| 96 | |
| 97 | func cortex_x1_cpu_reg_dump |
| 98 | adr x6, cortex_x1_regs |
| 99 | mrs x8, CORTEX_X1_CPUECTLR_EL1 |
| 100 | ret |
| 101 | endfunc cortex_x1_cpu_reg_dump |
| 102 | |
| 103 | declare_cpu_ops cortex_x1, CORTEX_X1_MIDR, \ |
| 104 | cortex_x1_reset_func, \ |
| 105 | cortex_x1_core_pwr_dwn |