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Jens Wiklander52c798e2015-12-07 14:37:10 +01001/*
2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jens Wiklander52c798e2015-12-07 14:37:10 +01005 */
6
Jens Wiklander52c798e2015-12-07 14:37:10 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Jens Wiklander52c798e2015-12-07 14:37:10 +01009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch.h>
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14
Jens Wiklander52c798e2015-12-07 14:37:10 +010015#include "qemu_private.h"
16
Chen Baozif7d9aa82023-02-20 10:50:15 +000017#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
18 bl1_tzram_layout.total_base, \
19 bl1_tzram_layout.total_size, \
20 MT_MEMORY | MT_RW | EL3_PAS)
21
22#define MAP_BL1_RO MAP_REGION_FLAT( \
23 BL_CODE_BASE, \
24 BL1_CODE_END - BL_CODE_BASE, \
25 MT_CODE | EL3_PAS), \
26 MAP_REGION_FLAT( \
27 BL1_RO_DATA_BASE, \
28 BL1_RO_DATA_END \
29 - BL_RO_DATA_BASE, \
30 MT_RO_DATA | EL3_PAS)
31
32#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
33 BL_COHERENT_RAM_BASE, \
34 BL_COHERENT_RAM_END \
35 - BL_COHERENT_RAM_BASE, \
36 MT_DEVICE | MT_RW | EL3_PAS)
37
Jens Wiklander52c798e2015-12-07 14:37:10 +010038/* Data structure which holds the extents of the trusted SRAM for BL1*/
39static meminfo_t bl1_tzram_layout;
40
41
42meminfo_t *bl1_plat_sec_mem_layout(void)
43{
44 return &bl1_tzram_layout;
45}
46
47/*******************************************************************************
48 * Perform any BL1 specific platform actions.
49 ******************************************************************************/
50void bl1_early_platform_setup(void)
51{
Jens Wiklander52c798e2015-12-07 14:37:10 +010052 /* Initialize the console to provide early debug support */
Michalis Pappascca6cb72018-03-04 15:43:38 +080053 qemu_console_init();
Jens Wiklander52c798e2015-12-07 14:37:10 +010054
55 /* Allow BL1 to see the whole Trusted RAM */
56 bl1_tzram_layout.total_base = BL_RAM_BASE;
57 bl1_tzram_layout.total_size = BL_RAM_SIZE;
Jens Wiklander52c798e2015-12-07 14:37:10 +010058}
59
60/******************************************************************************
61 * Perform the very early platform specific architecture setup. This only
62 * does basic initialization. Later architectural setup (bl1_arch_setup())
63 * does not do anything platform specific.
64 *****************************************************************************/
Julius Werner8e0ef0f2019-07-09 14:02:43 -070065#ifdef __aarch64__
Etienne Carriere911de8c2018-02-02 13:23:22 +010066#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__)
Julius Werner8e0ef0f2019-07-09 14:02:43 -070067#else
68#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
Etienne Carriere911de8c2018-02-02 13:23:22 +010069#endif
70
Jens Wiklander52c798e2015-12-07 14:37:10 +010071void bl1_plat_arch_setup(void)
72{
Chen Baozif7d9aa82023-02-20 10:50:15 +000073 const mmap_region_t bl_regions[] = {
74 MAP_BL1_TOTAL,
75 MAP_BL1_RO,
76 MAP_BL_COHERENT_RAM,
77 {0}
78 };
79
80 setup_page_tables(bl_regions, plat_qemu_get_mmap());
81#ifdef __aarch64__
82 enable_mmu_el3(0);
83#else
84 enable_mmu_svc_mon(0);
85#endif
Jens Wiklander52c798e2015-12-07 14:37:10 +010086}
87
88void bl1_platform_setup(void)
89{
90 plat_qemu_io_setup();
91}