blob: 0854fec0052bcd420a606062620806b276e6319d [file] [log] [blame]
Boyan Karatoteve7d7c272023-01-25 16:55:18 +00001/*
2 * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef CPU_OPS_H
8#define CPU_OPS_H
9
10#include <arch.h>
11
12#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
13 (MIDR_PN_MASK << MIDR_PN_SHIFT)
14
15/* Hardcode to keep compatible with assembly. sizeof(uintptr_t) */
16#if __aarch64__
17#define CPU_WORD_SIZE 8
18#else
19#define CPU_WORD_SIZE 4
20#endif /* __aarch64__ */
21
22/* The number of CPU operations allowed */
23#define CPU_MAX_PWR_DWN_OPS 2
24/* Special constant to specify that CPU has no reset function */
25#define CPU_NO_RESET_FUNC 0
26
27#if __aarch64__
28#define CPU_NO_EXTRA1_FUNC 0
29#define CPU_NO_EXTRA2_FUNC 0
30#define CPU_NO_EXTRA3_FUNC 0
31#endif /* __aarch64__ */
32
33
34/*
35 * Define the sizes of the fields in the cpu_ops structure. Word size is set per
36 * Aarch so keep these definitions the same and each can include whatever it
37 * needs.
38 */
39#define CPU_MIDR_SIZE CPU_WORD_SIZE
40#ifdef IMAGE_AT_EL3
41#define CPU_RESET_FUNC_SIZE CPU_WORD_SIZE
42#else
43#define CPU_RESET_FUNC_SIZE 0
44#endif /* IMAGE_AT_EL3 */
45#define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE
46#define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE
47#define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE
48#define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE
49/* The power down core and cluster is needed only in BL31 and BL32 */
50#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
51#define CPU_PWR_DWN_OPS_SIZE CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
52#else
53#define CPU_PWR_DWN_OPS_SIZE 0
54#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
55
56/* Fields required to print errata status */
57#if REPORT_ERRATA
58#define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE
59/* BL1 doesn't require mutual exclusion and printed flag. */
60#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
61#define CPU_ERRATA_LOCK_SIZE CPU_WORD_SIZE
62#define CPU_ERRATA_PRINTED_SIZE CPU_WORD_SIZE
63#else
64#define CPU_ERRATA_LOCK_SIZE 0
65#define CPU_ERRATA_PRINTED_SIZE 0
66#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */
67#else
68#define CPU_ERRATA_FUNC_SIZE 0
69#define CPU_ERRATA_LOCK_SIZE 0
70#define CPU_ERRATA_PRINTED_SIZE 0
71#endif /* REPORT_ERRATA */
72
73#if defined(IMAGE_BL31) && CRASH_REPORTING
74#define CPU_REG_DUMP_SIZE CPU_WORD_SIZE
75#else
76#define CPU_REG_DUMP_SIZE 0
77#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */
78
79
80/*
81 * Define the offsets to the fields in cpu_ops structure. Every offset is
82 * defined based on the offset and size of the previous field.
83 */
84#define CPU_MIDR 0
85#define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE
86#if __aarch64__
87#define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
88#define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
89#define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
90#define CPU_E_HANDLER_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE
91#define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
92#else
93#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
94#endif /* __aarch64__ */
95#define CPU_ERRATA_FUNC CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
96#define CPU_ERRATA_LOCK CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
97#define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
98#if __aarch64__
99#define CPU_REG_DUMP CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
100#define CPU_OPS_SIZE CPU_REG_DUMP + CPU_REG_DUMP_SIZE
101#else
102#define CPU_OPS_SIZE CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
103#endif /* __aarch64__ */
104
105#endif /* CPU_OPS_H */