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Soby Mathewc6820d12016-05-09 17:49:55 +01001/*
johpow01fa59c6f2020-10-02 13:41:11 -05002 * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
Florian Lugoud4e25032021-09-08 12:40:24 +02003 * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
Soby Mathewc6820d12016-05-09 17:49:55 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathewc6820d12016-05-09 17:49:55 +01006 */
7
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +00008#ifndef ARCH_HELPERS_H
9#define ARCH_HELPERS_H
Soby Mathewc6820d12016-05-09 17:49:55 +010010
Andre Przywara821d6c22023-05-23 10:34:38 +010011#include <assert.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010012#include <cdefs.h>
Masahiro Yamada019b4f82020-04-02 15:35:19 +090013#include <stdbool.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010014#include <stdint.h>
Antonio Nino Diaz4b32e622018-08-16 16:52:57 +010015#include <string.h>
Soby Mathewc6820d12016-05-09 17:49:55 +010016
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <arch.h>
18
Soby Mathewc6820d12016-05-09 17:49:55 +010019/**********************************************************************
20 * Macros which create inline functions to read or write CPU system
21 * registers
22 *********************************************************************/
23
24#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
25static inline void write_## _name(u_register_t v) \
26{ \
27 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
28}
29
30#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
31static inline u_register_t read_ ## _name(void) \
32{ \
33 u_register_t v; \
34 __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
35 return v; \
36}
37
38/*
39 * The undocumented %Q and %R extended asm are used to implemented the below
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000040 * 64 bit `mrrc` and `mcrr` instructions.
Soby Mathewc6820d12016-05-09 17:49:55 +010041 */
Soby Mathewc6820d12016-05-09 17:49:55 +010042
43#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
44static inline void write64_## _name(uint64_t v) \
45{ \
46 __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
47}
48
49#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \
50static inline uint64_t read64_## _name(void) \
51{ uint64_t v; \
52 __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
53 return v; \
54}
55
56#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
57static inline u_register_t read_ ## _name(void) \
58{ \
59 u_register_t v; \
60 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
61 return v; \
62}
63
64#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
65static inline void write_ ## _name(u_register_t v) \
66{ \
67 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
68}
69
70#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
71static inline void write_ ## _name(const u_register_t v) \
72{ \
73 __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
74}
75
76/* Define read function for coproc register */
77#define DEFINE_COPROCR_READ_FUNC(_name, ...) \
78 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__)
79
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080/* Define write function for coproc register */
81#define DEFINE_COPROCR_WRITE_FUNC(_name, ...) \
82 _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
83
Soby Mathewc6820d12016-05-09 17:49:55 +010084/* Define read & write function for coproc register */
85#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \
86 _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \
87 _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
88
89/* Define 64 bit read function for coproc register */
90#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \
91 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__)
92
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000093/* Define 64 bit write function for coproc register */
94#define DEFINE_COPROCR_WRITE_FUNC_64(_name, ...) \
95 _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
96
Soby Mathewc6820d12016-05-09 17:49:55 +010097/* Define 64 bit read & write function for coproc register */
98#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \
99 _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \
100 _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
101
102/* Define read & write function for system register */
103#define DEFINE_SYSREG_RW_FUNCS(_name) \
104 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
105 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
106
107/**********************************************************************
108 * Macros to create inline functions for tlbi operations
109 *********************************************************************/
110
111#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
112static inline void tlbi##_op(void) \
113{ \
114 u_register_t v = 0; \
115 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
116}
117
Antonio Nino Diazab37d152018-11-22 15:38:05 +0000118#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
119static inline void bpi##_op(void) \
Antonio Nino Diazac998032017-02-27 17:23:54 +0000120{ \
121 u_register_t v = 0; \
122 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
123}
124
Soby Mathewc6820d12016-05-09 17:49:55 +0100125#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
126static inline void tlbi##_op(u_register_t v) \
127{ \
128 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
129}
130
131/* Define function for simple TLBI operation */
132#define DEFINE_TLBIOP_FUNC(_op, ...) \
133 _DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__)
134
135/* Define function for TLBI operation with register parameter */
136#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \
137 _DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__)
138
Antonio Nino Diazac998032017-02-27 17:23:54 +0000139/* Define function for simple BPI operation */
140#define DEFINE_BPIOP_FUNC(_op, ...) \
141 _DEFINE_BPIOP_FUNC(_op, __VA_ARGS__)
142
Soby Mathewc6820d12016-05-09 17:49:55 +0100143/**********************************************************************
144 * Macros to create inline functions for DC operations
145 *********************************************************************/
146#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
147static inline void dc##_op(u_register_t v) \
148{ \
149 __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
150}
151
152/* Define function for DC operation with register parameter */
153#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \
154 _DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__)
155
156/**********************************************************************
157 * Macros to create inline functions for system instructions
158 *********************************************************************/
159 /* Define function for simple system instruction */
160#define DEFINE_SYSOP_FUNC(_op) \
161static inline void _op(void) \
162{ \
163 __asm__ (#_op); \
164}
165
166
167/* Define function for system instruction with type specifier */
168#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
169static inline void _op ## _type(void) \
170{ \
Andre Przywara5c29cba2020-10-16 18:19:03 +0100171 __asm__ (#_op " " #_type : : : "memory"); \
Soby Mathewc6820d12016-05-09 17:49:55 +0100172}
173
174/* Define function for system instruction with register parameter */
175#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
176static inline void _op ## _type(u_register_t v) \
177{ \
178 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
179}
180
181void flush_dcache_range(uintptr_t addr, size_t size);
182void clean_dcache_range(uintptr_t addr, size_t size);
183void inv_dcache_range(uintptr_t addr, size_t size);
Masahiro Yamada019b4f82020-04-02 15:35:19 +0900184bool is_dcache_enabled(void);
Soby Mathewc6820d12016-05-09 17:49:55 +0100185
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000186void dcsw_op_louis(u_register_t op_type);
187void dcsw_op_all(u_register_t op_type);
188
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100189void disable_mmu_secure(void);
190void disable_mmu_icache_secure(void);
191
Soby Mathewc6820d12016-05-09 17:49:55 +0100192DEFINE_SYSOP_FUNC(wfi)
193DEFINE_SYSOP_FUNC(wfe)
194DEFINE_SYSOP_FUNC(sev)
195DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
196DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000197DEFINE_SYSOP_TYPE_FUNC(dmb, st)
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100198
199/* dmb ld is not valid for armv7/thumb machines */
200#if ARM_ARCH_MAJOR != 7
Yatharth Kochar2694cba2016-11-14 12:00:41 +0000201DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100202#endif
203
Soby Mathewc6820d12016-05-09 17:49:55 +0100204DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000205DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100206DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100207DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
Soby Mathewc6820d12016-05-09 17:49:55 +0100208DEFINE_SYSOP_FUNC(isb)
209
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100210void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3,
211 uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
212
Soby Mathewc6820d12016-05-09 17:49:55 +0100213DEFINE_SYSREG_RW_FUNCS(spsr)
214DEFINE_SYSREG_RW_FUNCS(cpsr)
215
216/*******************************************************************************
217 * System register accessor prototypes
218 ******************************************************************************/
219DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
220DEFINE_COPROCR_READ_FUNC(midr, MIDR)
Andre Przywara54d57912023-05-23 13:56:55 +0100221DEFINE_COPROCR_READ_FUNC(id_mmfr3, ID_MMFR3)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000222DEFINE_COPROCR_READ_FUNC(id_mmfr4, ID_MMFR4)
Manish V Badarkhef356f7e2021-06-29 11:44:20 +0100223DEFINE_COPROCR_READ_FUNC(id_dfr0, ID_DFR0)
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100224DEFINE_COPROCR_READ_FUNC(id_pfr0, ID_PFR0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100225DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
226DEFINE_COPROCR_READ_FUNC(isr, ISR)
227DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
228DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)
229
230DEFINE_COPROCR_RW_FUNCS(scr, SCR)
231DEFINE_COPROCR_RW_FUNCS(ctr, CTR)
232DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR)
Etienne Carriere70a004b2017-11-05 22:56:03 +0100233DEFINE_COPROCR_RW_FUNCS(actlr, ACTLR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100234DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR)
235DEFINE_COPROCR_RW_FUNCS(hcr, HCR)
236DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR)
237DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ)
238DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL)
239DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0)
240DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000241DEFINE_COPROCR_RW_FUNCS(hmair0, HMAIR0)
Soby Mathewc6820d12016-05-09 17:49:55 +0100242DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000243DEFINE_COPROCR_RW_FUNCS(htcr, HTCR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100244DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0)
245DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64)
246DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000247DEFINE_COPROCR_RW_FUNCS_64(httbr, HTTBR_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100248DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR)
249DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR)
250DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64)
251DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64)
252DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64)
253DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR)
David Cunadofee86532017-04-13 22:38:29 +0100254DEFINE_COPROCR_RW_FUNCS(hstr, HSTR)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000255DEFINE_COPROCR_RW_FUNCS(cnthp_ctl_el2, CNTHP_CTL)
256DEFINE_COPROCR_RW_FUNCS(cnthp_tval_el2, CNTHP_TVAL)
257DEFINE_COPROCR_RW_FUNCS_64(cnthp_cval_el2, CNTHP_CVAL_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100258
Antonio Nino Diazdc4ed3d2018-11-23 13:54:00 +0000259#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
260 CNTP_CTL_ENABLE_MASK)
261#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
262 CNTP_CTL_IMASK_MASK)
263#define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
264 CNTP_CTL_ISTATUS_MASK)
265
266#define set_cntp_ctl_enable(x) ((x) |= U(1) << CNTP_CTL_ENABLE_SHIFT)
267#define set_cntp_ctl_imask(x) ((x) |= U(1) << CNTP_CTL_IMASK_SHIFT)
268
269#define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
270#define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
271
Soby Mathewc6820d12016-05-09 17:49:55 +0100272DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
273DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
274DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
275DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR)
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100276DEFINE_COPROCR_RW_FUNCS(icc_rpr_el1, ICC_RPR)
Soby Mathewc6820d12016-05-09 17:49:55 +0100277DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000278DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1)
Soby Mathewc6820d12016-05-09 17:49:55 +0100279DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0)
280DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0)
281DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1)
282DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0)
283DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
284DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
285DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100286DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000287DEFINE_COPROCR_WRITE_FUNC_64(icc_sgi1r, ICC_SGI1R_EL1_64)
Florian Lugoud4e25032021-09-08 12:40:24 +0200288DEFINE_COPROCR_WRITE_FUNC_64(icc_asgi1r, ICC_ASGI1R_EL1_64)
Soby Mathewc6820d12016-05-09 17:49:55 +0100289
Manish V Badarkhe51a97112021-07-08 09:33:18 +0100290DEFINE_COPROCR_RW_FUNCS(sdcr, SDCR)
David Cunado5f55e282016-10-31 17:37:34 +0000291DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
David Cunadoc14b08e2016-11-25 00:21:59 +0000292DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
David Cunado5f55e282016-10-31 17:37:34 +0000293DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
294
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000295/*
296 * Address translation
297 */
298DEFINE_COPROCR_WRITE_FUNC(ats1cpr, ATS1CPR)
299DEFINE_COPROCR_WRITE_FUNC(ats1hr, ATS1HR)
Douglas Raillard77414632018-08-21 12:54:45 +0100300DEFINE_COPROCR_RW_FUNCS_64(par, PAR_64)
301
Etienne Carriere70a004b2017-11-05 22:56:03 +0100302DEFINE_COPROCR_RW_FUNCS(nsacr, NSACR)
303
304/* AArch32 coproc registers for 32bit MMU descriptor support */
305DEFINE_COPROCR_RW_FUNCS(prrr, PRRR)
306DEFINE_COPROCR_RW_FUNCS(nmrr, NMRR)
307DEFINE_COPROCR_RW_FUNCS(dacr, DACR)
308
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100309/* Coproc registers for 32bit AMU support */
310DEFINE_COPROCR_READ_FUNC(amcfgr, AMCFGR)
311DEFINE_COPROCR_READ_FUNC(amcgcr, AMCGCR)
johpow01fa59c6f2020-10-02 13:41:11 -0500312DEFINE_COPROCR_RW_FUNCS(amcr, AMCR)
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100313
Dimitris Papastamosdda48b02017-10-17 14:03:14 +0100314DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0)
315DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1)
316DEFINE_COPROCR_RW_FUNCS(amcntenclr0, AMCNTENCLR0)
317DEFINE_COPROCR_RW_FUNCS(amcntenclr1, AMCNTENCLR1)
318
Alexei Fedorov7e6306b2020-07-14 08:17:56 +0100319/* Coproc registers for 64bit AMU support */
Dimitris Papastamoseaf3e6d2017-11-28 13:47:06 +0000320DEFINE_COPROCR_RW_FUNCS_64(amevcntr00, AMEVCNTR00)
321DEFINE_COPROCR_RW_FUNCS_64(amevcntr01, AMEVCNTR01)
322DEFINE_COPROCR_RW_FUNCS_64(amevcntr02, AMEVCNTR02)
323DEFINE_COPROCR_RW_FUNCS_64(amevcntr03, AMEVCNTR03)
324
Soby Mathewc6820d12016-05-09 17:49:55 +0100325/*
326 * TLBI operation prototypes
327 */
328DEFINE_TLBIOP_FUNC(all, TLBIALL)
329DEFINE_TLBIOP_FUNC(allis, TLBIALLIS)
330DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA)
331DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000332DEFINE_TLBIOP_PARAM_FUNC(mvaais, TLBIMVAAIS)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100333DEFINE_TLBIOP_PARAM_FUNC(mvahis, TLBIMVAHIS)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000334
335/*
336 * BPI operation prototypes.
337 */
338DEFINE_BPIOP_FUNC(allis, BPIALLIS)
Soby Mathewc6820d12016-05-09 17:49:55 +0100339
340/*
341 * DC operation prototypes
342 */
343DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
344DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000345#if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
346DEFINE_DCOP_PARAM_FUNC(cvac, DCCIMVAC)
347#else
Soby Mathewc6820d12016-05-09 17:49:55 +0100348DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000349#endif
Soby Mathewc6820d12016-05-09 17:49:55 +0100350
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500351/*
352 * DynamIQ Shared Unit power management
353 */
354DEFINE_COPROCR_RW_FUNCS(clusterpwrdn, CLUSTERPWRDN)
355
Andre Przywara821d6c22023-05-23 10:34:38 +0100356/*
357 * RNDR is AArch64 only, so just provide a placeholder here to make the
358 * linker happy.
359 */
360static inline u_register_t read_rndr(void)
361{
362 assert(1);
363
364 return 0;
365}
366
Soby Mathewc6820d12016-05-09 17:49:55 +0100367/* Previously defined accessor functions with incomplete register names */
368#define dsb() dsbsy()
Etienne Carrierea2579862017-11-05 22:57:29 +0100369#define dmb() dmbsy()
Soby Mathewc6820d12016-05-09 17:49:55 +0100370
Jeenu Viswambharan1aa2db32018-09-05 14:23:27 +0100371/* dmb ld is not valid for armv7/thumb machines, so alias it to dmb */
372#if ARM_ARCH_MAJOR == 7
373#define dmbld() dmb()
374#endif
375
Soby Mathewc6820d12016-05-09 17:49:55 +0100376#define IS_IN_SECURE() \
377 (GET_NS_BIT(read_scr()) == 0)
378
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100379#define IS_IN_HYP() (GET_M32(read_cpsr()) == MODE32_hyp)
380#define IS_IN_SVC() (GET_M32(read_cpsr()) == MODE32_svc)
381#define IS_IN_MON() (GET_M32(read_cpsr()) == MODE32_mon)
382#define IS_IN_EL2() IS_IN_HYP()
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000383/* If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3 */
Soby Mathewc6820d12016-05-09 17:49:55 +0100384#define IS_IN_EL3() \
385 ((GET_M32(read_cpsr()) == MODE32_mon) || \
386 (IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr)))
387
Douglas Raillard77414632018-08-21 12:54:45 +0100388static inline unsigned int get_current_el(void)
389{
390 if (IS_IN_EL3()) {
391 return 3U;
392 } else if (IS_IN_EL2()) {
393 return 2U;
394 } else {
395 return 1U;
396 }
397}
398
Soby Mathewc6820d12016-05-09 17:49:55 +0100399/* Macros for compatibility with AArch64 system registers */
400#define read_mpidr_el1() read_mpidr()
401
402#define read_scr_el3() read_scr()
403#define write_scr_el3(_v) write_scr(_v)
404
405#define read_hcr_el2() read_hcr()
406#define write_hcr_el2(_v) write_hcr(_v)
407
408#define read_cpacr_el1() read_cpacr()
409#define write_cpacr_el1(_v) write_cpacr(_v)
410
411#define read_cntfrq_el0() read_cntfrq()
412#define write_cntfrq_el0(_v) write_cntfrq(_v)
413#define read_isr_el1() read_isr()
414
415#define read_cntpct_el0() read64_cntpct()
416
Yatharth Kocharf528faf2016-06-28 16:58:26 +0100417#define read_ctr_el0() read_ctr()
418
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000419#define write_icc_sgi0r_el1(_v) write64_icc_sgi0r_el1(_v)
Florian Lugoud4e25032021-09-08 12:40:24 +0200420#define write_icc_sgi1r(_v) write64_icc_sgi1r(_v)
421#define write_icc_asgi1r(_v) write64_icc_asgi1r(_v)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000422
423#define read_daif() read_cpsr()
424#define write_daif(flags) write_cpsr(flags)
425
426#define read_cnthp_cval_el2() read64_cnthp_cval_el2()
427#define write_cnthp_cval_el2(v) write64_cnthp_cval_el2(v)
428
429#define read_amcntenset0_el0() read_amcntenset0()
430#define read_amcntenset1_el0() read_amcntenset1()
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100431
Antonio Nino Diazb4e3e4b2018-11-23 15:04:01 +0000432/* Helper functions to manipulate CPSR */
433static inline void enable_irq(void)
434{
435 /*
436 * The compiler memory barrier will prevent the compiler from
437 * scheduling non-volatile memory access after the write to the
438 * register.
439 *
440 * This could happen if some initialization code issues non-volatile
441 * accesses to an area used by an interrupt handler, in the assumption
442 * that it is safe as the interrupts are disabled at the time it does
443 * that (according to program order). However, non-volatile accesses
444 * are not necessarily in program order relatively with volatile inline
445 * assembly statements (and volatile accesses).
446 */
447 COMPILER_BARRIER();
448 __asm__ volatile ("cpsie i");
449 isb();
450}
451
452static inline void enable_serror(void)
453{
454 COMPILER_BARRIER();
455 __asm__ volatile ("cpsie a");
456 isb();
457}
458
459static inline void enable_fiq(void)
460{
461 COMPILER_BARRIER();
462 __asm__ volatile ("cpsie f");
463 isb();
464}
465
466static inline void disable_irq(void)
467{
468 COMPILER_BARRIER();
469 __asm__ volatile ("cpsid i");
470 isb();
471}
472
473static inline void disable_serror(void)
474{
475 COMPILER_BARRIER();
476 __asm__ volatile ("cpsid a");
477 isb();
478}
479
480static inline void disable_fiq(void)
481{
482 COMPILER_BARRIER();
483 __asm__ volatile ("cpsid f");
484 isb();
485}
486
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000487#endif /* ARCH_HELPERS_H */