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Haojian Zhuang602362d2017-06-01 12:15:14 +08001#
Masahiro Yamada4d156802018-01-26 11:42:01 +09002# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang602362d2017-06-01 12:15:14 +08003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Haojian Zhuang1b4b4122018-01-25 16:13:05 +08007# Non-TF Boot ROM
8BL2_AT_EL3 := 1
9
Victor Chong91287682017-05-28 00:14:37 +090010# On Hikey960, the TSP can execute from TZC secure area in DRAM.
Victor Chong4d64c2b2018-02-01 00:37:49 +090011HIKEY960_TSP_RAM_LOCATION ?= dram
Victor Chong91287682017-05-28 00:14:37 +090012ifeq (${HIKEY960_TSP_RAM_LOCATION}, dram)
13 HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_DRAM_ID
14else ifeq (${HIKEY960_TSP_RAM_LOCATION}, sram)
Victor Chong4d64c2b2018-02-01 00:37:49 +090015 HIKEY960_TSP_RAM_LOCATION_ID = HIKEY960_SRAM_ID
Victor Chong91287682017-05-28 00:14:37 +090016else
17 $(error "Currently unsupported HIKEY960_TSP_RAM_LOCATION value")
18endif
19
Haojian Zhuang602362d2017-06-01 12:15:14 +080020CRASH_CONSOLE_BASE := PL011_UART6_BASE
21COLD_BOOT_SINGLE_CPU := 1
Leo Yan3886dc62020-03-02 22:15:08 +080022PLAT_PL061_MAX_GPIOS := 232
Haojian Zhuang602362d2017-06-01 12:15:14 +080023PROGRAMMABLE_RESET_ADDRESS := 1
David Cunadoc5b0c0f2017-10-31 23:19:21 +000024ENABLE_SVE_FOR_NS := 0
Haojian Zhuang32052ab2019-09-14 18:43:51 +080025PLAT_PARTITION_BLOCK_SIZE := 4096
Haojian Zhuang602362d2017-06-01 12:15:14 +080026
27# Process flags
Victor Chong91287682017-05-28 00:14:37 +090028$(eval $(call add_define,HIKEY960_TSP_RAM_LOCATION_ID))
Haojian Zhuang602362d2017-06-01 12:15:14 +080029$(eval $(call add_define,CRASH_CONSOLE_BASE))
Kaihua Zhong39ff2ee2018-07-16 17:33:48 +080030$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
Haojian Zhuang32052ab2019-09-14 18:43:51 +080031$(eval $(call add_define,PLAT_PARTITION_BLOCK_SIZE))
Haojian Zhuang602362d2017-06-01 12:15:14 +080032
Victor Chong7d787f52017-08-16 13:53:56 +090033# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
34# in the FIP if the platform requires.
35ifneq ($(BL32_EXTRA1),)
Masahiro Yamada9c5ca522018-01-26 11:42:01 +090036$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
Victor Chong7d787f52017-08-16 13:53:56 +090037endif
38ifneq ($(BL32_EXTRA2),)
Masahiro Yamada9c5ca522018-01-26 11:42:01 +090039$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
Victor Chong7d787f52017-08-16 13:53:56 +090040endif
41
Haojian Zhuang602362d2017-06-01 12:15:14 +080042USE_COHERENT_MEM := 1
43
Antonio Nino Diaz50a4d1a2019-02-01 12:22:22 +000044PLAT_INCLUDES := -Iplat/hisilicon/hikey960/include
Haojian Zhuang602362d2017-06-01 12:15:14 +080045
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +010046PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
Haojian Zhuang602362d2017-06-01 12:15:14 +080047 drivers/delay_timer/delay_timer.c \
48 drivers/delay_timer/generic_delay_timer.c \
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +010049 lib/xlat_tables/aarch64/xlat_tables.c \
50 lib/xlat_tables/xlat_tables_common.c \
Haojian Zhuang602362d2017-06-01 12:15:14 +080051 plat/hisilicon/hikey960/aarch64/hikey960_common.c \
52 plat/hisilicon/hikey960/hikey960_boardid.c
53
54HIKEY960_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
55 drivers/arm/gic/v2/gicv2_main.c \
56 drivers/arm/gic/v2/gicv2_helpers.c \
57 plat/common/plat_gicv2.c
58
59BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
Kaihua Zhong39ff2ee2018-07-16 17:33:48 +080060 drivers/arm/pl061/pl061_gpio.c \
61 drivers/gpio/gpio.c \
Haojian Zhuang602362d2017-06-01 12:15:14 +080062 drivers/io/io_block.c \
63 drivers/io/io_fip.c \
64 drivers/io/io_storage.c \
65 drivers/synopsys/ufs/dw_ufs.c \
66 drivers/ufs/ufs.c \
67 lib/cpus/aarch64/cortex_a53.S \
68 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
Haojian Zhuangd82e29d2018-03-05 13:20:33 +080069 plat/hisilicon/hikey960/hikey960_bl1_setup.c \
70 plat/hisilicon/hikey960/hikey960_bl_common.c \
Haojian Zhuang602362d2017-06-01 12:15:14 +080071 plat/hisilicon/hikey960/hikey960_io_storage.c \
72 ${HIKEY960_GIC_SOURCES}
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080073
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080074BL2_SOURCES += common/desc_image_load.c \
Kaihua Zhong39ff2ee2018-07-16 17:33:48 +080075 drivers/arm/pl061/pl061_gpio.c \
76 drivers/gpio/gpio.c \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080077 drivers/io/io_block.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080078 drivers/io/io_fip.c \
79 drivers/io/io_storage.c \
Haojian Zhuang32052ab2019-09-14 18:43:51 +080080 drivers/partition/gpt.c \
81 drivers/partition/partition.c \
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080082 drivers/synopsys/ufs/dw_ufs.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080083 drivers/ufs/ufs.c \
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080084 lib/cpus/aarch64/cortex_a53.S \
85 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080086 plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080087 plat/hisilicon/hikey960/hikey960_bl2_setup.c \
Haojian Zhuangd82e29d2018-03-05 13:20:33 +080088 plat/hisilicon/hikey960/hikey960_bl_common.c \
Haojian Zhuanga94d75d2018-01-29 12:45:28 +080089 plat/hisilicon/hikey960/hikey960_image_load.c \
Haojian Zhuang1f73c0c2017-06-01 14:03:22 +080090 plat/hisilicon/hikey960/hikey960_io_storage.c \
91 plat/hisilicon/hikey960/hikey960_mcu_load.c
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080092
Victor Chong7d787f52017-08-16 13:53:56 +090093ifeq (${SPD},opteed)
94BL2_SOURCES += lib/optee/optee_utils.c
95endif
Victor Chong2d9a42d2017-08-17 15:21:10 +090096
Haojian Zhuang1b5c2252017-06-01 15:20:46 +080097BL31_SOURCES += drivers/arm/cci/cci.c \
Leo Yan3886dc62020-03-02 22:15:08 +080098 drivers/arm/pl061/pl061_gpio.c \
99 drivers/gpio/gpio.c \
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800100 lib/cpus/aarch64/cortex_a53.S \
101 lib/cpus/aarch64/cortex_a72.S \
102 lib/cpus/aarch64/cortex_a73.S \
Antonio Nino Diaz582c2d72018-09-24 17:23:47 +0100103 plat/common/plat_psci_common.c \
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800104 plat/hisilicon/hikey960/aarch64/hikey960_helpers.S \
105 plat/hisilicon/hikey960/hikey960_bl31_setup.c \
Leo Yan3886dc62020-03-02 22:15:08 +0800106 plat/hisilicon/hikey960/hikey960_bl_common.c \
Haojian Zhuang1b5c2252017-06-01 15:20:46 +0800107 plat/hisilicon/hikey960/hikey960_pm.c \
108 plat/hisilicon/hikey960/hikey960_topology.c \
109 plat/hisilicon/hikey960/drivers/pwrc/hisi_pwrc.c \
110 plat/hisilicon/hikey960/drivers/ipc/hisi_ipc.c \
111 ${HIKEY960_GIC_SOURCES}
Victor Chongcb27a352017-07-12 01:07:29 +0900112
Teddy Reeddd3f0a82018-09-03 17:38:50 -0400113ifneq (${TRUSTED_BOARD_BOOT},0)
114
115include drivers/auth/mbedtls/mbedtls_crypto.mk
116include drivers/auth/mbedtls/mbedtls_x509.mk
117
Teddy Reeddd3f0a82018-09-03 17:38:50 -0400118AUTH_SOURCES := drivers/auth/auth_mod.c \
119 drivers/auth/crypto_mod.c \
120 drivers/auth/img_parser_mod.c \
121 drivers/auth/tbbr/tbbr_cot.c
122
123BL1_SOURCES += ${AUTH_SOURCES} \
124 plat/common/tbbr/plat_tbbr.c \
125 plat/hisilicon/hikey960/hikey960_tbbr.c \
126 plat/hisilicon/hikey960/hikey960_rotpk.S
127
128BL2_SOURCES += ${AUTH_SOURCES} \
129 plat/common/tbbr/plat_tbbr.c \
130 plat/hisilicon/hikey960/hikey960_tbbr.c \
131 plat/hisilicon/hikey960/hikey960_rotpk.S
132
133ROT_KEY = $(BUILD_PLAT)/rot_key.pem
134ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
135
136$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
137$(BUILD_PLAT)/bl1/hikey960_rotpk.o: $(ROTPK_HASH)
138$(BUILD_PLAT)/bl2/hikey960_rotpk.o: $(ROTPK_HASH)
139
140certificates: $(ROT_KEY)
141$(ROT_KEY): | $(BUILD_PLAT)
142 @echo " OPENSSL $@"
143 $(Q)openssl genrsa 2048 > $@ 2>/dev/null
144
145$(ROTPK_HASH): $(ROT_KEY)
146 @echo " OPENSSL $@"
147 $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
148 openssl dgst -sha256 -binary > $@ 2>/dev/null
149endif
150
Victor Chongcb27a352017-07-12 01:07:29 +0900151# Enable workarounds for selected Cortex-A53 errata.
152ERRATA_A53_836870 := 1
153ERRATA_A53_843419 := 1
154ERRATA_A53_855873 := 1
Leo Yan453940d2017-11-22 17:10:39 +0800155
156FIP_ALIGN := 512