blob: 95ef77c0d04b4c7e4a028875928c484e4362ce55 [file] [log] [blame]
Yatharth Kocharede39cb2016-11-14 12:01:04 +00001/*
Dimitris Papastamos47bc2ba2017-06-14 14:47:36 +01002 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
Yatharth Kocharede39cb2016-11-14 12:01:04 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Yatharth Kocharede39cb2016-11-14 12:01:04 +00005 */
6
7#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <common/bl_common.h>
10#include <common/desc_image_load.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000011#include <plat/arm/common/plat_arm.h>
Yatharth Kocharede39cb2016-11-14 12:01:04 +000012
13#if JUNO_AARCH32_EL3_RUNTIME
14/*******************************************************************************
15 * This function changes the spsr for BL32 image to bypass
16 * the check in BL1 AArch64 exception handler. This is needed in the aarch32
17 * boot flow as the core comes up in aarch64 and to enter the BL32 image a warm
18 * reset in aarch32 state is required.
19 ******************************************************************************/
Daniel Boulby07d26872018-06-27 16:45:48 +010020int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
Yatharth Kocharede39cb2016-11-14 12:01:04 +000021{
22 int err = arm_bl2_handle_post_image_load(image_id);
23
24 if (!err && (image_id == BL32_IMAGE_ID)) {
25 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
26 assert(bl_mem_params);
27 bl_mem_params->ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
28 DISABLE_ALL_EXCEPTIONS);
29 }
30
31 return err;
32}
Yatharth Kocharede39cb2016-11-14 12:01:04 +000033#endif /* JUNO_AARCH32_EL3_RUNTIME */