Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | #include <arch_helpers.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <context.h> |
Achin Gupta | ef7a28c | 2014-02-01 08:59:56 +0000 | [diff] [blame] | 36 | #include <context_mgmt.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 37 | #include <platform.h> |
| 38 | #include <stddef.h> |
Dan Handley | 714a0d2 | 2014-04-09 13:13:04 +0100 | [diff] [blame] | 39 | #include "psci_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
Achin Gupta | ef7a28c | 2014-02-01 08:59:56 +0000 | [diff] [blame] | 42 | * Per cpu non-secure contexts used to program the architectural state prior |
| 43 | * return to the normal world. |
| 44 | * TODO: Use the memory allocator to set aside memory for the contexts instead |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 45 | * of relying on platform defined constants. |
Achin Gupta | ef7a28c | 2014-02-01 08:59:56 +0000 | [diff] [blame] | 46 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 47 | static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; |
Achin Gupta | ef7a28c | 2014-02-01 08:59:56 +0000 | [diff] [blame] | 48 | |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 49 | /****************************************************************************** |
| 50 | * Define the psci capability variable. |
| 51 | *****************************************************************************/ |
| 52 | uint32_t psci_caps; |
| 53 | |
Dan Handley | 60b13e3 | 2014-05-14 15:13:16 +0100 | [diff] [blame] | 54 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 55 | * Function which initializes the 'psci_non_cpu_pd_nodes' or the |
| 56 | * 'psci_cpu_pd_nodes' corresponding to the power level. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 57 | ******************************************************************************/ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 58 | static void psci_init_pwr_domain_node(int node_idx, int parent_idx, int level) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 59 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 60 | if (level > PSCI_CPU_PWR_LVL) { |
| 61 | psci_non_cpu_pd_nodes[node_idx].level = level; |
| 62 | psci_lock_init(psci_non_cpu_pd_nodes, node_idx); |
| 63 | psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx; |
| 64 | psci_non_cpu_pd_nodes[node_idx].local_state = |
| 65 | PLAT_MAX_OFF_STATE; |
| 66 | } else { |
| 67 | psci_cpu_data_t *svc_cpu_data; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 68 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 69 | psci_cpu_pd_nodes[node_idx].parent_node = parent_idx; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 70 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 71 | /* Initialize with an invalid mpidr */ |
| 72 | psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR; |
Soby Mathew | 2b69750 | 2014-10-02 17:24:19 +0100 | [diff] [blame] | 73 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 74 | svc_cpu_data = |
| 75 | &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data); |
Soby Mathew | 2b69750 | 2014-10-02 17:24:19 +0100 | [diff] [blame] | 76 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 77 | /* Set the Affinity Info for the cores as OFF */ |
| 78 | svc_cpu_data->aff_info_state = AFF_STATE_OFF; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 79 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 80 | /* Invalidate the suspend level for the cpu */ |
| 81 | svc_cpu_data->target_pwrlvl = PSCI_INVALID_DATA; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 82 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 83 | /* Set the power state to OFF state */ |
| 84 | svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; |
Soby Mathew | 2b69750 | 2014-10-02 17:24:19 +0100 | [diff] [blame] | 85 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 86 | flush_dcache_range((uint64_t)svc_cpu_data, |
| 87 | sizeof(*svc_cpu_data)); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 88 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 89 | cm_set_context_by_index(node_idx, |
| 90 | (void *) &psci_ns_context[node_idx], |
| 91 | NON_SECURE); |
| 92 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 96 | * This functions updates cpu_start_idx and ncpus field for each of the node in |
| 97 | * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of |
| 98 | * the CPUs and check whether they match with the parent of the previous |
| 99 | * CPU. The basic assumption for this work is that children of the same parent |
| 100 | * are allocated adjacent indices. The platform should ensure this though proper |
| 101 | * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and |
| 102 | * plat_my_core_pos() APIs. |
| 103 | *******************************************************************************/ |
| 104 | static void psci_update_pwrlvl_limits(void) |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 105 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 106 | int cpu_idx, j; |
| 107 | unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; |
| 108 | unsigned int temp_index[PLAT_MAX_PWR_LVL]; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 109 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 110 | for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { |
| 111 | psci_get_parent_pwr_domain_nodes(cpu_idx, |
| 112 | PLAT_MAX_PWR_LVL, |
| 113 | temp_index); |
| 114 | for (j = PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { |
| 115 | if (temp_index[j] != nodes_idx[j]) { |
| 116 | nodes_idx[j] = temp_index[j]; |
| 117 | psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx |
| 118 | = cpu_idx; |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 119 | } |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 120 | psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; |
| 121 | } |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 122 | } |
Achin Gupta | 0959db5 | 2013-12-02 17:33:04 +0000 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 126 | * Core routine to populate the power domain tree. The tree descriptor passed by |
| 127 | * the platform is populated breadth-first and the first entry in the map |
| 128 | * informs the number of root power domains. The parent nodes of the root nodes |
| 129 | * will point to an invalid entry(-1). |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 130 | ******************************************************************************/ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 131 | static void populate_power_domain_tree(const unsigned char *topology) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 132 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 133 | unsigned int i, j = 0, num_nodes_at_lvl = 1, num_nodes_at_next_lvl; |
| 134 | unsigned int node_index = 0, parent_node_index = 0, num_children; |
| 135 | int level = PLAT_MAX_PWR_LVL; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 136 | |
| 137 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 138 | * For each level the inputs are: |
| 139 | * - number of nodes at this level in plat_array i.e. num_nodes_at_level |
| 140 | * This is the sum of values of nodes at the parent level. |
| 141 | * - Index of first entry at this level in the plat_array i.e. |
| 142 | * parent_node_index. |
| 143 | * - Index of first free entry in psci_non_cpu_pd_nodes[] or |
| 144 | * psci_cpu_pd_nodes[] i.e. node_index depending upon the level. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 145 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 146 | while (level >= PSCI_CPU_PWR_LVL) { |
| 147 | num_nodes_at_next_lvl = 0; |
Achin Gupta | ef7a28c | 2014-02-01 08:59:56 +0000 | [diff] [blame] | 148 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 149 | * For each entry (parent node) at this level in the plat_array: |
| 150 | * - Find the number of children |
| 151 | * - Allocate a node in a power domain array for each child |
| 152 | * - Set the parent of the child to the parent_node_index - 1 |
| 153 | * - Increment parent_node_index to point to the next parent |
| 154 | * - Accumulate the number of children at next level. |
Achin Gupta | ef7a28c | 2014-02-01 08:59:56 +0000 | [diff] [blame] | 155 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 156 | for (i = 0; i < num_nodes_at_lvl; i++) { |
| 157 | assert(parent_node_index <= |
| 158 | PSCI_NUM_NON_CPU_PWR_DOMAINS); |
| 159 | num_children = topology[parent_node_index]; |
Achin Gupta | ef7a28c | 2014-02-01 08:59:56 +0000 | [diff] [blame] | 160 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 161 | for (j = node_index; |
| 162 | j < node_index + num_children; j++) |
| 163 | psci_init_pwr_domain_node(j, |
| 164 | parent_node_index - 1, |
| 165 | level); |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 166 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 167 | node_index = j; |
| 168 | num_nodes_at_next_lvl += num_children; |
| 169 | parent_node_index++; |
| 170 | } |
Achin Gupta | f6b9e99 | 2014-07-31 11:19:11 +0100 | [diff] [blame] | 171 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 172 | num_nodes_at_lvl = num_nodes_at_next_lvl; |
| 173 | level--; |
Soby Mathew | 7d861ea | 2014-11-18 10:14:14 +0000 | [diff] [blame] | 174 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 175 | /* Reset the index for the cpu power domain array */ |
| 176 | if (level == PSCI_CPU_PWR_LVL) |
| 177 | node_index = 0; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 178 | } |
| 179 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 180 | /* Validate the sanity of array exported by the platform */ |
| 181 | assert(j == PLATFORM_CORE_COUNT); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 182 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 183 | #if !USE_COHERENT_MEM |
| 184 | /* Flush the non CPU power domain data to memory */ |
| 185 | flush_dcache_range((uint64_t) &psci_non_cpu_pd_nodes, |
| 186 | sizeof(psci_non_cpu_pd_nodes)); |
| 187 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | /******************************************************************************* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 191 | * This function initializes the power domain topology tree by querying the |
| 192 | * platform. The power domain nodes higher than the CPU are populated in the |
| 193 | * array psci_non_cpu_pd_nodes[] and the CPU power domains are populated in |
| 194 | * psci_cpu_pd_nodes[]. The platform exports its static topology map through the |
| 195 | * populate_power_domain_topology_tree() API. The algorithm populates the |
| 196 | * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this |
| 197 | * topology map. On a platform that implements two clusters of 2 cpus each, and |
| 198 | * supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would look |
| 199 | * like this: |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 200 | * |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 201 | * --------------------------------------------------- |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 202 | * | system node | cluster 0 node | cluster 1 node | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 203 | * --------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 204 | * |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 205 | * And populated psci_cpu_pd_nodes would look like this : |
| 206 | * <- cpus cluster0 -><- cpus cluster1 -> |
| 207 | * ------------------------------------------------ |
| 208 | * | CPU 0 | CPU 1 | CPU 2 | CPU 3 | |
| 209 | * ------------------------------------------------ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 210 | ******************************************************************************/ |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 211 | int32_t psci_setup(void) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 212 | { |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 213 | const unsigned char *topology_tree; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 214 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 215 | /* Query the topology map from the platform */ |
| 216 | topology_tree = plat_get_power_domain_tree_desc(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 218 | /* Populate the power domain arrays using the platform topology map */ |
| 219 | populate_power_domain_tree(topology_tree); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 220 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 221 | /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ |
| 222 | psci_update_pwrlvl_limits(); |
| 223 | |
| 224 | /* Populate the mpidr field of cpu node for this CPU */ |
| 225 | psci_cpu_pd_nodes[plat_my_core_pos()].mpidr = |
| 226 | read_mpidr() & MPIDR_AFFINITY_MASK; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 227 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 228 | #if !USE_COHERENT_MEM |
| 229 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 230 | * The psci_non_cpu_pd_nodes only needs flushing when it's not allocated in |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 231 | * coherent memory. |
| 232 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 233 | flush_dcache_range((uint64_t) &psci_non_cpu_pd_nodes, |
| 234 | sizeof(psci_non_cpu_pd_nodes)); |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 235 | #endif |
| 236 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 237 | flush_dcache_range((uint64_t) &psci_cpu_pd_nodes, |
| 238 | sizeof(psci_cpu_pd_nodes)); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 239 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 240 | psci_init_req_local_pwr_states(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 241 | |
| 242 | /* |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 243 | * Set the requested and target state of this CPU and all the higher |
| 244 | * power domain levels for this CPU to run. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 245 | */ |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 246 | psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 247 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 248 | plat_setup_psci_ops((uintptr_t)psci_entrypoint, |
| 249 | &psci_plat_pm_ops); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 250 | assert(psci_plat_pm_ops); |
| 251 | |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 252 | /* Initialize the psci capability */ |
| 253 | psci_caps = PSCI_GENERIC_CAP; |
| 254 | |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 255 | if (psci_plat_pm_ops->pwr_domain_off) |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 256 | psci_caps |= define_psci_cap(PSCI_CPU_OFF); |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 257 | if (psci_plat_pm_ops->pwr_domain_on && |
| 258 | psci_plat_pm_ops->pwr_domain_on_finish) |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 259 | psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64); |
Soby Mathew | 981487a | 2015-07-13 14:10:57 +0100 | [diff] [blame] | 260 | if (psci_plat_pm_ops->pwr_domain_suspend && |
| 261 | psci_plat_pm_ops->pwr_domain_suspend_finish) { |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 262 | psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64); |
Soby Mathew | 9616838 | 2014-12-17 14:47:57 +0000 | [diff] [blame] | 263 | if (psci_plat_pm_ops->get_sys_suspend_power_state) |
| 264 | psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64); |
| 265 | } |
Soby Mathew | 6cdddaf | 2015-01-07 11:10:22 +0000 | [diff] [blame] | 266 | if (psci_plat_pm_ops->system_off) |
| 267 | psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF); |
| 268 | if (psci_plat_pm_ops->system_reset) |
| 269 | psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET); |
| 270 | |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 271 | return 0; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 272 | } |