blob: 9f9d04797387128c310195639822a6ecc6a84b8f [file] [log] [blame]
Konstantin Porotchkin62a76462018-02-26 15:51:11 +02001/*
2 * Copyright (C) 2016 - 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8/* IOW unit device driver for Marvell CP110 and CP115 SoCs */
9
10#include <a8k_common.h>
11#include <arch_helpers.h>
12#include <debug.h>
13#include <iob.h>
14#include <mmio.h>
15#include <mvebu.h>
16#include <mvebu_def.h>
17
18#if LOG_LEVEL >= LOG_LEVEL_INFO
19#define DEBUG_ADDR_MAP
20#endif
21
22#define MVEBU_IOB_OFFSET (0x190000)
23#define MVEBU_IOB_MAX_WINS 16
24
25/* common defines */
26#define WIN_ENABLE_BIT (0x1)
27/* Physical address of the base of the window = {AddrLow[19:0],20`h0} */
28#define ADDRESS_SHIFT (20 - 4)
29#define ADDRESS_MASK (0xFFFFFFF0)
30#define IOB_WIN_ALIGNMENT (0x100000)
31
32/* IOB registers */
33#define IOB_WIN_CR_OFFSET(win) (iob_base + 0x0 + (0x20 * win))
34#define IOB_TARGET_ID_OFFSET (8)
35#define IOB_TARGET_ID_MASK (0xF)
36
37#define IOB_WIN_SCR_OFFSET(win) (iob_base + 0x4 + (0x20 * win))
38#define IOB_WIN_ENA_CTRL_WRITE_SECURE (0x1)
39#define IOB_WIN_ENA_CTRL_READ_SECURE (0x2)
40#define IOB_WIN_ENA_WRITE_SECURE (0x4)
41#define IOB_WIN_ENA_READ_SECURE (0x8)
42
43#define IOB_WIN_ALR_OFFSET(win) (iob_base + 0x8 + (0x20 * win))
44#define IOB_WIN_AHR_OFFSET(win) (iob_base + 0xC + (0x20 * win))
45
46uintptr_t iob_base;
47
48static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
49{
50 /* check if address is aligned to the size */
51 if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) {
52 win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT);
53 ERROR("Window %d: base address unaligned to 0x%x\n",
54 win_num, IOB_WIN_ALIGNMENT);
55 tf_printf("Align up the base address to 0x%llx\n",
56 win->base_addr);
57 }
58
59 /* size parameter validity check */
60 if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) {
61 win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT);
62 ERROR("Window %d: window size unaligned to 0x%x\n", win_num,
63 IOB_WIN_ALIGNMENT);
64 tf_printf("Aligning size to 0x%llx\n", win->win_size);
65 }
66}
67
68static void iob_enable_win(struct addr_map_win *win, uint32_t win_id)
69{
70 uint32_t iob_win_reg;
71 uint32_t alr, ahr;
72 uint64_t end_addr;
73
74 end_addr = (win->base_addr + win->win_size - 1);
75 alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
76 ahr = (uint32_t)((end_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
77
78 mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr);
79 mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr);
80
81 iob_win_reg = WIN_ENABLE_BIT;
82 iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK)
83 << IOB_TARGET_ID_OFFSET;
84 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg);
85
86}
87
88#ifdef DEBUG_ADDR_MAP
89static void dump_iob(void)
90{
91 uint32_t win_id, win_cr, alr, ahr;
92 uint8_t target_id;
93 uint64_t start, end;
94 char *iob_target_name[IOB_MAX_TID] = {
95 "CFG ", "MCI0 ", "PEX1 ", "PEX2 ",
96 "PEX0 ", "NAND ", "RUNIT", "MCI1 " };
97
98 /* Dump all IOB windows */
99 tf_printf("bank id target start end\n");
100 tf_printf("----------------------------------------------------\n");
101 for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
102 win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
103 if (win_cr & WIN_ENABLE_BIT) {
104 target_id = (win_cr >> IOB_TARGET_ID_OFFSET) &
105 IOB_TARGET_ID_MASK;
106 alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id));
107 start = ((uint64_t)alr << ADDRESS_SHIFT);
108 if (win_id != 0) {
109 ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id));
110 end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT);
111 } else {
112 /* Window #0 size is hardcoded to 16MB, as it's
113 * reserved for CP configuration space.
114 */
115 end = start + (16 << 20);
116 }
117 tf_printf("iob %02d %s 0x%016llx 0x%016llx\n",
118 win_id, iob_target_name[target_id],
119 start, end);
120 }
121 }
122}
123#endif
124
125void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base,
126 uintptr_t new_base)
127{
128 debug_enter();
129
130 iob_base = base + MVEBU_IOB_OFFSET;
131
132 NOTICE("Change the base address of AP%d-CP%d to %lx\n",
133 ap_idx, cp_idx, new_base);
134 mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT);
135
136 iob_base = new_base + MVEBU_IOB_OFFSET;
137
138 /* Make sure the address was configured by the CPU before
139 * any possible access to the CP.
140 */
141 dsb();
142
143 debug_exit();
144}
145
146int init_iob(uintptr_t base)
147{
148 struct addr_map_win *win;
149 uint32_t win_id, win_reg;
150 uint32_t win_count;
151
152 INFO("Initializing IOB Address decoding\n");
153
154 /* Get the base address of the address decoding MBUS */
155 iob_base = base + MVEBU_IOB_OFFSET;
156
157 /* Get the array of the windows and fill the map data */
158 marvell_get_iob_memory_map(&win, &win_count, base);
159 if (win_count <= 0) {
160 INFO("no windows configurations found\n");
161 return 0;
162 } else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) {
163 ERROR("IOB mem map array > than max available windows (%d)\n",
164 MVEBU_IOB_MAX_WINS);
165 win_count = MVEBU_IOB_MAX_WINS;
166 }
167
168 /* disable all IOB windows, start from win_id = 1
169 * because can't disable internal register window
170 */
171 for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) {
172 win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id));
173 win_reg &= ~WIN_ENABLE_BIT;
174 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), win_reg);
175
176 win_reg = ~IOB_WIN_ENA_CTRL_WRITE_SECURE;
177 win_reg &= ~IOB_WIN_ENA_CTRL_READ_SECURE;
178 win_reg &= ~IOB_WIN_ENA_WRITE_SECURE;
179 win_reg &= ~IOB_WIN_ENA_READ_SECURE;
180 mmio_write_32(IOB_WIN_SCR_OFFSET(win_id), win_reg);
181 }
182
183 for (win_id = 1; win_id < win_count + 1; win_id++, win++) {
184 iob_win_check(win, win_id);
185 iob_enable_win(win, win_id);
186 }
187
188#ifdef DEBUG_ADDR_MAP
189 dump_iob();
190#endif
191
192 INFO("Done IOB Address decoding Initializing\n");
193
194 return 0;
195}