/*
 * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

/dts-v1/;
#include "morello.dtsi"

/ {
	model = "Arm Morello Fixed Virtual Platform";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure-firmware@ff000000 {
			reg = <0 0xff000000 0 0x01000000>;
			no-map;
		};
	};

	/*
	 * The timings below are just to demonstrate working cpuidle.
	 * These values may be inaccurate.
	 */
	idle-states {
		entry-method = "psci";

		cluster_sleep: cluster-sleep {
			compatible = "arm,idle-state";
			arm,psci-suspend-param = <0x40000022>;
			local-timer-stop;
			entry-latency-us = <500>;
			exit-latency-us = <1000>;
			min-residency-us = <2500>;
		};

		cpu_sleep: cpu-sleep {
			compatible = "arm,idle-state";
			arm,psci-suspend-param = <0x40000002>;
			local-timer-stop;
			entry-latency-us = <150>;
			exit-latency-us = <300>;
			min-residency-us = <200>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};
				core1 {
					cpu = <&CPU1>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};
				core1 {
					cpu = <&CPU3>;
				};
			};
		};
		CPU0: cpu0@0 {
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 0>;
			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
		};
		CPU1: cpu1@100 {
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 0>;
			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
		};
		CPU2: cpu2@10000 {
			compatible = "arm,armv8";
			reg = <0x0 0x10000>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 1>;
			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
		};
		CPU3: cpu3@10100 {
			compatible = "arm,armv8";
			reg = <0x0 0x10100>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_dvfs 1>;
			cpu-idle-states = <&cpu_sleep &cluster_sleep>;
		};
	};

	/* The first bank of memory, memory map is actually provided by UEFI. */
	memory@80000000 {
		device_type = "memory";
		/* [0x80000000-0xffffffff] */
		reg = <0x00000000 0x80000000 0x0 0x80000000>;
	};

	memory@8080000000 {
		device_type = "memory";
		/* [0x8080000000-0x83ffffffff] */
		reg = <0x00000080 0x80000000 0x1 0x80000000>;
	};

	virtio_block@1c170000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c170000 0x0 0x200>;
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	};

	virtio_net@1c180000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c180000 0x0 0x200>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	};

	virtio_rng@1c190000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c190000 0x0 0x200>;
		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
	};

	virtio_p9@1c1a0000 {
		compatible = "virtio,mmio";
		reg = <0x0 0x1c1a0000 0x0 0x200>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	};

	ethernet@1d100000 {
		compatible = "smsc,lan91c111";
		reg = <0x0 0x1d100000 0x0 0x10000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};

	kmi@1c150000 {
		compatible = "arm,pl050", "arm,primecell";
		reg = <0x0 0x1c150000 0x0 0x1000>;
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
		clock-names = "KMIREFCLK", "apb_pclk";
	};

	kmi@1c160000 {
		compatible = "arm,pl050", "arm,primecell";
		reg = <0x0 0x1c160000 0x0 0x1000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
		clock-names = "KMIREFCLK", "apb_pclk";
	};

	firmware {
		scmi {
			compatible = "arm,scmi";
			mbox-names = "tx", "rx";
			mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
			shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_dvfs: protocol@13 {
				reg = <0x13>;
				#clock-cells = <1>;
			};
		};
	};

	bp_clock24mhz: clock24mhz {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "bp:clock24mhz";
	};
};

&gic {
	reg = <0x0 0x30000000 0 0x10000>,	/* GICD */
	      <0x0 0x300c0000 0 0x80000>;	/* GICR */
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};