fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
diff --git a/plat/intel/soc/n5x/include/n5x_clock_manager.h b/plat/intel/soc/n5x/include/n5x_clock_manager.h
index 14a5717..54477da 100644
--- a/plat/intel/soc/n5x/include/n5x_clock_manager.h
+++ b/plat/intel/soc/n5x/include/n5x_clock_manager.h
@@ -4,10 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef CLOCKMANAGER_H
-#define CLOCKMANAGER_H
+#ifndef N5X_SOCFPGA_CLOCKMANAGER_H
+#define N5X_SOCFPGA_CLOCKMANAGER_H
-#include "socfpga_handoff.h"
/* MACRO DEFINITION */
#define SOCFPGA_GLOBAL_TIMER 0xffd01000
@@ -56,5 +55,6 @@
uint32_t get_clk_freq(uint32_t psrc_reg);
uint32_t get_mpu_clk(void);
uint32_t get_cpu_clk(void);
+uint32_t get_mpu_periph_clk(void);
-#endif
+#endif /* N5X_SOCFPGA_CLOCKMANAGER_H */
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index a06bbc4..c86cbb7 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -8,8 +8,8 @@
#ifndef PLAT_SOCFPGA_DEF_H
#define PLAT_SOCFPGA_DEF_H
-#include "n5x_system_manager.h"
#include <platform_def.h>
+#include "n5x_system_manager.h"
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_N5X
@@ -85,7 +85,7 @@
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (get_mpu_periph_clk() * PLAT_HZ_CONVERT_TO_MHZ)
#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
/*******************************************************************************
@@ -101,6 +101,6 @@
#define L2_RESET_DONE_REG 0xFFD12218
/* Platform specific system counter */
-#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
+#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_mpu_periph_clk()
#endif /* PLAT_SOCFPGA_DEF_H */
diff --git a/plat/intel/soc/n5x/soc/n5x_clock_manager.c b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
index f32e0f8..2e3acc9 100644
--- a/plat/intel/soc/n5x/soc/n5x_clock_manager.c
+++ b/plat/intel/soc/n5x/soc/n5x_clock_manager.c
@@ -12,8 +12,7 @@
#include "n5x_clock_manager.h"
#include "n5x_system_manager.h"
-
-
+#include "socfpga_handoff.h"
uint64_t clk_get_pll_output_hz(void)
{
@@ -155,3 +154,18 @@
return cpu_clk;
}
+
+/* Return mpu_periph_clk clock frequency */
+uint32_t get_mpu_periph_clk(void)
+{
+ uint32_t mpu_periph_clk = 0;
+ /* mpu_periph_clk is mpu_clk, via a static /4 divider */
+ mpu_periph_clk = (get_mpu_clk()/4)/PLAT_HZ_CONVERT_TO_MHZ;
+ return mpu_periph_clk;
+}
+
+/* Return mpu_periph_clk tick */
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return PLAT_SYS_COUNTER_FREQ_IN_TICKS;
+}