| commit | 7dfbca73596a5d6ef745a4cb43d3aac4c8f8ee31 | [log] [tgz] |
|---|---|---|
| author | Steven Kao <skao@nvidia.com> | Tue Jul 25 12:44:32 2017 +0800 |
| committer | Varun Wadekar <vwadekar@nvidia.com> | Thu Nov 28 11:14:21 2019 -0800 |
| tree | bb5e437a2b44babbb1adb6d19e0fb2d1e62c738c | |
| parent | 978887fd5a0efc0adac5427c2a09d44f028ba310 [diff] |
Tegra194: smmu: ISO support The FPGA configuration is encoded in the high byte of MISCREG_EMU_REVID. Configs GPU and MAX (encoded as 2 and 3) support the ISO SMMU, while BASE (encoded as 1) does not. This patch implements this encoding and returns the proper number of SMMU instances. Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe Signed-off-by: Steven Kao <skao@nvidia.com>