diff --git a/plat/intel/soc/n5x/include/n5x_system_manager.h b/plat/intel/soc/n5x/include/n5x_system_manager.h
index b628219..3610a6e 100644
--- a/plat/intel/soc/n5x/include/n5x_system_manager.h
+++ b/plat/intel/soc/n5x/include/n5x_system_manager.h
@@ -143,6 +143,18 @@
 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8		0x278
 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9		0x27C
 
+/* QSPI ECC from SDM register */
+#define SOCFPGA_ECC_QSPI_CTRL						0x08
+#define SOCFPGA_ECC_QSPI_ERRINTEN					0x10
+#define SOCFPGA_ECC_QSPI_ERRINTENS					0x14
+#define SOCFPGA_ECC_QSPI_ERRINTENR					0x18
+#define SOCFPGA_ECC_QSPI_INTMODE					0x1C
+#define SOCFPGA_ECC_QSPI_INTSTAT					0x20
+#define SOCFPGA_ECC_QSPI_INTTEST					0x24
+#define SOCFPGA_ECC_QSPI_ECC_ACCCTRL					0x78
+#define SOCFPGA_ECC_QSPI_ECC_STARTACC					0x7C
+#define SOCFPGA_ECC_QSPI_ECC_WDCTRL					0x80
+
 #define DMA0_STREAM_CTRL_REG				0x10D1217C
 #define DMA1_STREAM_CTRL_REG				0x10D12180
 #define SDM_STREAM_CTRL_REG				0x10D12184
@@ -186,6 +198,9 @@
 #define RMMUSECSID_REG_VAL				BIT(5)
 
 /* Macros */
+#define SOCFPGA_ECC_QSPI(_reg)						(SOCFPGA_ECC_QSPI_REG_BASE \
+									+ (SOCFPGA_ECC_QSPI_##_reg))
+
 #define SOCFPGA_SYSMGR(_reg)				(SOCFPGA_SYSMGR_REG_BASE \
 								+ (SOCFPGA_SYSMGR_##_reg))
 #define ENABLE_STREAMID					WSTREAMIDEN_REG_CTRL | \
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index 93b0c18..3568e3b 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -29,11 +29,10 @@
 /* Register Mapping */
 #define SOCFPGA_CCU_NOC_REG_BASE		U(0xf7000000)
 #define SOCFPGA_F2SDRAMMGR_REG_BASE		U(0xf8024000)
-
 #define SOCFPGA_MMC_REG_BASE			U(0xff808000)
-
 #define SOCFPGA_RSTMGR_REG_BASE			U(0xffd11000)
 #define SOCFPGA_SYSMGR_REG_BASE			U(0xffd12000)
+#define SOCFPGA_ECC_QSPI_REG_BASE				U(0xffa22000)
 
 #define SOCFPGA_L4_PER_SCR_REG_BASE			U(0xffd21000)
 #define SOCFPGA_L4_SYS_SCR_REG_BASE			U(0xffd21100)