zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.
Example:
Consider a case of nand_ref clock which has 2 divisor and 1 mux.
The frequency of mux clock is 1500MHz and default value of div1 and
div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
When driver requests 80MHz for nand_ref clock, clock framework will
adjust the div2 value to 1 (setting div2 value 2 results final clock
to 50MHz which is more inaccurate compare to 100Mhz) which results
final clock to 100MHz.
Ideally the value of div1 and div2 should be updated to 19 and 1
respectively so that final clock goes to around 78MHz.
This patch fixes above problem by allowing change in div1 value.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
1 file changed