feat(versal): add infrastructure to handle multiple interrupts
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index d151842..ecd8d08 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -192,10 +193,12 @@
* @data - array of PAYLOAD_ARG_CNT elements
* @flag - 0 - Call from secure source
* 1 - Call from non-secure source
+ * @ack - 0 - Do not ack IPI after reading payload
+ * 1 - Ack IPI after reading payload
*
* Read value from ipi buffer response buffer.
*/
-void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag)
+void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag, uint32_t ack)
{
/* Return if interrupt is not from PMU */
if (pm_ipi_irq_status(primary_proc) == 0) {
@@ -203,7 +206,10 @@
}
pm_ipi_buff_read_callb(data, count);
- pm_ipi_irq_clear(primary_proc);
+
+ if (ack != 0U) {
+ pm_ipi_irq_clear(primary_proc);
+ }
}
/**