Merge "Add Cortex-A65/AE to the supported FVP list" into integration
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
index daa2e66..6e63b43 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -8,34 +8,181 @@
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
-&CPU0 {
- reg = <0x0 0x0>;
-};
+&CPU_MAP {
+ /delete-node/ cluster0;
-&CPU1 {
- reg = <0x0 0x1>;
+ cluster0 {
+ core0 {
+ thread0 {
+ cpu = <&CPU0>;
+ };
+ thread1 {
+ cpu = <&CPU1>;
+ };
+ };
+ core1 {
+ thread0 {
+ cpu = <&CPU2>;
+ };
+ thread1 {
+ cpu = <&CPU3>;
+ };
+ };
+ core2 {
+ thread0 {
+ cpu = <&CPU4>;
+ };
+ thread1 {
+ cpu = <&CPU5>;
+ };
+ };
+ core3 {
+ thread0 {
+ cpu = <&CPU6>;
+ };
+ thread1 {
+ cpu = <&CPU7>;
+ };
+ };
+ core4 {
+ thread0 {
+ cpu = <&CPU8>;
+ };
+ thread1 {
+ cpu = <&CPU9>;
+ };
+ };
+ core5 {
+ thread0 {
+ cpu = <&CPU10>;
+ };
+ thread1 {
+ cpu = <&CPU11>;
+ };
+ };
+ core6 {
+ thread0 {
+ cpu = <&CPU12>;
+ };
+ thread1 {
+ cpu = <&CPU13>;
+ };
+ };
+ core7 {
+ thread0 {
+ cpu = <&CPU14>;
+ };
+ thread1 {
+ cpu = <&CPU15>;
+ };
+ };
+ };
};
-&CPU2 {
- reg = <0x0 0x100>;
-};
+/ {
+ cpus {
+ CPU0:cpu@0 {
+ reg = <0x0 0x0>;
+ };
-&CPU3 {
- reg = <0x0 0x101>;
-};
+ CPU1:cpu@1 {
+ reg = <0x0 0x1>;
+ };
-&CPU4 {
- reg = <0x0 0x200>;
-};
+ CPU2:cpu@2 {
+ reg = <0x0 0x100>;
+ };
-&CPU5 {
- reg = <0x0 0x201>;
-};
+ CPU3:cpu@3 {
+ reg = <0x0 0x101>;
+ };
-&CPU6 {
- reg = <0x0 0x300>;
-};
+ CPU4:cpu@100 {
+ reg = <0x0 0x200>;
+ };
+
+ CPU5:cpu@101 {
+ reg = <0x0 0x201>;
+ };
+
+ CPU6:cpu@102 {
+ reg = <0x0 0x300>;
+ };
+
+ CPU7:cpu@103 {
+ reg = <0x0 0x301>;
+ };
+
+ CPU8:cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU9:cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x401>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU10:cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU11:cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x501>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU12:cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU13:cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x601>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU14:cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
-&CPU7 {
- reg = <0x0 0x301>;
+ CPU15:cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x701>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+ };
};
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index 2b1d983..19a52f7 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -10,9 +10,11 @@
/* SiP status response */
#define INTEL_SIP_SMC_STATUS_OK 0
-#define INTEL_SIP_SMC_STATUS_ERROR 0x4
#define INTEL_SIP_SMC_STATUS_BUSY 0x1
#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
+#define INTEL_SIP_SMC_STATUS_ERROR 0x4
+#define INTEL_SIP_SMC_RSU_ERROR 0x7
+
/* SMC SiP service function identifier */
#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 1c3d45b..b15fa3d 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -374,7 +374,7 @@
static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz)
{
if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
+ return INTEL_SIP_SMC_RSU_ERROR;
return INTEL_SIP_SMC_STATUS_OK;
}
@@ -388,7 +388,7 @@
static uint32_t intel_rsu_notify(uint64_t execution_stage)
{
if (mailbox_hps_stage_notify(execution_stage) < 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
+ return INTEL_SIP_SMC_RSU_ERROR;
return INTEL_SIP_SMC_STATUS_OK;
}
@@ -397,7 +397,7 @@
uint32_t *ret_stat)
{
if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0)
- return INTEL_SIP_SMC_STATUS_ERROR;
+ return INTEL_SIP_SMC_RSU_ERROR;
*ret_stat = respbuf[8];
return INTEL_SIP_SMC_STATUS_OK;