| commit | fcbcd6f36ec8f367d4a9fdce11d277d7758a2647 | [log] [tgz] |
|---|---|---|
| author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | Wed Feb 26 12:37:05 2020 -0600 |
| committer | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | Sun Mar 01 06:44:30 2020 -0600 |
| tree | 15d4515c7f5fc2d3d34fae93b9fe58a1b5453e2b | |
| parent | 65bc9b327568b5b4dd7a5142c385575d32e988b1 [diff] [blame] |
aarch32: stop speculative execution past exception returns aarch32 CPUs speculatively execute instructions following a ERET as if it was not a jump instruction. This could lead to cache-based side channel vulnerabilities. The software fix is to place barrier instructions following ERET. The counterpart patch for aarch64 is merged: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=f461fe346b728d0e88142fd7b8f2816415af18bc Change-Id: I2aa3105bee0b92238f389830b3a3b8650f33af3d Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
diff --git a/include/arch/aarch32/smccc_macros.S b/include/arch/aarch32/smccc_macros.S index 4ec2292..ea7835a 100644 --- a/include/arch/aarch32/smccc_macros.S +++ b/include/arch/aarch32/smccc_macros.S
@@ -235,7 +235,7 @@ /* Restore the rest of the general purpose registers */ ldm r0, {r0-r12} - eret + exception_return .endm #endif /* SMCCC_MACROS_S */