fix(intel): update DDR range checking for Agilex5
Update DDR range checking for Agilex when total max size of
DRAM_BASE and DRAM_SIZE overflow unsigned 64bit.
Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index c6530cf..314a7d7 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -280,6 +280,9 @@
bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
{
+ uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE;
+ uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size;
+
if (!addr && !size) {
return true;
}
@@ -289,7 +292,7 @@
if (addr < BL31_LIMIT) {
return false;
}
- if (addr + size > DRAM_BASE + DRAM_SIZE) {
+ if (dram_region_end > dram_max_sz) {
return false;
}