| commit | fc4a01729cc9af00d81f1c24ab198e0ac5900a70 | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Mon Sep 25 22:30:34 2023 +0800 |
| committer | Jit Loon Lim <jit.loon.lim@intel.com> | Fri Dec 15 11:15:10 2023 +0800 |
| tree | 4195c7705d0c00ec88b044b7c23c4ec08dc6122d | |
| parent | 1165717bcba28cb0ad85c95bbd03c96771620af1 [diff] |
fix(intel): update DDR range checking for Agilex5 Update DDR range checking for Agilex when total max size of DRAM_BASE and DRAM_SIZE overflow unsigned 64bit. Change-Id: Iaecfa5daae48da0af46cc1831d10c0e6a79613c2 Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>