feat(s32g274a): add ncore support
Ncore is a cache-coherent interconnect module. It enables the
integration of heterogenous coherent agents and non-coherent
agents in a chip. TF-A boots with the first core in isolation
to avoid crashes due to cache invalidation operations. Later,
it will disable the isolation and reconfigure the module every
time a new core is added or removed through PSCI.
Change-Id: Ida42db91b10be1e66c3b9b73674d1e37a61844dd
Signed-off-by: Dan Nica <dan.nica@nxp.com>
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/plat/nxp/s32/s32g274ardb2/plat_helpers.S b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
index 10c0035..7121900 100644
--- a/plat/nxp/s32/s32g274ardb2/plat_helpers.S
+++ b/plat/nxp/s32/s32g274ardb2/plat_helpers.S
@@ -6,10 +6,7 @@
#include <asm_macros.S>
#include <platform_def.h>
-
-#define S32G_NCORE_CAIU0_BASE_ADDR UL(0x50400000)
-#define S32G_NCORE_CAIUTC_OFF U(0x0)
-#define S32G_NCORE_CAIUTC_ISOLEN_SHIFT U(1)
+#include <s32cc-ncore.h>
.globl plat_crash_console_flush
.globl plat_crash_console_init
@@ -104,12 +101,12 @@
* Clobber list: x0, x1, x2
*/
func plat_reset_handler
- mov x0, #S32G_NCORE_CAIU0_BASE_ADDR
- ldr w1, [x0, #S32G_NCORE_CAIUTC_OFF]
+ mov x0, #NCORE_CAIU0_BASE_ADDR
+ ldr w1, [x0, #NCORE_CAIUTC_OFF]
movz w2, #1
- lsl w2, w2, #S32G_NCORE_CAIUTC_ISOLEN_SHIFT
+ lsl w2, w2, #NCORE_CAIUTC_ISOLEN_SHIFT
orr w1, w1, w2
- str w1, [x0, #S32G_NCORE_CAIUTC_OFF]
+ str w1, [x0, #NCORE_CAIUTC_OFF]
ret
endfunc plat_reset_handler