diff --git a/plat/mediatek/mt8186/aarch64/platform_common.c b/plat/mediatek/mt8186/aarch64/platform_common.c
index 9b9697f..021cab7 100644
--- a/plat/mediatek/mt8186/aarch64/platform_common.c
+++ b/plat/mediatek/mt8186/aarch64/platform_common.c
@@ -15,6 +15,8 @@
 			MT_DEVICE | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),
+	MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
+			MT_DEVICE | MT_RW | MT_SECURE),
 	{ 0 }
 };
 
diff --git a/plat/mediatek/mt8186/bl31_plat_setup.c b/plat/mediatek/mt8186/bl31_plat_setup.c
index b70245f..5fc6b6e 100644
--- a/plat/mediatek/mt8186/bl31_plat_setup.c
+++ b/plat/mediatek/mt8186/bl31_plat_setup.c
@@ -18,6 +18,7 @@
 /* Platform Includes */
 #include <emi_mpu.h>
 #include <mt_gic_v3.h>
+#include <mt_spm.h>
 #include <mt_timer.h>
 #include <mtgpio.h>
 #include <mtk_dcm.h>
@@ -94,6 +95,7 @@
 	mt_gpio_init();
 	mt_systimer_init();
 	generic_delay_timer_init();
+	spm_boot_init();
 
 	emi_mpu_init();
 }
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c
index c6c2e38..8c012e7 100644
--- a/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c
+++ b/plat/mediatek/mt8186/drivers/mcdi/mt_cpu_pm.c
@@ -12,6 +12,8 @@
 #include <lib/spinlock.h>
 
 #include <mt_cpu_pm_cpc.h>
+#include <mt_lp_irqremain.h>
+#include <mt_lp_rm.h>
 #include <mt_mcdi.h>
 #include <plat_mtk_lpm.h>
 #include <plat_pm.h>
@@ -73,15 +75,22 @@
 static int pwr_mcusys_pwron_finished(unsigned int cpu,
 					const psci_power_state_t *state)
 {
+	int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
 	if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
 		return -1;
 	}
 
+	mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
+	mt_lp_irqremain_release();
+
 	return 0;
 }
 
 static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
 {
+	int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
 	if (!IS_MCUSYS_OFF_STATE(state)) {
 		goto mt_pwr_mcusysoff_break;
 	}
@@ -90,10 +99,25 @@
 		goto mt_pwr_mcusysoff_break;
 	}
 
+	if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
+		goto mt_pwr_mcusysoff_break;
+	}
+
+	plat_mt_lp_cpu_rc =
+		mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
+
+	if (plat_mt_lp_cpu_rc < 0) {
+		goto mt_pwr_mcusysoff_reflect;
+	}
+
+	mt_lp_irqremain_aquire();
+
 	return 0;
 
-mt_pwr_mcusysoff_break:
+mt_pwr_mcusysoff_reflect:
+	mtk_cpc_mcusys_off_reflect();
 
+mt_pwr_mcusysoff_break:
 	plat_mt_lp_cpu_rc = -1;
 
 	return -1;
@@ -119,5 +143,7 @@
 		INFO("MCDI init done.\n");
 	}
 
+	mt_lp_irqremain_init();
+
 	return &plat_pm;
 }
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c
new file mode 100644
index 0000000..42b2808
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mt_lp_irqremain.h>
+#include <mt_lp_rm.h>
+#include <mtk_cirq.h>
+#include <plat_mtk_lpm.h>
+
+#define KEYPAD_IRQ_ID		U(138)
+#define KEYPAD_WAKESRC		(0x4U)
+
+static struct mt_irqremain remain_irqs;
+
+int mt_lp_irqremain_submit(void)
+{
+	int ret = 0;
+
+	if (remain_irqs.count == 0) {
+		ret = -1;
+	} else {
+		set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
+		mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
+	}
+
+	return ret;
+}
+
+int mt_lp_irqremain_aquire(void)
+{
+	int ret = 0;
+
+	if (remain_irqs.count == 0) {
+		ret = -1;
+	} else {
+		mt_cirq_sw_reset();
+		mt_cirq_clone_gic();
+		mt_cirq_enable();
+	}
+
+	return ret;
+}
+
+int mt_lp_irqremain_release(void)
+{
+	int ret = 0;
+
+	if (remain_irqs.count == 0) {
+		ret = -1;
+	} else {
+		mt_cirq_flush();
+		mt_cirq_disable();
+	}
+
+	return ret;
+}
+
+void mt_lp_irqremain_init(void)
+{
+	uint32_t idx;
+
+	remain_irqs.count = 0U;
+
+	/*edge keypad*/
+	idx = remain_irqs.count;
+	remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
+	remain_irqs.wakeupsrc_cat[idx] = 0U;
+	remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
+	remain_irqs.count++;
+
+	mt_lp_irqremain_submit();
+}
diff --git a/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.h b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.h
new file mode 100644
index 0000000..c313438
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/mcdi/mt_lp_irqremain.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_IRQREMAIN_H
+#define MT_LP_IRQREMAIN_H
+
+extern int mt_lp_irqremain_submit(void);
+extern int mt_lp_irqremain_aquire(void);
+extern int mt_lp_irqremain_release(void);
+extern void mt_lp_irqremain_init(void);
+
+#endif /* MT_LP_IRQREMAIN_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/build.mk b/plat/mediatek/mt8186/drivers/spm/build.mk
new file mode 100644
index 0000000..f288691
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/build.mk
@@ -0,0 +1,77 @@
+#
+# Copyright (c) 2022, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Enable or disable spm feature
+MT_SPM_FEATURE_SUPPORT=yes
+
+# Enable or disable cirq restore
+MT_SPM_CIRQ_FEATURE_SUPPORT=yes
+
+# sspm notifier support
+MT_SPM_SSPM_NOTIFIER_SUPPORT=yes
+
+CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm
+
+# spm common files
+PLAT_SPM_SOURCE_FILES_COMMON +=				\
+	${CUR_SPM_FOLDER}/mt_spm.c			\
+	${CUR_SPM_FOLDER}/mt_spm_internal.c		\
+	${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c		\
+	${CUR_SPM_FOLDER}/mt_spm_conservation.c		\
+	${CUR_SPM_FOLDER}/mt_spm_extern.c
+
+# spm platform dependcy files
+PLAT_SPM_SOURCE_FILES +=					\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c	\
+	${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c		\
+	${CUR_SPM_FOLDER}/mt_spm_cond.c				\
+	${CUR_SPM_FOLDER}/mt_spm_suspend.c			\
+	${CUR_SPM_FOLDER}/mt_spm_idle.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
+
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON}
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES +=	\
+	${PLAT_SPM_SOURCE_FILES_COMMON} \
+	${PLAT_SPM_SOURCE_FILES}
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c
+endif
+
+ifeq (${MTK_VOLTAGE_BIN_VCORE}, yes)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_VOLTAGE_BIN_VCORE_SUPPORT
+endif
+
+ifeq ($(MTK_SPM_EXTENSION_CONFIG), pmic6362)
+MTK_SPM_EXTENSION_PMIC_CONTROL := 6362
+$(eval $(call add_define,MTK_SPM_EXTENSION_PMIC_CONTROL))
+endif
+
+$(info --------------------------------------)
+$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS})
+$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES})
+$(info --------------------------------------)
+
+# Common makefile for platform.mk
+PLAT_INCLUDES +=				\
+	${PLAT_SPM_DEBUG_CFLAGS}		\
+	-I${CUR_SPM_FOLDER}/			\
+	-I${CUR_SPM_FOLDER}/constraints/	\
+	-I${CUR_SPM_FOLDER}/notifier/
+
+PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..66fbe91
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_gic_v3.h>
+#endif
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mtk_cirq.h>
+#endif
+
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_BUS26M_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP |	\
+	 MT_RM_CONSTRAINT_ALLOW_LVTS_STATE |	\
+	 MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_ENABLE_TIA_WORKAROUND |	\
+	 SPM_FLAG_ENABLE_LVTS_WORKAROUND |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1	(0U)
+#define CONSTRAINT_BUS26M_RESOURCE_REQ	(0U)
+
+static unsigned int bus26m_ext_opand;
+static struct mt_irqremain *refer2remain_irq;
+static struct mt_spm_cond_tables cond_bus26m = {
+	.name = "bus26m",
+	.table_cg = {
+		0x0385E03C, /* MTCMOS1 */
+		0x003F0100, /* INFRA0  */
+		0x0A040802, /* INFRA1  */
+		0x06017E51, /* INFRA2  */
+		0x08000000, /* INFRA3  */
+		0x00000000, /* INFRA4  */
+		0x00000000, /* INFRA5  */
+		0x03720820, /* MMSYS0  */
+		0x00000000, /* MMSYS1  */
+		0x00000000, /* MMSYS2  */
+		0x00015151, /* MMSYS3  */
+	},
+	.table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
+		      PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL |
+		      PLL_BIT_MMPLL),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+	.table_cg = {0U},
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_BUS26M,
+	.valid = (MT_SPM_RC_VALID_SW | MT_SPM_RC_VALID_COND_LATCH),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_bus26m_res,
+};
+
+/*
+ * Cirq will take the place of gic when gic is off.
+ * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
+ * Therefore, we need to set irq pending for specific wakeup source.
+ */
+#ifdef ATF_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+				   unsigned int irq_index,
+				   struct wake_status *wakeup)
+{
+	INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
+	     wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
+	     wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
+	     wakeup->tr.comm.b_sw_flag1);
+
+	INFO("irq:%u(0x%08x) set pending\n",
+	     irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+	unsigned int idx;
+	int res = 0;
+	struct wake_status *wakeup = NULL;
+	struct mt_irqremain *irqs = refer2remain_irq;
+
+	res = spm_conservation_get_result(&wakeup);
+
+	if ((res != 0) && (irqs == NULL)) {
+		return;
+	}
+
+	for (idx = 0; idx < irqs->count; ++idx) {
+		if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+		    ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+			if ((irqs->wakeupsrc_cat[idx] & MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+				mt_spm_irq_remain_dump(irqs, idx, wakeup);
+			}
+
+			mt_irq_set_pending(irqs->irqs[idx]);
+		}
+	}
+}
+#endif
+
+static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp, unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		res = MT_RM_STATUS_BAD;
+	} else {
+		if (type == PLAT_RC_UPDATE_CONDITION) {
+			tlb = (const struct mt_spm_cond_tables *)val;
+			tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+			status.cond_block =
+				mt_spm_cond_check(state_id, tlb, tlb_check,
+						  ((status.valid &
+						   MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+						  (&cond_bus26m_res) : (NULL));
+		} else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
+			refer2remain_irq = (struct mt_irqremain *)val;
+		} else {
+			res = MT_RM_STATUS_BAD;
+		}
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+
+#ifdef ATF_VOLTAGE_BIN_VCORE_SUPPORT
+#define SUSPEND_VB_MAGIC    (0x5642)
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE,
+				       ((SUSPEND_VB_MAGIC << 16) |
+					spm_get_suspend_vcore_voltage_idx()));
+	}
+#endif
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+			       (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_CLR_26M_RECORD |
+				      MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      bus26m_ext_opand),
+				     CONSTRAINT_BUS26M_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_bus26m_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+	(void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
+		mt_spm_suspend_resume(state_id, ext_op, NULL);
+		bus26m_ext_opand = 0U;
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+		status.enter_cnt++;
+	}
+
+	do_irqs_delivery();
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..c47cf1f
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG	\
+	(SPM_FLAG_DISABLE_INFRA_PDN |	\
+	 SPM_FLAG_DISABLE_VCORE_DVS |	\
+	 SPM_FLAG_DISABLE_VCORE_DFS |	\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1	(0U)
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ	\
+	(MT_SPM_DRAM_S1 |			\
+	 MT_SPM_DRAM_S0 |			\
+	 MT_SPM_SYSPLL |			\
+	 MT_SPM_INFRA |				\
+	 MT_SPM_26M |				\
+	 MT_SPM_XO_FPM)
+
+static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
+static unsigned int cpubuckldo_enter_cnt;
+
+static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
+				unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+	(void)state_id;
+
+	return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	unsigned int ext_op = 0U;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+			       (IS_PLAT_SUSPEND_ID(state_id) ?
+				(MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     MT_SPM_EX_OP_SET_WDT,
+				     CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op,
+					  spm_cpu_bcuk_ldo_conduct);
+	}
+
+	cpubuckldo_enter_cnt++;
+
+	return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	unsigned int ext_op = 0U;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_dram.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..b281734
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_DRAM_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_DRAM_S0	|	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG	\
+	(SPM_FLAG_DISABLE_INFRA_PDN |	\
+	 SPM_FLAG_DISABLE_VCORE_DVS |	\
+	 SPM_FLAG_DISABLE_VCORE_DFS |	\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |	\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1	(0U)
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ	\
+	(MT_SPM_SYSPLL |		\
+	 MT_SPM_INFRA |			\
+	 MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+	.name = "dram",
+	.table_cg = {
+		0x0385E03C, /* MTCMOS1 */
+		0x003F0100, /* INFRA0  */
+		0x08040802, /* INFRA1  */
+		0x06015641, /* INFRA2  */
+		0x00000000, /* INFRA3  */
+		0x00000000, /* INFRA4  */
+		0x00000000, /* INFRA5  */
+		0x02300020, /* MMSYS0  */
+		0x00000000, /* MMSYS1  */
+		0x00000000, /* MMSYS2  */
+		0x00015111, /* MMSYS3  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+	.table_cg = {0U},
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_DRAM,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_dram_res,
+};
+
+static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
+			     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+	*resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		res = MT_RM_STATUS_BAD;
+	} else {
+		if (type == PLAT_RC_UPDATE_CONDITION) {
+			tlb = (const struct mt_spm_cond_tables *)val;
+			tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+			status.cond_block =
+				mt_spm_cond_check(state_id, tlb, tlb_check,
+						  ((status.valid &
+						   MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+						   (&cond_dram_res) : (NULL));
+		} else {
+			res = MT_RM_STATUS_BAD;
+		}
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+			       (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+	(void)allows;
+#endif
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+				     CONSTRAINT_DRAM_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_WDT | MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_internal.h b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..dfacba9
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#include <stdbool.h>
+
+#define SPM_SRAM_SLEEP_DEFAULT_FLAG (SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define SPM_FLAG_SRAM_SLEEP_CTRL			\
+	(SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |	\
+	 SPM_FLAG_DISABLE_SYSRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP |		\
+	 SPM_FLAG_DISABLE_SRAM_EVENT)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+
+#endif /* MT_SPM_RC_INTERNAL_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_syspll.c b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..4977de1
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW			\
+	(MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S0 |	\
+	 MT_RM_CONSTRAINT_ALLOW_DRAM_S1 |	\
+	 MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#if (MTK_SPM_EXTENSION_PMIC_CONTROL == 6362)
+#define SPM_FLAG_EXTRA_PMIC_CONTROL (SPM_FLAG_ENABLE_6362_CTRL)
+#else
+#define SPM_FLAG_EXTRA_PMIC_CONTROL (SPM_FLAG_ENABLE_6315_CTRL)
+#endif
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_USE_SRCCLKENO2 |		\
+	 SPM_FLAG_SRAM_SLEEP_CTRL |		\
+	 SPM_FLAG_KEEP_CSYSPWRACK_HIGH |	\
+	 SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1	(0U)
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ	(MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_syspll = {
+	.name = "syspll",
+	.table_cg = {
+		0x0385E03C, /* MTCMOS1 */
+		0x003F0100, /* INFRA0  */
+		0x08040802, /* INFRA1  */
+		0x06015641, /* INFRA2  */
+		0x00000000, /* INFRA3  */
+		0x00000000, /* INFRA4  */
+		0x00000000, /* INFRA5  */
+		0x03720820, /* MMSYS0  */
+		0x00000000, /* MMSYS1  */
+		0x00000000, /* MMSYS2  */
+		0x00015151, /* MMSYS3  */
+	},
+	.table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+	.table_cg = {0U},
+	.table_pll = 0U,
+};
+
+static struct constraint_status status = {
+	.id = MT_RM_CONSTRAINT_ID_SYSPLL,
+	.valid = (MT_SPM_RC_VALID_SW |
+		  MT_SPM_RC_VALID_COND_LATCH |
+		  MT_SPM_RC_VALID_XSOC_BBLPM),
+	.cond_block = 0U,
+	.enter_cnt = 0U,
+	.cond_res = &cond_syspll_res,
+};
+
+static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
+			     unsigned int *resource_req)
+{
+	spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+	spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+
+	*resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+	(void)cpu;
+	(void)state_id;
+
+	return ((status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid));
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+	const struct mt_spm_cond_tables *tlb;
+	const struct mt_spm_cond_tables *tlb_check;
+	int res = MT_RM_STATUS_OK;
+
+	if (val == NULL) {
+		res = MT_RM_STATUS_BAD;
+	} else {
+		if (type == PLAT_RC_UPDATE_CONDITION) {
+			tlb = (const struct mt_spm_cond_tables *)val;
+			tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
+
+			status.cond_block =
+				mt_spm_cond_check(state_id, tlb, tlb_check,
+						  ((status.valid &
+						   MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+						   (&cond_syspll_res) : (NULL));
+		} else {
+			res = MT_RM_STATUS_BAD;
+		}
+	}
+
+	return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+	(void)state_id;
+
+	return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows | (IS_PLAT_SUSPEND_ID(state_id) ?
+			       (MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND) : (0U)));
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_enter(state_id,
+				     (MT_SPM_EX_OP_SET_WDT |
+				      MT_SPM_EX_OP_HW_S1_DETECT |
+				      MT_SPM_EX_OP_SET_SUSPEND_MODE),
+				     CONSTRAINT_SYSPLL_RESOURCE_REQ);
+	} else {
+		mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+	}
+
+	return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+	unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+	unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+	(void)cpu;
+
+	if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+		ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+		allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+	}
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+	mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+	(void)allows;
+#endif
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		mt_spm_suspend_resume(state_id,
+				      (MT_SPM_EX_OP_SET_SUSPEND_MODE |
+				       MT_SPM_EX_OP_SET_WDT |
+				       MT_SPM_EX_OP_HW_S1_DETECT),
+				      NULL);
+	} else {
+		mt_spm_idle_generic_resume(state_id, ext_op, NULL, NULL);
+		status.enter_cnt++;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm.c b/plat/mediatek/mt8186/drivers/spm/mt_spm.c
new file mode 100644
index 0000000..8ad50e2
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include "mt_spm_extern.h"
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <mtk_plat_common.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <sleep_def.h>
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DEFINE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
+#else
+spinlock_t spm_lock;
+#define plat_spm_lock_init()
+#endif
+
+/* CLK_SCP_CFG_0 */
+#define CLK_SCP_CFG_0		(TOPCKGEN_BASE + 0x200)
+#define SPM_CK_CONTROL_EN	(0x3FF)
+
+/* CLK_SCP_CFG_1 */
+#define CLK_SCP_CFG_1		(TOPCKGEN_BASE + 0x210)
+#define CLK_SCP_CFG_1_MASK	(0x100C)
+#define CLK_SCP_CFG_1_SPM	(0x3)
+
+#define MT_SPM_EX_OP_TIME_CHECK	BIT(10)
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+	.is_valid = spm_is_valid_rc_bus26m,
+	.update = spm_update_rc_bus26m,
+	.allow = spm_allow_rc_bus26m,
+	.run = spm_run_rc_bus26m,
+	.reset = spm_reset_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+	.is_valid = spm_is_valid_rc_syspll,
+	.update = spm_update_rc_syspll,
+	.allow = spm_allow_rc_syspll,
+	.run = spm_run_rc_syspll,
+	.reset = spm_reset_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+	.is_valid = spm_is_valid_rc_dram,
+	.update = spm_update_rc_dram,
+	.allow = spm_allow_rc_dram,
+	.run = spm_run_rc_dram,
+	.reset = spm_reset_rc_dram,
+};
+
+/* Maybe remove when the spm won't cpu power control aymore */
+struct mt_resource_constraint plat_constraint_cpu = {
+	.is_valid = spm_is_valid_rc_cpu_buck_ldo,
+	.update = NULL,
+	.allow = spm_allow_rc_cpu_buck_ldo,
+	.run = spm_run_rc_cpu_buck_ldo,
+	.reset = spm_reset_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+	&plat_constraint_bus26m,
+	&plat_constraint_syspll,
+	&plat_constraint_dram,
+	&plat_constraint_cpu,
+	NULL,
+};
+
+struct mt_resource_manager plat_mt8186_rm = {
+	.update = mt_spm_cond_update,
+	.consts = plat_constraints,
+};
+
+void spm_boot_init(void)
+{
+	NOTICE("MT8186 %s\n", __func__);
+
+	/* switch ck_off/axi_26m control to SPM */
+	mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
+	mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK, CLK_SCP_CFG_1_SPM);
+
+	plat_spm_lock_init();
+	mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+	mt_lp_rm_register(&plat_mt8186_rm);
+	mt_spm_idle_generic_init();
+	mt_spm_suspend_init();
+	spm_extern_initialize();
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm.h b/plat/mediatek/mt8186/drivers/spm/mt_spm.h
new file mode 100644
index 0000000..0e21b5e
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <lib/bakery_lock.h>
+#include <lib/spinlock.h>
+#include <plat_mtk_lpm.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. Therefore, there is no doubt to use the spin_lock here.
+ */
+#if !HW_ASSISTED_COHERENCY
+#define MT_SPM_USING_BAKERY_LOCK
+#endif
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DECLARE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock() bakery_lock_get(&spm_lock)
+#define plat_spm_unlock() bakery_lock_release(&spm_lock)
+#else
+extern spinlock_t spm_lock;
+#define plat_spm_lock() spin_lock(&spm_lock)
+#define plat_spm_unlock() spin_unlock(&spm_lock)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD		BIT(0)
+#define MT_SPM_EX_OP_SET_WDT			BIT(1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ	BIT(2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE		BIT(3)
+#define MT_SPM_EX_OP_SET_IS_ADSP		BIT(4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM		BIT(5)
+#define MT_SPM_EX_OP_HW_S1_DETECT		BIT(6)
+#define MT_SPM_EX_OP_TRACE_LP			BIT(7)
+#define MT_SPM_EX_OP_TRACE_SUSPEND		BIT(8)
+#define MT_SPM_EX_OP_TRACE_TIMESTAMP_EN		BIT(9)
+#define MT_SPM_EX_OP_TIME_CHECK			BIT(10)
+#define MT_SPM_EX_OP_TIME_OBS			BIT(11)
+
+typedef enum {
+	WR_NONE = 0,
+	WR_UART_BUSY = 1,
+	WR_ABORT = 2,
+	WR_PCM_TIMER = 3,
+	WR_WAKE_SRC = 4,
+	WR_DVFSRC = 5,
+	WR_TWAM = 6,
+	WR_PMSR = 7,
+	WR_SPM_ACK_CHK = 8,
+	WR_UNKNOWN = 9,
+} wake_reason_t;
+
+/* for suspend vol. bin settings */
+enum MT_PLAT_SUSPEND_VCORE {
+	SPM_SUSPEND_VCORE_5500 = 0,
+	SPM_SUSPEND_VCORE_5250 = 1,
+	SPM_SUSPEND_VCORE_5000 = 2,
+};
+
+extern void spm_boot_init(void);
+
+static inline void spm_lock_get(void)
+{
+	plat_spm_lock();
+}
+
+static inline void spm_lock_release(void)
+{
+	plat_spm_unlock();
+}
+
+unsigned int spm_get_suspend_vcore_voltage_idx(void);
+
+#endif /* MT_SPM_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
new file mode 100644
index 0000000..a420e16
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#define MT_LP_TZ_INFRA_REG(ofs)		(INFRACFG_AO_BASE + ofs)
+#define MT_LP_TZ_MM_REG(ofs)		(MMSYS_BASE + ofs)
+#define MT_LP_TZ_MDP_REG(ofs)		(MDPSYS_BASE + ofs)
+#define MT_LP_TZ_SPM_REG(ofs)		(SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs)		(TOPCKGEN_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs)	(APMIXEDSYS + ofs)
+
+#define SPM_PWR_STATUS			MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND		MT_LP_TZ_SPM_REG(0x0170)
+#define	INFRA_SW_CG0			MT_LP_TZ_INFRA_REG(0x0090)
+#define	INFRA_SW_CG1			MT_LP_TZ_INFRA_REG(0x0094)
+#define	INFRA_SW_CG2			MT_LP_TZ_INFRA_REG(0x00AC)
+#define	INFRA_SW_CG3			MT_LP_TZ_INFRA_REG(0x00C8)
+#define INFRA_SW_CG4                    MT_LP_TZ_INFRA_REG(0x00E8)
+#define INFRA_SW_CG5                    MT_LP_TZ_INFRA_REG(0x00D8)
+#define MMSYS_CG_CON0			MT_LP_TZ_MM_REG(0x100)
+#define MMSYS_CG_CON1			MT_LP_TZ_MM_REG(0x110)
+#define MMSYS_CG_CON2                   MT_LP_TZ_MM_REG(0x1A0)
+#define MMSYS_CG_CON3			MT_LP_TZ_MDP_REG(0x100)
+
+/* Check clkmux registers */
+#define CLK_CFG(id)    MT_LP_TZ_TOPCK_REG(0xe0 + id * 0x10)
+#define CLK_CHECK      BIT(31)
+
+enum {
+	CLKMUX_DISP  = 0,
+	CLKMUX_MDP   = 1,
+	CLKMUX_IMG1  = 2,
+	CLKMUX_IMG2  = 3,
+	NF_CLKMUX    = 4,
+};
+
+static bool is_clkmux_pdn(unsigned int clkmux_id)
+{
+	unsigned int reg, val, idx;
+	bool ret = false;
+
+	if (clkmux_id & CLK_CHECK) {
+		clkmux_id = (clkmux_id & ~CLK_CHECK);
+		reg = clkmux_id / 4U;
+		val = mmio_read_32(CLK_CFG(reg));
+		idx = clkmux_id % 4U;
+		ret = (((val >> (idx * 8U)) & 0x80) != 0U);
+	}
+
+	return ret;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+struct idle_cond_info {
+	unsigned int subsys_mask;
+	uintptr_t addr;
+	bool bit_flip;
+	unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux)	\
+	{mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+	IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U),
+	IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U),
+	IDLE_CG(0x00200000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)),
+	IDLE_CG(0x00200000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)),
+	IDLE_CG(0x00200000, MMSYS_CG_CON2, true, (CLK_CHECK | CLKMUX_DISP)),
+	IDLE_CG(0x00200000, MMSYS_CG_CON3, true, (CLK_CHECK | CLKMUX_MDP)),
+};
+
+/* Check pll idle condition */
+#define PLL_MFGPLL	MT_LP_TZ_APMIXEDSYS(0x314)
+#define PLL_MMPLL	MT_LP_TZ_APMIXEDSYS(0x254)
+#define PLL_UNIVPLL	MT_LP_TZ_APMIXEDSYS(0x324)
+#define PLL_MSDCPLL	MT_LP_TZ_APMIXEDSYS(0x38c)
+#define PLL_TVDPLL	MT_LP_TZ_APMIXEDSYS(0x264)
+
+unsigned int mt_spm_cond_check(int state_id,
+			       const struct mt_spm_cond_tables *src,
+			       const struct mt_spm_cond_tables *dest,
+			       struct mt_spm_cond_tables *res)
+{
+	unsigned int blocked = 0U;
+	unsigned int i;
+	bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
+
+	if ((src == NULL) || (dest == NULL)) {
+		blocked = SPM_COND_CHECK_FAIL;
+	} else {
+		for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+			if (res != NULL) {
+				res->table_cg[i] = (src->table_cg[i] & dest->table_cg[i]);
+				if (is_system_suspend && ((res->table_cg[i]) != 0U)) {
+					INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
+					     dest->name, i, idle_cg_info[i].addr,
+					     res->table_cg[i]);
+				}
+
+				if ((res->table_cg[i]) != 0U) {
+					blocked |= BIT(i);
+				}
+			} else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+				blocked |= BIT(i);
+				break;
+			}
+		}
+
+		if (res != NULL) {
+			res->table_pll = (src->table_pll & dest->table_pll);
+
+			if (res->table_pll != 0U) {
+				blocked |= (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+					    SPM_COND_CHECK_BLOCKED_PLL;
+			}
+		} else if ((src->table_pll & dest->table_pll) != 0U) {
+			blocked |= SPM_COND_CHECK_BLOCKED_PLL;
+		}
+
+		if (is_system_suspend && ((blocked) != 0U)) {
+			INFO("suspend: %s total blocked = 0x%08x\n", dest->name, blocked);
+		}
+	}
+
+	return blocked;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask)					\
+	(((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) &&	\
+	 ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con, int stateid, void *priv)
+{
+	int res;
+	uint32_t i;
+	struct mt_resource_constraint *const *rc;
+
+	/* read all cg state */
+	for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+		spm_cond_t.table_cg[i] = 0U;
+
+		/* check mtcmos, if off set idle_value and clk to 0 disable */
+		if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+			continue;
+		}
+
+		/* check clkmux */
+		if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+			continue;
+		}
+
+		spm_cond_t.table_cg[i] = idle_cg_info[i].bit_flip ?
+					 ~mmio_read_32(idle_cg_info[i].addr) :
+					 mmio_read_32(idle_cg_info[i].addr);
+	}
+
+	spm_cond_t.table_pll = 0U;
+	if ((mmio_read_32(PLL_MFGPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
+	}
+
+	if ((mmio_read_32(PLL_MMPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MMPLL;
+	}
+
+	if ((mmio_read_32(PLL_UNIVPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
+	}
+
+	if ((mmio_read_32(PLL_MSDCPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
+	}
+
+	if ((mmio_read_32(PLL_TVDPLL) & 0x1) != 0U) {
+		spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
+	}
+
+	spm_cond_t.priv = priv;
+
+	for (rc = con; *rc != NULL; rc++) {
+		if (((*rc)->update) == NULL) {
+			continue;
+		}
+
+		res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+				    (void const *)&spm_cond_t);
+		if (res != MT_RM_STATUS_OK) {
+			break;
+		}
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
new file mode 100644
index 0000000..24c39ba
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_cond.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONDIT_H
+#define MT_SPM_CONDIT_H
+
+#include <mt_lp_rm.h>
+
+enum PLAT_SPM_COND {
+	PLAT_SPM_COND_MTCMOS1    = 0,
+	PLAT_SPM_COND_CG_INFRA_0 = 1,
+	PLAT_SPM_COND_CG_INFRA_1 = 2,
+	PLAT_SPM_COND_CG_INFRA_2 = 3,
+	PLAT_SPM_COND_CG_INFRA_3 = 4,
+	PLAT_SPM_COND_CG_INFRA_4 = 5,
+	PLAT_SPM_COND_CG_INFRA_5 = 6,
+	PLAT_SPM_COND_CG_MMSYS_0 = 7,
+	PLAT_SPM_COND_CG_MMSYS_1 = 8,
+	PLAT_SPM_COND_CG_MMSYS_2 = 9,
+	PLAT_SPM_COND_CG_MMSYS_3 = 10,
+	PLAT_SPM_COND_MAX        = 11,
+};
+
+#define PLL_BIT_UNIVPLL	BIT(0)
+#define PLL_BIT_MFGPLL	BIT(1)
+#define PLL_BIT_MSDCPLL	BIT(2)
+#define PLL_BIT_TVDPLL	BIT(3)
+#define PLL_BIT_MMPLL	BIT(4)
+
+/*
+ * Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30]     : pll blocking information
+ * bit [31]	: idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX		U(0)
+#define SPM_COND_BLOCKED_PLL_IDX	U(16)
+#define SPM_COND_CHECK_BLOCKED_PLL	BIT(30)
+#define SPM_COND_CHECK_FAIL		BIT(31)
+
+struct mt_spm_cond_tables {
+	char *name;
+	unsigned int table_cg[PLAT_SPM_COND_MAX];
+	unsigned int table_pll;
+	void *priv;
+};
+
+extern unsigned int mt_spm_cond_check(int state_id,
+				      const struct mt_spm_cond_tables *src,
+				      const struct mt_spm_cond_tables *dest,
+				      struct mt_spm_cond_tables *res);
+
+extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+			      int stateid, void *priv);
+
+#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c
new file mode 100644
index 0000000..0f8dfe8
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#define MT_RESUMETIME_THRESHOLD_MAX	(5U) /*ms*/
+#define IS_RESUME_OVERTIME(delta)	(delta > MT_RESUMETIME_THRESHOLD_MAX)
+
+static struct wake_status spm_wakesta; /* record last wakesta */
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				unsigned int resource_req)
+{
+	int ret = 0;
+	struct pwr_ctrl *pwrctrl;
+	uint32_t cpu = plat_my_core_pos();
+
+	pwrctrl = spm_lp->pwrctrl;
+
+	__spm_set_cpu_status(cpu);
+	__spm_set_power_control(pwrctrl);
+	__spm_set_wakeup_event(pwrctrl);
+
+	__spm_set_pcm_flags(pwrctrl);
+
+	__spm_src_req_update(pwrctrl, resource_req);
+
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(1);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+		__spm_xo_soc_bblpm(1);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_resume();
+	}
+
+	/* Disable auto resume by PCM in system suspend stage */
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		__spm_disable_pcm_timer();
+		__spm_set_pcm_wdt(0);
+	}
+
+	__spm_send_cpu_wakeup_event();
+
+	INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
+	     cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
+	     (mmio_read_32(PCM_TIMER_VAL) / 32768));
+	INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
+	     pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
+	     mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
+	     mmio_read_32(PWR_STATUS_2ND));
+
+	return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+				struct spm_lp_scen *spm_lp,
+				struct wake_status **status)
+{
+	unsigned int ext_status = 0U;
+
+	spm_wakesta.tr.comm.resumetime = 0;
+	spm_wakesta.tr.comm.times_h = spm_wakesta.tr.comm.times_l = 0;
+
+	/* system watchdog will be resumed at kernel stage */
+	if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+		__spm_set_pcm_wdt(0);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+		__spm_xo_soc_bblpm(0);
+	}
+
+	if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+		spm_hw_s1_state_monitor_pause(&ext_status);
+	}
+
+	__spm_ext_int_wakeup_req_clr();
+
+	__spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+	if (status != NULL) {
+		*status = &spm_wakesta;
+	}
+
+	__spm_clean_after_wakeup();
+
+	if (IS_PLAT_SUSPEND_ID(state_id)) {
+		__spm_output_wake_reason(state_id, &spm_wakesta);
+	}
+
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+		     struct spm_lp_scen *spm_lp, unsigned int resource_req)
+{
+	int ret = 0;
+
+	if (spm_lp == NULL) {
+		ret = -1;
+	} else {
+		spm_lock_get();
+		go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req);
+		spm_lock_release();
+	}
+
+	return ret;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+			     struct spm_lp_scen *spm_lp,
+			     struct wake_status **status)
+{
+	spm_lock_get();
+	go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+	spm_lock_release();
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+	int ret = 0;
+
+	if (res == NULL) {
+		ret = -1;
+	} else {
+		*res = &spm_wakesta;
+	}
+	return ret;
+}
+
+#define GPIO_BANK	(GPIO_BASE + 0x6F0)
+#define TRAP_UFS_FIRST	BIT(11) /* bit 11, 0: UFS, 1: eMMC */
+
+void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl)
+{
+	if (pwrctrl != NULL) {
+		/* For ufs, emmc storage type */
+		if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) {
+			/* If eMMC is used, mask UFS req */
+			pwrctrl->reg_ufs_srcclkena_mask_b = 0;
+			pwrctrl->reg_ufs_infra_req_mask_b = 0;
+			pwrctrl->reg_ufs_apsrc_req_mask_b = 0;
+			pwrctrl->reg_ufs_vrf18_req_mask_b = 0;
+			pwrctrl->reg_ufs_ddren_req_mask_b = 0;
+		}
+	}
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.h
new file mode 100644
index 0000000..e7ef346
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_conservation.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include <mt_spm_internal.h>
+
+extern int spm_conservation(int state_id, unsigned int ext_opand,
+			    struct spm_lp_scen *spm_lp,
+			    unsigned int resource_req);
+extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
+				    struct spm_lp_scen *spm_lp,
+				    struct wake_status **status);
+extern int spm_conservation_get_result(struct wake_status **res);
+extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
+
+#endif /* MT_SPM_CONSERVATION_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_constraint.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_constraint.h
new file mode 100644
index 0000000..53be3b6
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_constraint.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF	BIT(0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0		BIT(1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1		BIT(2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP		BIT(3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN	BIT(4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF	BIT(5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND	BIT(6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM		BIT(7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS		BIT(8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE	BIT(9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE	BIT(10)
+
+#define MT_SPM_RC_INVALID		(0x0)
+#define MT_SPM_RC_VALID_SW		BIT(0)
+#define MT_SPM_RC_VALID_FW		BIT(1)
+#define MT_SPM_RC_VALID_RESIDNECY	BIT(2)
+#define MT_SPM_RC_VALID_COND_CHECK	BIT(3)
+#define MT_SPM_RC_VALID_COND_LATCH	BIT(4)
+#define MT_SPM_RC_VALID_UFS_H8		BIT(5)
+#define MT_SPM_RC_VALID_FLIGHTMODE	BIT(6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM	BIT(7)
+#define MT_SPM_RC_VALID_TRACE_EVENT	BIT(8)
+
+#define MT_SPM_RC_VALID	(MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status)	\
+	((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+#define MT_SPM_RC_BBLPM_MODE		\
+	(MT_SPM_RC_VALID_UFS_H8 |	\
+	 MT_SPM_RC_VALID_FLIGHTMODE |	\
+	 MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st)	\
+	((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+struct constraint_status {
+	uint16_t id;
+	uint16_t valid;
+	uint32_t cond_block;
+	uint32_t enter_cnt;
+	struct mt_spm_cond_tables *cond_res;
+};
+
+enum MT_SPM_RM_RC_TYPE {
+	MT_RM_CONSTRAINT_ID_BUS26M		= 0U,
+	MT_RM_CONSTRAINT_ID_SYSPLL		= 1U,
+	MT_RM_CONSTRAINT_ID_DRAM		= 2U,
+	MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO	= 3U,
+	MT_RM_CONSTRAINT_ID_ALL			= 4U,
+};
+
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.c
new file mode 100644
index 0000000..608d9f9
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) since 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define INFRA_AO_RES_CTRL_MASK			(INFRACFG_AO_BASE + 0xB8)
+#define INFRA_AO_RES_CTRL_MASK_EMI_IDLE		BIT(18)
+#define INFRA_AO_RES_CTRL_MASK_MPU_IDLE		BIT(15)
+
+void spm_extern_initialize(void)
+{
+	unsigned int val;
+
+	val = mmio_read_32(INFRA_AO_RES_CTRL_MASK);
+
+	val |= (INFRA_AO_RES_CTRL_MASK_EMI_IDLE | INFRA_AO_RES_CTRL_MASK_MPU_IDLE);
+	mmio_write_32(INFRA_AO_RES_CTRL_MASK, val);
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.h
new file mode 100644
index 0000000..5bcbaff
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_extern.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) since 2022, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_EXTERN_H
+#define MT_SPM_EXTERN_H
+
+void spm_extern_initialize(void);
+
+#endif
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.c
new file mode 100644
index 0000000..04776c8
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_pm.h>
+
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__	\
+	(R12_PCM_TIMER |		\
+	 R12_KP_IRQ_B |			\
+	 R12_APWDT_EVENT_B |		\
+	 R12_APXGPT1_EVENT_B |		\
+	 R12_CONN2AP_SPM_WAKEUP_B |	\
+	 R12_EINT_EVENT_B |		\
+	 R12_CONN_WDT_IRQ_B |		\
+	 R12_SSPM2SPM_WAKEUP_B |	\
+	 R12_SCP2SPM_WAKEUP_B |		\
+	 R12_ADSP2SPM_WAKEUP_B |	\
+	 R12_USBX_CDSC_B |		\
+	 R12_USBX_POWERDWN_B |		\
+	 R12_SYS_TIMER_EVENT_B |	\
+	 R12_EINT_EVENT_SECURE_B |	\
+	 R12_AFE_IRQ_MCU_B |		\
+	 R12_SYS_CIRQ_IRQ_B |		\
+	 R12_NNA_WAKEUP |		\
+	 R12_SEJ_EVENT_B |		\
+	 R12_REG_CPU_WAKEUP)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND			\
+	(__WAKE_SRC_FOR_SUSPEND_COMMON__ |	\
+	 R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+	.timer_val = 0x28000,
+	.wake_src = WAKE_SRC_FOR_SUSPEND,
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	.reg_wfi_op = 0,
+	.reg_wfi_type = 0,
+	.reg_mp0_cputop_idle_mask = 0,
+	.reg_mp1_cputop_idle_mask = 0,
+	.reg_mcusys_idle_mask = 0,
+	.reg_md_apsrc_1_sel = 0,
+	.reg_md_apsrc_0_sel = 0,
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC6_MASK */
+	.reg_ccif_event_infra_req_mask_b = 0,
+	.reg_ccif_event_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_apsrc_req = 0,
+	.reg_spm_f26m_req = 0,
+	.reg_spm_infra_req = 0,
+	.reg_spm_vrf18_req = 0,
+	.reg_spm_ddren_req = 0,
+	.reg_spm_dvfs_req = 0,
+	.reg_spm_sw_mailbox_req = 0,
+	.reg_spm_sspm_mailbox_req = 0,
+	.reg_spm_adsp_mailbox_req = 0,
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	.reg_md_0_srcclkena_mask_b = 0,
+	.reg_md_0_infra_req_mask_b = 0,
+	.reg_md_0_apsrc_req_mask_b = 0,
+	.reg_md_0_vrf18_req_mask_b = 0,
+	.reg_md_0_ddren_req_mask_b = 0,
+	.reg_md_1_srcclkena_mask_b = 0,
+	.reg_md_1_infra_req_mask_b = 0,
+	.reg_md_1_apsrc_req_mask_b = 0,
+	.reg_md_1_vrf18_req_mask_b = 0,
+	.reg_md_1_ddren_req_mask_b = 0,
+	.reg_conn_srcclkena_mask_b = 1,
+	.reg_conn_srcclkenb_mask_b = 0,
+	.reg_conn_infra_req_mask_b = 1,
+	.reg_conn_apsrc_req_mask_b = 1,
+	.reg_conn_vrf18_req_mask_b = 1,
+	.reg_conn_ddren_req_mask_b = 1,
+	.reg_conn_vfe28_mask_b = 0,
+	.reg_srcclkeni_srcclkena_mask_b = 1,
+	.reg_srcclkeni_infra_req_mask_b = 1,
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	.reg_infrasys_ddren_req_mask_b = 1,
+	.reg_sspm_srcclkena_mask_b = 1,
+	.reg_sspm_infra_req_mask_b = 1,
+	.reg_sspm_apsrc_req_mask_b = 1,
+	.reg_sspm_vrf18_req_mask_b = 1,
+	.reg_sspm_ddren_req_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	.reg_scp_srcclkena_mask_b = 1,
+	.reg_scp_infra_req_mask_b = 1,
+	.reg_scp_apsrc_req_mask_b = 1,
+	.reg_scp_vrf18_req_mask_b = 1,
+	.reg_scp_ddren_req_mask_b = 1,
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	.reg_audio_dsp_ddren_req_mask_b = 1,
+	.reg_ufs_srcclkena_mask_b = 1,
+	.reg_ufs_infra_req_mask_b = 1,
+	.reg_ufs_apsrc_req_mask_b = 1,
+	.reg_ufs_vrf18_req_mask_b = 1,
+	.reg_ufs_ddren_req_mask_b = 1,
+	.reg_disp0_apsrc_req_mask_b = 1,
+	.reg_disp0_ddren_req_mask_b = 1,
+	.reg_disp1_apsrc_req_mask_b = 1,
+	.reg_disp1_ddren_req_mask_b = 1,
+	.reg_gce_infra_req_mask_b = 1,
+	.reg_gce_apsrc_req_mask_b = 1,
+	.reg_gce_vrf18_req_mask_b = 1,
+	.reg_gce_ddren_req_mask_b = 1,
+	.reg_apu_srcclkena_mask_b = 0,
+	.reg_apu_infra_req_mask_b = 0,
+	.reg_apu_apsrc_req_mask_b = 0,
+	.reg_apu_vrf18_req_mask_b = 0,
+	.reg_apu_ddren_req_mask_b = 0,
+	.reg_cg_check_srcclkena_mask_b = 0,
+	.reg_cg_check_apsrc_req_mask_b = 0,
+	.reg_cg_check_vrf18_req_mask_b = 0,
+	.reg_cg_check_ddren_req_mask_b = 0,
+
+	/* SPM_SRC3_MASK */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+	.reg_sw2spm_wakeup_mask_b = 0,
+	.reg_adsp2spm_wakeup_mask_b = 0,
+	.reg_sspm2spm_wakeup_mask_b = 0,
+	.reg_scp2spm_wakeup_mask_b = 0,
+	.reg_csyspwrup_ack_mask = 1,
+	.reg_spm_reserved_srcclkena_mask_b = 0,
+	.reg_spm_reserved_infra_req_mask_b = 0,
+	.reg_spm_reserved_apsrc_req_mask_b = 0,
+	.reg_spm_reserved_vrf18_req_mask_b = 0,
+	.reg_spm_reserved_ddren_req_mask_b = 0,
+	.reg_mcupm_srcclkena_mask_b = 0,
+	.reg_mcupm_infra_req_mask_b = 0,
+	.reg_mcupm_apsrc_req_mask_b = 0,
+	.reg_mcupm_vrf18_req_mask_b = 0,
+	.reg_mcupm_ddren_req_mask_b = 0,
+	.reg_msdc0_srcclkena_mask_b = 1,
+	.reg_msdc0_infra_req_mask_b = 1,
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	.reg_msdc0_ddren_req_mask_b = 1,
+	.reg_msdc1_srcclkena_mask_b = 1,
+	.reg_msdc1_infra_req_mask_b = 1,
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	.reg_msdc1_ddren_req_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	.reg_ccif_event_srcclkena_mask_b = 0,
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	.reg_bak_psri_infra_req_mask_b = 0,
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	.reg_bak_psri_ddren_req_mask_b = 0,
+	.reg_dramc_md32_infra_req_mask_b = 0,
+	.reg_dramc_md32_vrf18_req_mask_b = 0,
+	.reg_conn_srcclkenb2pwrap_mask_b = 0,
+	.reg_dramc_md32_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC5_MASK */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x83,
+	.reg_mcusys_merge_ddren_req_mask_b = 0x83,
+	.reg_afe_srcclkena_mask_b = 1,
+	.reg_afe_infra_req_mask_b = 1,
+	.reg_afe_apsrc_req_mask_b = 1,
+	.reg_afe_vrf18_req_mask_b = 1,
+	.reg_afe_ddren_req_mask_b = 1,
+	.reg_msdc2_srcclkena_mask_b = 0,
+	.reg_msdc2_infra_req_mask_b = 0,
+	.reg_msdc2_apsrc_req_mask_b = 0,
+	.reg_msdc2_vrf18_req_mask_b = 0,
+	.reg_msdc2_ddren_req_mask_b = 0,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0xE1283203,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/* SPM_SRC7_MASK */
+	.reg_pcie_srcclkena_mask_b = 0,
+	.reg_pcie_infra_req_mask_b = 0,
+	.reg_pcie_apsrc_req_mask_b = 0,
+	.reg_pcie_vrf18_req_mask_b = 0,
+	.reg_pcie_ddren_req_mask_b = 0,
+	.reg_dpmaif_srcclkena_mask_b = 1,
+	.reg_dpmaif_infra_req_mask_b = 1,
+	.reg_dpmaif_apsrc_req_mask_b = 1,
+	.reg_dpmaif_vrf18_req_mask_b = 1,
+	.reg_dpmaif_ddren_req_mask_b = 1,
+
+	/* Auto-gen End */
+};
+
+struct spm_lp_scen idle_spm_lp = {
+	.pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+			      spm_idle_conduct fn)
+{
+	unsigned int src_req = 0U;
+
+	if (fn != NULL) {
+		fn(&idle_spm_lp, &src_req);
+	}
+
+	return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+}
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status,
+				spm_idle_conduct_restore fn)
+{
+	ext_opand |= (MT_SPM_EX_OP_TIME_CHECK | MT_SPM_EX_OP_TIME_OBS);
+	spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+}
+
+void mt_spm_idle_generic_init(void)
+{
+	spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.h
new file mode 100644
index 0000000..7196190
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_idle.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp, unsigned int *resource_req);
+
+typedef int (*spm_idle_conduct_restore)(int state_id,
+					struct spm_lp_scen *spm_lp,
+					struct wake_status *status);
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand, spm_idle_conduct fn);
+
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+				struct wake_status **status,
+				spm_idle_conduct_restore fn);
+
+void mt_spm_idle_generic_init(void);
+
+#endif /* MT_SPM_IDLE_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.c
new file mode 100644
index 0000000..f228961
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.c
@@ -0,0 +1,623 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+/* Define and Declare */
+#define ROOT_CORE_ADDR_OFFSET			(0x20000000)
+#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK	(0xefffffff)
+#define SPM_INIT_DONE_US			(20)
+
+static unsigned int mt_spm_bblpm_cnt;
+
+const char *wakeup_src_str[32] = {
+	[0] = "R12_PCM_TIMER",
+	[1] = "R12_RESERVED_DEBUG_B",
+	[2] = "R12_KP_IRQ_B",
+	[3] = "R12_APWDT_EVENT_B",
+	[4] = "R12_APXGPT1_EVENT_B",
+	[5] = "R12_CONN2AP_SPM_WAKEUP_B",
+	[6] = "R12_EINT_EVENT_B",
+	[7] = "R12_CONN_WDT_IRQ_B",
+	[8] = "R12_CCIF0_EVENT_B",
+	[9] = "R12_LOWBATTERY_IRQ_B",
+	[10] = "R12_SC_SSPM2SPM_WAKEUP_B",
+	[11] = "R12_SC_SCP2SPM_WAKEUP_B",
+	[12] = "R12_SC_ADSP2SPM_WAKEUP_B",
+	[13] = "R12_PCM_WDT_WAKEUP_B",
+	[14] = "R12_USB_CDSC_B",
+	[15] = "R12_USB_POWERDWN_B",
+	[16] = "R12_SYS_TIMER_EVENT_B",
+	[17] = "R12_EINT_EVENT_SECURE_B",
+	[18] = "R12_CCIF1_EVENT_B",
+	[19] = "R12_UART0_IRQ_B",
+	[20] = "R12_AFE_IRQ_MCU_B",
+	[21] = "R12_THERM_CTRL_EVENT_B",
+	[22] = "R12_SYS_CIRQ_IRQ_B",
+	[23] = "R12_MD2AP_PEER_EVENT_B",
+	[24] = "R12_CSYSPWREQ_B",
+	[25] = "R12_MD1_WDT_B",
+	[26] = "R12_AP2AP_PEER_WAKEUPEVENT_B",
+	[27] = "R12_SEJ_EVENT_B",
+	[28] = "R12_SPM_CPU_WAKEUPEVENT_B",
+	[29] = "R12_APUSYS",
+	[30] = "R12_PCIE_BRIDGE_IRQ",
+	[31] = "R12_PCIE_IRQ",
+};
+
+/* Function and API */
+wake_reason_t __spm_output_wake_reason(int state_id, const struct wake_status *wakesta)
+{
+	uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
+	wake_reason_t wr = WR_UNKNOWN;
+
+	if (wakesta != NULL) {
+		if (wakesta->abort != 0U) {
+			ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
+			      wakesta->abort, wakesta->timer_out);
+		} else {
+			for (i = 0U; i < 32U; i++) {
+				if ((wakesta->r12 & BIT(i)) != 0U) {
+					INFO("wake up by %s, timer_out = %u\n",
+					     wakeup_src_str[i], wakesta->timer_out);
+					wr = WR_WAKE_SRC;
+					break;
+				}
+			}
+		}
+
+		INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+		     wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
+		     wakesta->debug_flag1);
+		INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
+		     wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
+		     wakesta->md32pcm_event_sta, wakesta->idle_sta,
+		     wakesta->cg_check_sta);
+		INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
+		     wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
+		     wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
+		INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
+		     wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
+		INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
+		     wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
+		INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
+		     wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
+		     wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
+		INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
+		     wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
+		     mmio_read_32(SYS_TIMER_VALUE_H));
+
+		if (wakesta->timer_out != 0U) {
+			bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
+			spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
+			INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
+		}
+	}
+
+	return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+	uint32_t root_core_addr;
+
+	if (cpu < 8U) {
+		mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu));
+
+		root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
+		root_core_addr += ROOT_CORE_ADDR_OFFSET;
+		mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
+
+		/* Notify SSPM that preferred cpu wakeup */
+		mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+	} else {
+		ERROR("%s: error cpu number %d\n", __func__, cpu);
+	}
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+			  unsigned int resource_usage)
+{
+	uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
+			     1 : pwrctrl->reg_spm_apsrc_req;
+	uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
+			     1 : pwrctrl->reg_spm_ddren_req;
+	uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
+			     1 : pwrctrl->reg_spm_vrf18_req;
+	uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
+			     1 : pwrctrl->reg_spm_infra_req;
+	uint8_t f26m_req  = ((resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
+			     1 : pwrctrl->reg_spm_f26m_req;
+
+	/*
+	 * if SPM_FLAG_SSPM_INFRA_SLEEP_MODE set,
+	 * clear sspm_srclkena_mask_b and sspm_infra_mask_b
+	 */
+	uint8_t reg_sspm_srcclkena_mask_b =
+		(pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
+		 ? 0U : pwrctrl->reg_sspm_srcclkena_mask_b;
+
+	uint8_t reg_sspm_infra_req_mask_b =
+		(pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
+		 ? 0 : pwrctrl->reg_sspm_infra_req_mask_b;
+
+	/* SPM_SRC_REQ */
+	mmio_write_32(SPM_SRC_REQ,
+		      ((apsrc_req & 0x1) << 0) |
+		      ((f26m_req & 0x1) << 1) |
+		      ((infra_req & 0x1) << 3) |
+		      ((vrf18_req & 0x1) << 4) |
+		      ((ddr_en_req & 0x1) << 7) |
+		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	mmio_write_32(SPM_SRC_MASK,
+		      ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
+		      ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
+		      ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
+		      ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
+		      ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
+		      ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
+		      ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
+		      ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
+		      ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
+		      ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
+		      ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
+		      ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
+		      ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
+		      ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
+		      ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
+		      ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
+		      ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
+		      ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
+		      ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
+		      ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
+		      ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
+		      ((reg_sspm_srcclkena_mask_b & 0x1) << 27) |
+		      ((reg_sspm_infra_req_mask_b & 0x1) << 28) |
+		      ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
+		      ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
+		      ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	mmio_write_32(SPM_AP_STANDBY_CON,
+		      ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+		      ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+		      ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+		      ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+		      ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+		      ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+		      ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+		      ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+	/* SPM_SRC6_MASK */
+	mmio_write_32(SPM_SRC6_MASK,
+		      ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |
+		      ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));
+
+	/* SPM_SRC_REQ */
+	mmio_write_32(SPM_SRC_REQ,
+		      ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+		      ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+		      ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+		      ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+		      ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |
+		      ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+		      ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+		      ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+		      ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+		      ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+	/* SPM_SRC_MASK */
+	mmio_write_32(SPM_SRC_MASK,
+		      ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
+		      ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
+		      ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
+		      ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
+		      ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
+		      ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
+		      ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
+		      ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
+		      ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
+		      ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
+		      ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
+		      ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
+		      ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
+		      ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
+		      ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
+		      ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
+		      ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
+		      ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
+		      ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
+		      ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
+		      ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
+		      ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |
+		      ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |
+		      ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
+		      ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
+		      ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC2_MASK */
+	mmio_write_32(SPM_SRC2_MASK,
+		((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |
+		((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
+		((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC3_MASK */
+	mmio_write_32(SPM_SRC3_MASK,
+		((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |
+		((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |
+		((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |
+		((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |
+		((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |
+		((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |
+		((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |
+		((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |
+		((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
+		((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
+		((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
+		((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
+		((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));
+
+	/* SPM_SRC4_MASK */
+	mmio_write_32(SPM_SRC4_MASK,
+		((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |
+		((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
+		((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
+		((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |
+		((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |
+		((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));
+
+	/* SPM_SRC5_MASK */
+	mmio_write_32(SPM_SRC5_MASK,
+		((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+		((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |
+		((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |
+		((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |
+		((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |
+		((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |
+		((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |
+		((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |
+		((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |
+		((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |
+		((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |
+		((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+		((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+		((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+
+	/* SPM_SRC7_MASK */
+	mmio_write_32(SPM_SRC7_MASK,
+		((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |
+		((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |
+		((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |
+		((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |
+		((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |
+		((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |
+		((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |
+		((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |
+		((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |
+		((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));
+	/* Auto-gen End */
+}
+
+void __spm_disable_pcm_timer(void)
+{
+	mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+}
+
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+	uint32_t val, mask;
+
+	/* toggle event counter clear */
+	mmio_setbits_32(PCM_CON1,
+			SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB);
+
+	/* toggle for reset SYS TIMER start point */
+	mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+	if (pwrctrl->timer_val_cust == 0U) {
+		val = pwrctrl->timer_val ? (pwrctrl->timer_val) : (PCM_TIMER_MAX);
+	} else {
+		val = pwrctrl->timer_val_cust;
+	}
+
+	mmio_write_32(PCM_TIMER_VAL, val);
+	mmio_setbits_32(PCM_CON1, (SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB));
+
+	/* unmask AP wakeup source */
+	if (pwrctrl->wake_src_cust == 0U) {
+		mask = pwrctrl->wake_src;
+	} else {
+		mask = pwrctrl->wake_src_cust;
+	}
+
+	if (pwrctrl->reg_csyspwrup_ack_mask != 0U) {
+		mask &= ~R12_CSYSPWREQ_B;
+	}
+
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+	/* unmask SPM ISR (keep TWAM setting) */
+	mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+	/* toggle event counter clear */
+	mmio_clrsetbits_32(PCM_CON1, REG_SPM_EVENT_COUNTER_CLR_LSB,
+			   SPM_REGWR_CFG_KEY);
+	/* toggle for reset SYS TIMER start point */
+	mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+	/* set PCM flags and data */
+	if (pwrctrl->pcm_flags_cust_clr != 0U) {
+		pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+	}
+
+	if (pwrctrl->pcm_flags_cust_set != 0U) {
+		pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+	}
+
+	if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+		pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+	}
+
+	if (pwrctrl->pcm_flags1_cust_set != 0U) {
+		pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+	}
+
+	mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+
+	mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+
+	mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+
+	mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta,
+			     unsigned int ext_status)
+{
+	wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+	wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+	wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+	wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+	wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+	wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+	wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+	wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+	wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+	wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+	if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+		wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+						SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+		mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag);
+	}
+
+	wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+	wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+	/* record below spm info for debug */
+	wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+	wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
+	wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+	wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+	wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+	wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+	wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
+
+	/* backup of SPM_WAKEUP_MISC */
+	wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
+
+	/* get sleep time, backup of PCM_TIMER_OUT */
+	wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+
+	/* get other SYS and co-clock status */
+	wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
+	wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+	wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+	wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+	wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+	wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+	wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+	/* get HW CG check status */
+	wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
+
+	/* get debug flag for PCM execution check */
+	wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+	wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+	/* get backup SW flag status */
+	wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+	wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+	wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
+	wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
+	wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
+	wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
+	wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
+
+	/* get ISR status */
+	wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+	/* get SW flag status */
+	wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+	wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+	/* get CLK SETTLE */
+	wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
+
+	/* check abort */
+	wakesta->abort = ((wakesta->debug_flag & DEBUG_ABORT_MASK) |
+			  (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1));
+}
+
+void __spm_clean_after_wakeup(void)
+{
+	mmio_write_32(SPM_BK_WAKE_EVENT,
+		      (mmio_read_32(SPM_WAKEUP_STA) |
+		       mmio_read_32(SPM_BK_WAKE_EVENT)));
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U);
+
+	/*
+	 * clean wakeup event raw status (for edge trigger event)
+	 * bit[28] for cpu wake up event
+	 */
+	mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
+
+	/* clean ISR status (except TWAM) */
+	mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+	mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+	mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+	mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
+			   SPM_REGWR_CFG_KEY);
+
+	if (en == 1) {
+		mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
+				   SPM_REGWR_CFG_KEY);
+
+		if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+			mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+		}
+
+		mmio_write_32(PCM_WDT_VAL,
+			      mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+		mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+	}
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+	/* SPM will clear SPM_CPU_WAKEUP_EVENT */
+	mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+	unsigned int reg = mmio_read_32(SPM_MD32_IRQ) & (~(0x1U << 0));
+
+	mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+	/* Clear spm2mcupm wakeup interrupt status */
+	mmio_write_32(SPM_MD32_IRQ, reg);
+}
+
+void __spm_xo_soc_bblpm(int en)
+{
+	if (en == 1) {
+		mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+				   RC_SW_SRCCLKEN_FPM, RC_SW_SRCCLKEN_RC);
+		assert(mt_spm_bblpm_cnt == 0);
+		mt_spm_bblpm_cnt += 1;
+	} else {
+		mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+				   RC_SW_SRCCLKEN_RC, RC_SW_SRCCLKEN_FPM);
+		mt_spm_bblpm_cnt -= 1;
+	}
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+	unsigned int reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+	if (en == 1) {
+		reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+		reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
+		mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+		reg |= SPM_ACK_CHK_3_CON_EN;
+		mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+	} else {
+		if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
+		    (status != NULL)) {
+			*status |= SPM_INTERNAL_STATUS_HW_S1;
+		}
+
+		mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+				   SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
+				   SPM_ACK_CHK_3_CON_CLR_ALL);
+	}
+}
+
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h
new file mode 100644
index 0000000..760900d
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_internal.h
@@ -0,0 +1,618 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL
+#define MT_SPM_INTERNAL
+
+#include "mt_spm.h"
+
+/* Config and Parameter */
+#define POWER_ON_VAL0_DEF	(0x0000F100)
+#define POWER_ON_VAL1_DEF	(0x80015860)
+#define PCM_WDT_TIMEOUT		(30 * 32768)	/* 30s */
+#define PCM_TIMER_MAX		(0xffffffff - PCM_WDT_TIMEOUT)
+
+/* Define and Declare */
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0		BIT(0)
+#define PCM_PWRIO_EN_R7		BIT(7)
+#define PCM_RF_SYNC_R0		BIT(16)
+#define PCM_RF_SYNC_R6		BIT(22)
+#define PCM_RF_SYNC_R7		BIT(23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0		BIT(0)
+#define PCM_SW_INT1		BIT(1)
+#define PCM_SW_INT2		BIT(2)
+#define PCM_SW_INT3		BIT(3)
+#define PCM_SW_INT4		BIT(4)
+#define PCM_SW_INT5		BIT(5)
+#define PCM_SW_INT6		BIT(6)
+#define PCM_SW_INT7		BIT(7)
+#define PCM_SW_INT8		BIT(8)
+#define PCM_SW_INT9		BIT(9)
+#define PCM_SW_INT_ALL		(PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+				 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+				 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+				 PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND		(1U)
+#define WFI_OP_OR		(0U)
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM		(1U << 2)
+#define ISRM_PCM_RETURN		(1U << 3)
+#define ISRM_RET_IRQ0		(1U << 8)
+#define ISRM_RET_IRQ1		(1U << 9)
+#define ISRM_RET_IRQ2		(1U << 10)
+#define ISRM_RET_IRQ3		(1U << 11)
+#define ISRM_RET_IRQ4		(1U << 12)
+#define ISRM_RET_IRQ5		(1U << 13)
+#define ISRM_RET_IRQ6		(1U << 14)
+#define ISRM_RET_IRQ7		(1U << 15)
+#define ISRM_RET_IRQ8		(1U << 16)
+#define ISRM_RET_IRQ9		(1U << 17)
+#define ISRM_RET_IRQ_AUX	((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+				 (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+				 (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+				 (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+				 (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM	(ISRM_RET_IRQ_AUX)
+#define ISRM_ALL		(ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM		BIT(2)
+#define ISRS_PCM_RETURN		BIT(3)
+#define ISRC_TWAM		ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM	ISRS_PCM_RETURN
+#define ISRC_ALL		(ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP			(0x3FF)
+#define WAKE_MISC_DVFSRC_IRQ			DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP		SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT		PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_PMIC_OUT_B			((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B			TWAM_IRQ_B_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0		SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1		SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2		SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3		SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL	SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK			PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ			PMIC_SCP_IRQ_LSB
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK				\
+	(SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC |	\
+	 SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1					\
+	(SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT |			\
+	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT |	\
+	 SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT |		\
+	 SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU	(0x0C55FD10)
+
+struct pwr_ctrl {
+	uint32_t pcm_flags;
+	uint32_t pcm_flags_cust;
+	uint32_t pcm_flags_cust_set;
+	uint32_t pcm_flags_cust_clr;
+	uint32_t pcm_flags1;
+	uint32_t pcm_flags1_cust;
+	uint32_t pcm_flags1_cust_set;
+	uint32_t pcm_flags1_cust_clr;
+	uint32_t timer_val;
+	uint32_t timer_val_cust;
+	uint32_t timer_val_ramp_en;
+	uint32_t timer_val_ramp_en_sec;
+	uint32_t wake_src;
+	uint32_t wake_src_cust;
+	uint32_t wakelock_timer_val;
+	uint8_t wdt_disable;
+
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	uint8_t reg_wfi_op;
+	uint8_t reg_wfi_type;
+	uint8_t reg_mp0_cputop_idle_mask;
+	uint8_t reg_mp1_cputop_idle_mask;
+	uint8_t reg_mcusys_idle_mask;
+	uint8_t reg_md_apsrc_1_sel;
+	uint8_t reg_md_apsrc_0_sel;
+	uint8_t reg_conn_apsrc_sel;
+
+	/* SPM_SRC6_MASK */
+	uint32_t reg_ccif_event_infra_req_mask_b;
+	uint32_t reg_ccif_event_apsrc_req_mask_b;
+
+	/* SPM_SRC_REQ */
+	uint8_t reg_spm_apsrc_req;
+	uint8_t reg_spm_f26m_req;
+	uint8_t reg_spm_infra_req;
+	uint8_t reg_spm_vrf18_req;
+	uint8_t reg_spm_ddren_req;
+	uint8_t reg_spm_dvfs_req;
+	uint8_t reg_spm_sw_mailbox_req;
+	uint8_t reg_spm_sspm_mailbox_req;
+	uint8_t reg_spm_adsp_mailbox_req;
+	uint8_t reg_spm_scp_mailbox_req;
+
+	/* SPM_SRC_MASK */
+	uint8_t reg_md_0_srcclkena_mask_b;
+	uint8_t reg_md_0_infra_req_mask_b;
+	uint8_t reg_md_0_apsrc_req_mask_b;
+	uint8_t reg_md_0_vrf18_req_mask_b;
+	uint8_t reg_md_0_ddren_req_mask_b;
+	uint8_t reg_md_1_srcclkena_mask_b;
+	uint8_t reg_md_1_infra_req_mask_b;
+	uint8_t reg_md_1_apsrc_req_mask_b;
+	uint8_t reg_md_1_vrf18_req_mask_b;
+	uint8_t reg_md_1_ddren_req_mask_b;
+	uint8_t reg_conn_srcclkena_mask_b;
+	uint8_t reg_conn_srcclkenb_mask_b;
+	uint8_t reg_conn_infra_req_mask_b;
+	uint8_t reg_conn_apsrc_req_mask_b;
+	uint8_t reg_conn_vrf18_req_mask_b;
+	uint8_t reg_conn_ddren_req_mask_b;
+	uint8_t reg_conn_vfe28_mask_b;
+	uint8_t reg_srcclkeni_srcclkena_mask_b;
+	uint8_t reg_srcclkeni_infra_req_mask_b;
+	uint8_t reg_infrasys_apsrc_req_mask_b;
+	uint8_t reg_infrasys_ddren_req_mask_b;
+	uint8_t reg_sspm_srcclkena_mask_b;
+	uint8_t reg_sspm_infra_req_mask_b;
+	uint8_t reg_sspm_apsrc_req_mask_b;
+	uint8_t reg_sspm_vrf18_req_mask_b;
+	uint8_t reg_sspm_ddren_req_mask_b;
+
+	/* SPM_SRC2_MASK */
+	uint8_t reg_scp_srcclkena_mask_b;
+	uint8_t reg_scp_infra_req_mask_b;
+	uint8_t reg_scp_apsrc_req_mask_b;
+	uint8_t reg_scp_vrf18_req_mask_b;
+	uint8_t reg_scp_ddren_req_mask_b;
+	uint8_t reg_audio_dsp_srcclkena_mask_b;
+	uint8_t reg_audio_dsp_infra_req_mask_b;
+	uint8_t reg_audio_dsp_apsrc_req_mask_b;
+	uint8_t reg_audio_dsp_vrf18_req_mask_b;
+	uint8_t reg_audio_dsp_ddren_req_mask_b;
+	uint8_t reg_ufs_srcclkena_mask_b;
+	uint8_t reg_ufs_infra_req_mask_b;
+	uint8_t reg_ufs_apsrc_req_mask_b;
+	uint8_t reg_ufs_vrf18_req_mask_b;
+	uint8_t reg_ufs_ddren_req_mask_b;
+	uint8_t reg_disp0_apsrc_req_mask_b;
+	uint8_t reg_disp0_ddren_req_mask_b;
+	uint8_t reg_disp1_apsrc_req_mask_b;
+	uint8_t reg_disp1_ddren_req_mask_b;
+	uint8_t reg_gce_infra_req_mask_b;
+	uint8_t reg_gce_apsrc_req_mask_b;
+	uint8_t reg_gce_vrf18_req_mask_b;
+	uint8_t reg_gce_ddren_req_mask_b;
+	uint8_t reg_apu_srcclkena_mask_b;
+	uint8_t reg_apu_infra_req_mask_b;
+	uint8_t reg_apu_apsrc_req_mask_b;
+	uint8_t reg_apu_vrf18_req_mask_b;
+	uint8_t reg_apu_ddren_req_mask_b;
+	uint8_t reg_cg_check_srcclkena_mask_b;
+	uint8_t reg_cg_check_apsrc_req_mask_b;
+	uint8_t reg_cg_check_vrf18_req_mask_b;
+	uint8_t reg_cg_check_ddren_req_mask_b;
+
+	/* SPM_SRC3_MASK */
+	uint8_t reg_dvfsrc_event_trigger_mask_b;
+	uint8_t reg_sw2spm_wakeup_mask_b;
+	uint8_t reg_adsp2spm_wakeup_mask_b;
+	uint8_t reg_sspm2spm_wakeup_mask_b;
+	uint8_t reg_scp2spm_wakeup_mask_b;
+	uint8_t reg_csyspwrup_ack_mask;
+	uint8_t reg_spm_reserved_srcclkena_mask_b;
+	uint8_t reg_spm_reserved_infra_req_mask_b;
+	uint8_t reg_spm_reserved_apsrc_req_mask_b;
+	uint8_t reg_spm_reserved_vrf18_req_mask_b;
+	uint8_t reg_spm_reserved_ddren_req_mask_b;
+	uint8_t reg_mcupm_srcclkena_mask_b;
+	uint8_t reg_mcupm_infra_req_mask_b;
+	uint8_t reg_mcupm_apsrc_req_mask_b;
+	uint8_t reg_mcupm_vrf18_req_mask_b;
+	uint8_t reg_mcupm_ddren_req_mask_b;
+	uint8_t reg_msdc0_srcclkena_mask_b;
+	uint8_t reg_msdc0_infra_req_mask_b;
+	uint8_t reg_msdc0_apsrc_req_mask_b;
+	uint8_t reg_msdc0_vrf18_req_mask_b;
+	uint8_t reg_msdc0_ddren_req_mask_b;
+	uint8_t reg_msdc1_srcclkena_mask_b;
+	uint8_t reg_msdc1_infra_req_mask_b;
+	uint8_t reg_msdc1_apsrc_req_mask_b;
+	uint8_t reg_msdc1_vrf18_req_mask_b;
+	uint8_t reg_msdc1_ddren_req_mask_b;
+
+	/* SPM_SRC4_MASK */
+	uint32_t reg_ccif_event_srcclkena_mask_b;
+	uint8_t reg_bak_psri_srcclkena_mask_b;
+	uint8_t reg_bak_psri_infra_req_mask_b;
+	uint8_t reg_bak_psri_apsrc_req_mask_b;
+	uint8_t reg_bak_psri_vrf18_req_mask_b;
+	uint8_t reg_bak_psri_ddren_req_mask_b;
+	uint8_t reg_dramc_md32_infra_req_mask_b;
+	uint8_t reg_dramc_md32_vrf18_req_mask_b;
+	uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+	uint8_t reg_dramc_md32_apsrc_req_mask_b;
+
+	/* SPM_SRC5_MASK */
+	uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+	uint32_t reg_mcusys_merge_ddren_req_mask_b;
+	uint8_t reg_afe_srcclkena_mask_b;
+	uint8_t reg_afe_infra_req_mask_b;
+	uint8_t reg_afe_apsrc_req_mask_b;
+	uint8_t reg_afe_vrf18_req_mask_b;
+	uint8_t reg_afe_ddren_req_mask_b;
+	uint8_t reg_msdc2_srcclkena_mask_b;
+	uint8_t reg_msdc2_infra_req_mask_b;
+	uint8_t reg_msdc2_apsrc_req_mask_b;
+	uint8_t reg_msdc2_vrf18_req_mask_b;
+	uint8_t reg_msdc2_ddren_req_mask_b;
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	uint32_t reg_wakeup_event_mask;
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	uint32_t reg_ext_wakeup_event_mask;
+
+	/* SPM_SRC7_MASK */
+	uint8_t reg_pcie_srcclkena_mask_b;
+	uint8_t reg_pcie_infra_req_mask_b;
+	uint8_t reg_pcie_apsrc_req_mask_b;
+	uint8_t reg_pcie_vrf18_req_mask_b;
+	uint8_t reg_pcie_ddren_req_mask_b;
+	uint8_t reg_dpmaif_srcclkena_mask_b;
+	uint8_t reg_dpmaif_infra_req_mask_b;
+	uint8_t reg_dpmaif_apsrc_req_mask_b;
+	uint8_t reg_dpmaif_vrf18_req_mask_b;
+	uint8_t reg_dpmaif_ddren_req_mask_b;
+
+	/* Auto-gen End */
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+	PW_PCM_FLAGS,
+	PW_PCM_FLAGS_CUST,
+	PW_PCM_FLAGS_CUST_SET,
+	PW_PCM_FLAGS_CUST_CLR,
+	PW_PCM_FLAGS1,
+	PW_PCM_FLAGS1_CUST,
+	PW_PCM_FLAGS1_CUST_SET,
+	PW_PCM_FLAGS1_CUST_CLR,
+	PW_TIMER_VAL,
+	PW_TIMER_VAL_CUST,
+	PW_TIMER_VAL_RAMP_EN,
+	PW_TIMER_VAL_RAMP_EN_SEC,
+	PW_WAKE_SRC,
+	PW_WAKE_SRC_CUST,
+	PW_WAKELOCK_TIMER_VAL,
+	PW_WDT_DISABLE,
+
+	/* SPM_AP_STANDBY_CON */
+	PW_REG_WFI_OP,
+	PW_REG_WFI_TYPE,
+	PW_REG_MP0_CPUTOP_IDLE_MASK,
+	PW_REG_MP1_CPUTOP_IDLE_MASK,
+	PW_REG_MCUSYS_IDLE_MASK,
+	PW_REG_MD_APSRC_1_SEL,
+	PW_REG_MD_APSRC_0_SEL,
+	PW_REG_CONN_APSRC_SEL,
+
+	/* SPM_SRC6_MASK */
+	PW_REG_CCIF_EVENT_INFRA_REQ_MASK_B,
+	PW_REG_CCIF_EVENT_APSRC_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_SENS */
+	PW_REG_WAKEUP_EVENT_SENS,
+
+	/* SPM_SRC_REQ */
+	PW_REG_SPM_APSRC_REQ,
+	PW_REG_SPM_F26M_REQ,
+	PW_REG_SPM_INFRA_REQ,
+	PW_REG_SPM_VRF18_REQ,
+	PW_REG_SPM_DDREN_REQ,
+	PW_REG_SPM_DVFS_REQ,
+	PW_REG_SPM_SW_MAILBOX_REQ,
+	PW_REG_SPM_SSPM_MAILBOX_REQ,
+	PW_REG_SPM_ADSP_MAILBOX_REQ,
+	PW_REG_SPM_SCP_MAILBOX_REQ,
+
+	/* SPM_SRC_MASK */
+	PW_REG_MD_0_SRCCLKENA_MASK_B,
+	PW_REG_MD_0_INFRA_REQ_MASK_B,
+	PW_REG_MD_0_APSRC_REQ_MASK_B,
+	PW_REG_MD_0_VRF18_REQ_MASK_B,
+	PW_REG_MD_0_DDREN_REQ_MASK_B,
+	PW_REG_MD_1_SRCCLKENA_MASK_B,
+	PW_REG_MD_1_INFRA_REQ_MASK_B,
+	PW_REG_MD_1_APSRC_REQ_MASK_B,
+	PW_REG_MD_1_VRF18_REQ_MASK_B,
+	PW_REG_MD_1_DDREN_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENA_MASK_B,
+	PW_REG_CONN_SRCCLKENB_MASK_B,
+	PW_REG_CONN_INFRA_REQ_MASK_B,
+	PW_REG_CONN_APSRC_REQ_MASK_B,
+	PW_REG_CONN_VRF18_REQ_MASK_B,
+	PW_REG_CONN_DDREN_REQ_MASK_B,
+	PW_REG_CONN_VFE28_MASK_B,
+	PW_REG_SRCCLKENI_SRCCLKENA_MASK_B,
+	PW_REG_SRCCLKENI_INFRA_REQ_MASK_B,
+	PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+	PW_REG_INFRASYS_DDREN_REQ_MASK_B,
+	PW_REG_SSPM_SRCCLKENA_MASK_B,
+	PW_REG_SSPM_INFRA_REQ_MASK_B,
+	PW_REG_SSPM_APSRC_REQ_MASK_B,
+	PW_REG_SSPM_VRF18_REQ_MASK_B,
+	PW_REG_SSPM_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC2_MASK */
+	PW_REG_SCP_SRCCLKENA_MASK_B,
+	PW_REG_SCP_INFRA_REQ_MASK_B,
+	PW_REG_SCP_APSRC_REQ_MASK_B,
+	PW_REG_SCP_VRF18_REQ_MASK_B,
+	PW_REG_SCP_DDREN_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+	PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+	PW_REG_AUDIO_DSP_DDREN_REQ_MASK_B,
+	PW_REG_UFS_SRCCLKENA_MASK_B,
+	PW_REG_UFS_INFRA_REQ_MASK_B,
+	PW_REG_UFS_APSRC_REQ_MASK_B,
+	PW_REG_UFS_VRF18_REQ_MASK_B,
+	PW_REG_UFS_DDREN_REQ_MASK_B,
+	PW_REG_DISP0_APSRC_REQ_MASK_B,
+	PW_REG_DISP0_DDREN_REQ_MASK_B,
+	PW_REG_DISP1_APSRC_REQ_MASK_B,
+	PW_REG_DISP1_DDREN_REQ_MASK_B,
+	PW_REG_GCE_INFRA_REQ_MASK_B,
+	PW_REG_GCE_APSRC_REQ_MASK_B,
+	PW_REG_GCE_VRF18_REQ_MASK_B,
+	PW_REG_GCE_DDREN_REQ_MASK_B,
+	PW_REG_APU_SRCCLKENA_MASK_B,
+	PW_REG_APU_INFRA_REQ_MASK_B,
+	PW_REG_APU_APSRC_REQ_MASK_B,
+	PW_REG_APU_VRF18_REQ_MASK_B,
+	PW_REG_APU_DDREN_REQ_MASK_B,
+	PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+	PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+	PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+	PW_REG_CG_CHECK_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC3_MASK */
+	PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+	PW_REG_SW2SPM_WAKEUP_MASK_B,
+	PW_REG_ADSP2SPM_WAKEUP_MASK_B,
+	PW_REG_SSPM2SPM_WAKEUP_MASK_B,
+	PW_REG_SCP2SPM_WAKEUP_MASK_B,
+	PW_REG_CSYSPWRUP_ACK_MASK,
+	PW_REG_SPM_RESERVED_SRCCLKENA_MASK_B,
+	PW_REG_SPM_RESERVED_INFRA_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_APSRC_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_VRF18_REQ_MASK_B,
+	PW_REG_SPM_RESERVED_DDREN_REQ_MASK_B,
+	PW_REG_MCUPM_SRCCLKENA_MASK_B,
+	PW_REG_MCUPM_INFRA_REQ_MASK_B,
+	PW_REG_MCUPM_APSRC_REQ_MASK_B,
+	PW_REG_MCUPM_VRF18_REQ_MASK_B,
+	PW_REG_MCUPM_DDREN_REQ_MASK_B,
+	PW_REG_MSDC0_SRCCLKENA_MASK_B,
+	PW_REG_MSDC0_INFRA_REQ_MASK_B,
+	PW_REG_MSDC0_APSRC_REQ_MASK_B,
+	PW_REG_MSDC0_VRF18_REQ_MASK_B,
+	PW_REG_MSDC0_DDREN_REQ_MASK_B,
+	PW_REG_MSDC1_SRCCLKENA_MASK_B,
+	PW_REG_MSDC1_INFRA_REQ_MASK_B,
+	PW_REG_MSDC1_APSRC_REQ_MASK_B,
+	PW_REG_MSDC1_VRF18_REQ_MASK_B,
+	PW_REG_MSDC1_DDREN_REQ_MASK_B,
+
+	/* SPM_SRC4_MASK */
+	PW_REG_CCIF_EVENT_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+	PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+	PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+	PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+	PW_REG_BAK_PSRI_DDREN_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_INFRA_REQ_MASK_B,
+	PW_REG_DRAMC_MD32_VRF18_REQ_MASK_B,
+	PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+	PW_REG_DRAMC_MD32_APSRC_REQ_MASK_B,
+
+	/* SPM_SRC5_MASK */
+	PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+	PW_REG_MCUSYS_MERGE_DDREN_REQ_MASK_B,
+	PW_REG_AFE_SRCCLKENA_MASK_B,
+	PW_REG_AFE_INFRA_REQ_MASK_B,
+	PW_REG_AFE_APSRC_REQ_MASK_B,
+	PW_REG_AFE_VRF18_REQ_MASK_B,
+	PW_REG_AFE_DDREN_REQ_MASK_B,
+	PW_REG_MSDC2_SRCCLKENA_MASK_B,
+	PW_REG_MSDC2_INFRA_REQ_MASK_B,
+	PW_REG_MSDC2_APSRC_REQ_MASK_B,
+	PW_REG_MSDC2_VRF18_REQ_MASK_B,
+	PW_REG_MSDC2_DDREN_REQ_MASK_B,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	PW_REG_WAKEUP_EVENT_MASK,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+	/* SPM_SRC7_MASK */
+	PW_REG_PCIE_SRCCLKENA_MASK_B,
+	PW_REG_PCIE_INFRA_REQ_MASK_B,
+	PW_REG_PCIE_APSRC_REQ_MASK_B,
+	PW_REG_PCIE_VRF18_REQ_MASK_B,
+	PW_REG_PCIE_DDREN_REQ_MASK_B,
+	PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+	PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+	PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+	PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+	PW_REG_DPMAIF_DDREN_REQ_MASK_B,
+
+	PW_MAX_COUNT,
+};
+
+/*
+ * ACK HW MODE SETTING
+ * 0: trigger(1)
+ * 1: trigger(0)
+ * 2: trigger(1) and target(0)
+ * 3: trigger(0) and target(1)
+ * 4: trigger(1) and target(1)
+ * 5: trigger(0) and target(0)
+ */
+#define TRIG_H_TAR_L		(2U)
+#define TRIG_L_TAR_H		(3U)
+#define TRIG_H_TAR_H		(4U)
+#define TRIG_L_TAR_L		(5U)
+
+#define SPM_INTERNAL_STATUS_HW_S1	(1U << 0)
+#define SPM_ACK_CHK_3_SEL_HW_S1		(0x00350098)
+#define SPM_ACK_CHK_3_HW_S1_CNT		(1U)
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG	(TRIG_L_TAR_H << 9u)
+#define SPM_ACK_CHK_3_CON_EN		(0x110)
+#define SPM_ACK_CHK_3_CON_CLR_ALL	(0x2)
+#define SPM_ACK_CHK_3_CON_RESULT	(0x8000)
+
+struct wake_status_trace_comm {
+	uint32_t debug_flag;	/* PCM_WDT_LATCH_SPARE_0 */
+	uint32_t debug_flag1;	/* PCM_WDT_LATCH_SPARE_1 */
+	uint32_t timer_out;	/* SPM_SW_RSV_6*/
+	uint32_t b_sw_flag0;	/* SPM_SW_RSV_7 */
+	uint32_t b_sw_flag1;	/* SPM_SW_RSV_7 */
+	uint32_t r12;		/* SPM_SW_RSV_0 */
+	uint32_t r13;		/* PCM_REG13_DATA */
+	uint32_t req_sta0;	/* SRC_REQ_STA_0 */
+	uint32_t req_sta1;	/* SRC_REQ_STA_1 */
+	uint32_t req_sta2;	/* SRC_REQ_STA_2 */
+	uint32_t req_sta3;	/* SRC_REQ_STA_3 */
+	uint32_t req_sta4;	/* SRC_REQ_STA_4 */
+	uint32_t raw_sta;	/* SPM_WAKEUP_STA */
+	uint32_t times_h;	/* timestamp high bits */
+	uint32_t times_l;	/* timestamp low bits */
+	uint32_t resumetime;	/* timestamp low bits */
+};
+
+struct wake_status_trace {
+	struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+	struct wake_status_trace tr;
+	uint32_t r12;			/* SPM_BK_WAKE_EVENT */
+	uint32_t r12_ext;		/* SPM_WAKEUP_EXT_STA */
+	uint32_t raw_sta;		/* SPM_WAKEUP_STA */
+	uint32_t raw_ext_sta;		/* SPM_WAKEUP_EXT_STA */
+	uint32_t md32pcm_wakeup_sta;	/* MD32CPM_WAKEUP_STA */
+	uint32_t md32pcm_event_sta;	/* MD32PCM_EVENT_STA */
+	uint32_t wake_misc;		/* SPM_BK_WAKE_MISC */
+	uint32_t timer_out;		/* SPM_BK_PCM_TIMER */
+	uint32_t r13;			/* PCM_REG13_DATA */
+	uint32_t idle_sta;		/* SUBSYS_IDLE_STA */
+	uint32_t req_sta0;		/* SRC_REQ_STA_0 */
+	uint32_t req_sta1;		/* SRC_REQ_STA_1 */
+	uint32_t req_sta2;		/* SRC_REQ_STA_2 */
+	uint32_t req_sta3;		/* SRC_REQ_STA_3 */
+	uint32_t req_sta4;		/* SRC_REQ_STA_4 */
+	uint32_t cg_check_sta;		/* SPM_CG_CHECK_STA */
+	uint32_t debug_flag;		/* PCM_WDT_LATCH_SPARE_0 */
+	uint32_t debug_flag1;		/* PCM_WDT_LATCH_SPARE_1 */
+	uint32_t b_sw_flag0;		/* SPM_SW_RSV_7 */
+	uint32_t b_sw_flag1;		/* SPM_SW_RSV_8 */
+	uint32_t isr;			/* SPM_IRQ_STA */
+	uint32_t sw_flag0;		/* SPM_SW_FLAG_0 */
+	uint32_t sw_flag1;		/* SPM_SW_FLAG_1 */
+	uint32_t clk_settle;		/* SPM_CLK_SETTLE */
+	uint32_t src_req;		/* SPM_SRC_REQ */
+	uint32_t log_index;
+	uint32_t abort;
+	uint32_t rt_req_sta0;		/* SPM_SW_RSV_2 */
+	uint32_t rt_req_sta1;		/* SPM_SW_RSV_3 */
+	uint32_t rt_req_sta2;		/* SPM_SW_RSV_4 */
+	uint32_t rt_req_sta3;		/* SPM_SW_RSV_5 */
+	uint32_t rt_req_sta4;		/* SPM_SW_RSV_6 */
+	uint32_t mcupm_req_sta;
+};
+
+struct spm_lp_scen {
+	struct pcm_desc *pcmdesc;
+	struct pwr_ctrl *pwrctrl;
+};
+
+extern struct spm_lp_scen __spm_vcorefs;
+
+extern void __spm_set_cpu_status(unsigned int cpu);
+extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
+extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
+extern void __spm_init_pcm_register(void);
+extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+				 unsigned int resource_usage);
+extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+extern void __spm_disable_pcm_timer(void);
+extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
+extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+extern void __spm_send_cpu_wakeup_event(void);
+
+extern void __spm_get_wakeup_status(struct wake_status *wakesta,
+				    unsigned int ext_status);
+extern void __spm_clean_after_wakeup(void);
+extern wake_reason_t __spm_output_wake_reason(int state_id,
+					      const struct wake_status *wakesta);
+extern void __spm_set_pcm_wdt(int en);
+extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
+extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
+extern void __spm_ext_int_wakeup_req_clr(void);
+extern void __spm_xo_soc_bblpm(int en);
+
+static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
+					 uint32_t flags)
+{
+	if (pwrctrl->pcm_flags_cust == 0U) {
+		pwrctrl->pcm_flags = flags;
+	} else {
+		pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
+	}
+}
+
+static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
+					  uint32_t flags)
+{
+	if (pwrctrl->pcm_flags1_cust == 0U) {
+		pwrctrl->pcm_flags1 = flags;
+	} else {
+		pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
+	}
+}
+
+extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+	__spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+	__spm_hw_s1_state_monitor(0, status);
+}
+
+#endif /* MT_SPM_INTERNAL_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c
new file mode 100644
index 0000000..849ffb7
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <pmic.h>
+
+/* PMIC_WRAP MT6359 */
+#define NR_PMIC_WRAP_CMD	(NR_IDX_ALL)
+#define SPM_DATA_SHIFT		(16U)
+
+struct pmic_wrap_cmd {
+	unsigned long cmd_addr;
+	unsigned long cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+	enum pmic_wrap_phase_id phase;
+	struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+	struct {
+		struct {
+			unsigned long cmd_addr;
+			unsigned long cmd_wdata;
+		} _[NR_PMIC_WRAP_CMD];
+		const int nr_idx;
+	} set[NR_PMIC_WRAP_PHASE];
+};
+
+struct set_vsram {
+	unsigned long cmd_addr;
+	unsigned long cmd_wdata;
+};
+
+/* MT6366 */
+#define VOLT_TO_PMIC_VAL_66(volt)	(((volt) - 50000 + 625 - 1) / 625)
+#define BUCK_VCORE_ELR0_66		(0x14AA)
+#define TOP_SPI_CON0_66			(0x44C)
+
+static struct pmic_wrap_setting pw66 = {
+	.phase = NR_PMIC_WRAP_PHASE,    /* invalid setting for init */
+	.addr = { {0UL, 0UL} },
+	.set[PMIC_WRAP_PHASE_ALLINONE] = {
+		._[CMD_0] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(80000), },
+		._[CMD_1] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(75000), },
+		._[CMD_2] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(70000), },
+		._[CMD_3] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(65000), },
+		._[CMD_4] = { BUCK_VCORE_ELR0_66, VOLT_TO_PMIC_VAL_66(60000), },
+		._[CMD_5] = { TOP_SPI_CON0_66, 0x1, },
+		._[CMD_6] = { TOP_SPI_CON0_66, 0x0, },
+		.nr_idx = NR_IDX_ALL,
+	},
+};
+
+/* MT6357 */
+#define VOLT_TO_PMIC_VAL_57(volt)	(((volt) - 51875 + 625 - 1) / 625)
+#define BUCK_VCORE_ELR0_57		(0x152A)
+#define TOP_SPI_CON0_57			(0x448)
+
+static struct pmic_wrap_setting pw57 = {
+	.phase = NR_PMIC_WRAP_PHASE,    /* invalid setting for init */
+	.addr = { {0UL, 0UL} },
+	.set[PMIC_WRAP_PHASE_ALLINONE] = {
+		._[CMD_0] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(80000), },
+		._[CMD_1] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(75000), },
+		._[CMD_2] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(70000), },
+		._[CMD_3] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(65000), },
+		._[CMD_4] = { BUCK_VCORE_ELR0_57, VOLT_TO_PMIC_VAL_57(62500), },
+		._[CMD_5] = { TOP_SPI_CON0_57, 0x1, },
+		._[CMD_6] = { TOP_SPI_CON0_57, 0x0, },
+		.nr_idx = NR_IDX_ALL,
+	},
+};
+
+static struct pmic_wrap_setting *pw;
+
+#define IS_PMIC_57() ((pmic_get_hwcid() >> 8) == 0x57)
+
+void _mt_spm_pmic_table_init(void)
+{
+	struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+		{ (uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0, },
+		{ (uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1, },
+		{ (uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2, },
+		{ (uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3, },
+		{ (uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4, },
+		{ (uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5, },
+		{ (uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6, },
+		{ (uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7, },
+		{ (uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8, },
+	};
+
+	if (IS_PMIC_57()) {
+		pw = &pw57;
+	} else {
+		pw = &pw66;
+	}
+
+	memcpy(pw->addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+	uint32_t idx, addr, data;
+
+	if (phase < NR_PMIC_WRAP_PHASE) {
+		if (pw == NULL || pw->addr[0].cmd_addr == 0) {
+			_mt_spm_pmic_table_init();
+		}
+
+		if (pw->phase != phase) {
+			pw->phase = phase;
+
+			mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+			for (idx = 0; idx < pw->set[phase].nr_idx; idx++) {
+				addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+				data = pw->set[phase]._[idx].cmd_wdata;
+				mmio_write_32(pw->addr[idx].cmd_addr, addr | data);
+			}
+		}
+	}
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
+			      uint32_t cmd_wdata)
+{
+	uint32_t addr;
+
+	if (phase >= NR_PMIC_WRAP_PHASE) {
+		return;
+	}
+
+	if (pw == NULL || idx >= pw->set[phase].nr_idx) {
+		return;
+	}
+
+	pw->set[phase]._[idx].cmd_wdata = cmd_wdata;
+
+	mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+	if (pw->phase == phase) {
+		addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+		mmio_write_32(pw->addr[idx].cmd_addr, addr | cmd_wdata);
+	}
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
+{
+	uint64_t ret = 0UL;
+
+	if ((phase < NR_PMIC_WRAP_PHASE) &&
+	    (pw != NULL && idx < pw->set[phase].nr_idx)) {
+		ret = pw->set[phase]._[idx].cmd_wdata;
+	}
+
+	return ret;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.h
new file mode 100644
index 0000000..219b8d3
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_pmic_wrap.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+	PMIC_WRAP_PHASE_ALLINONE	= 0U,
+	NR_PMIC_WRAP_PHASE		= 1U,
+};
+
+/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
+enum {
+	CMD_0		= 0U,        /* 0x0 */
+	CMD_1		= 1U,        /* 0x1 */
+	CMD_2		= 2U,        /* 0x2 */
+	CMD_3		= 3U,        /* 0x3 */
+	CMD_4		= 4U,        /* 0x4 */
+	CMD_5		= 5U,        /* 0x5 */
+	CMD_6		= 6U,        /* 0x6 */
+	CMD_7		= 7U,        /* 0x7 */
+	CMD_8		= 8U,        /* 0x8 */
+	NR_IDX_ALL	= 9U,
+};
+
+/* APIs */
+extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
+				     uint32_t idx, uint32_t cmd_wdata);
+extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
+					 uint32_t idx);
+
+#endif /* MT_SPM_PMIC_WRAP_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_reg.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_reg.h
new file mode 100644
index 0000000..f85ee3b
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_reg.h
@@ -0,0 +1,2957 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_REG
+#define MT_SPM_REG
+
+#include "pcm_def.h"
+#include <platform_def.h>
+#include "sleep_def.h"
+
+/* Define and Declare */
+#define POWERON_CONFIG_EN			(SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0			(SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1			(SPM_BASE + 0x008)
+#define SPM_CLK_CON				(SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE				(SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON			(SPM_BASE + 0x014)
+#define PCM_CON0				(SPM_BASE + 0x018)
+#define PCM_CON1				(SPM_BASE + 0x01C)
+#define SPM_POWER_ON_VAL2			(SPM_BASE + 0x020)
+#define SPM_POWER_ON_VAL3			(SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI			(SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN				(SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL				(SPM_BASE + 0x030)
+#define PCM_WDT_VAL				(SPM_BASE + 0x034)
+#define SPM_SW_RST_CON				(SPM_BASE + 0x040)
+#define SPM_SW_RST_CON_SET			(SPM_BASE + 0x044)
+#define SPM_SW_RST_CON_CLR			(SPM_BASE + 0x048)
+#define SPM_SRC6_MASK				(SPM_BASE + 0x04C)
+#define MD32_CLK_CON				(SPM_BASE + 0x084)
+#define SPM_SRAM_RSV_CON			(SPM_BASE + 0x088)
+#define SPM_SWINT				(SPM_BASE + 0x08C)
+#define SPM_SWINT_SET				(SPM_BASE + 0x090)
+#define SPM_SWINT_CLR				(SPM_BASE + 0x094)
+#define SPM_SCP_MAILBOX				(SPM_BASE + 0x098)
+#define SCP_SPM_MAILBOX				(SPM_BASE + 0x09C)
+#define SPM_WAKEUP_EVENT_SENS			(SPM_BASE + 0x0A0)
+#define SPM_WAKEUP_EVENT_CLEAR			(SPM_BASE + 0x0A4)
+#define SPM_SCP_IRQ				(SPM_BASE + 0x0AC)
+#define SPM_CPU_WAKEUP_EVENT			(SPM_BASE + 0x0B0)
+#define SPM_IRQ_MASK				(SPM_BASE + 0x0B4)
+#define SPM_SRC_REQ				(SPM_BASE + 0x0B8)
+#define SPM_SRC_MASK				(SPM_BASE + 0x0BC)
+#define SPM_SRC2_MASK				(SPM_BASE + 0x0C0)
+#define SPM_SRC3_MASK				(SPM_BASE + 0x0C4)
+#define SPM_SRC4_MASK				(SPM_BASE + 0x0C8)
+#define SPM_SRC5_MASK				(SPM_BASE + 0x0CC)
+#define SPM_WAKEUP_EVENT_MASK			(SPM_BASE + 0x0D0)
+#define SPM_WAKEUP_EVENT_EXT_MASK		(SPM_BASE + 0x0D4)
+#define SPM_SRC7_MASK				(SPM_BASE + 0x0D8)
+#define SCP_CLK_CON				(SPM_BASE + 0x0DC)
+#define PCM_DEBUG_CON				(SPM_BASE + 0x0E0)
+#define DDREN_DBC_CON				(SPM_BASE + 0x0E8)
+#define SPM_RESOURCE_ACK_CON4			(SPM_BASE + 0x0EC)
+#define SPM_RESOURCE_ACK_CON0			(SPM_BASE + 0x0F0)
+#define SPM_RESOURCE_ACK_CON1			(SPM_BASE + 0x0F4)
+#define SPM_RESOURCE_ACK_CON2			(SPM_BASE + 0x0F8)
+#define SPM_RESOURCE_ACK_CON3			(SPM_BASE + 0x0FC)
+#define PCM_REG0_DATA				(SPM_BASE + 0x100)
+#define PCM_REG2_DATA				(SPM_BASE + 0x104)
+#define PCM_REG6_DATA				(SPM_BASE + 0x108)
+#define PCM_REG7_DATA				(SPM_BASE + 0x10C)
+#define PCM_REG13_DATA				(SPM_BASE + 0x110)
+#define SRC_REQ_STA_0				(SPM_BASE + 0x114)
+#define SRC_REQ_STA_1				(SPM_BASE + 0x118)
+#define SRC_REQ_STA_2				(SPM_BASE + 0x11C)
+#define PCM_TIMER_OUT				(SPM_BASE + 0x120)
+#define PCM_WDT_OUT				(SPM_BASE + 0x124)
+#define SPM_IRQ_STA				(SPM_BASE + 0x128)
+#define SRC_REQ_STA_4				(SPM_BASE + 0x12C)
+#define MD32PCM_WAKEUP_STA			(SPM_BASE + 0x130)
+#define MD32PCM_EVENT_STA			(SPM_BASE + 0x134)
+#define SPM_WAKEUP_STA				(SPM_BASE + 0x138)
+#define SPM_WAKEUP_EXT_STA			(SPM_BASE + 0x13C)
+#define SPM_WAKEUP_MISC				(SPM_BASE + 0x140)
+#define MM_DVFS_HALT				(SPM_BASE + 0x144)
+#define BUS_PROTECT_RDY				(SPM_BASE + 0x150)
+#define BUS_PROTECT1_RDY			(SPM_BASE + 0x154)
+#define BUS_PROTECT2_RDY			(SPM_BASE + 0x158)
+#define BUS_PROTECT3_RDY			(SPM_BASE + 0x15C)
+#define SUBSYS_IDLE_STA				(SPM_BASE + 0x160)
+#define PCM_STA					(SPM_BASE + 0x164)
+#define SRC_REQ_STA_3				(SPM_BASE + 0x168)
+#define PWR_STATUS				(SPM_BASE + 0x16C)
+#define PWR_STATUS_2ND				(SPM_BASE + 0x170)
+#define CPU_PWR_STATUS				(SPM_BASE + 0x174)
+#define OTHER_PWR_STATUS			(SPM_BASE + 0x178)
+#define SPM_VTCXO_EVENT_COUNT_STA		(SPM_BASE + 0x17C)
+#define SPM_INFRA_EVENT_COUNT_STA		(SPM_BASE + 0x180)
+#define SPM_VRF18_EVENT_COUNT_STA		(SPM_BASE + 0x184)
+#define SPM_APSRC_EVENT_COUNT_STA		(SPM_BASE + 0x188)
+#define SPM_DDREN_EVENT_COUNT_STA		(SPM_BASE + 0x18C)
+#define MD32PCM_STA				(SPM_BASE + 0x190)
+#define MD32PCM_PC				(SPM_BASE + 0x194)
+#define DVFSRC_EVENT_STA			(SPM_BASE + 0x1A4)
+#define BUS_PROTECT4_RDY			(SPM_BASE + 0x1A8)
+#define BUS_PROTECT5_RDY			(SPM_BASE + 0x1AC)
+#define BUS_PROTECT6_RDY			(SPM_BASE + 0x1B0)
+#define BUS_PROTECT7_RDY			(SPM_BASE + 0x1B4)
+#define BUS_PROTECT8_RDY			(SPM_BASE + 0x1B8)
+#define SPM_TWAM_LAST_STA0			(SPM_BASE + 0x1D0)
+#define SPM_TWAM_LAST_STA1			(SPM_BASE + 0x1D4)
+#define SPM_TWAM_LAST_STA2			(SPM_BASE + 0x1D8)
+#define SPM_TWAM_LAST_STA3			(SPM_BASE + 0x1DC)
+#define SPM_TWAM_CURR_STA0			(SPM_BASE + 0x1E0)
+#define SPM_TWAM_CURR_STA1			(SPM_BASE + 0x1E4)
+#define SPM_TWAM_CURR_STA2			(SPM_BASE + 0x1E8)
+#define SPM_TWAM_CURR_STA3			(SPM_BASE + 0x1EC)
+#define SPM_TWAM_TIMER_OUT			(SPM_BASE + 0x1F0)
+#define SPM_CG_CHECK_STA			(SPM_BASE + 0x1F4)
+#define SPM_DVFS_STA				(SPM_BASE + 0x1F8)
+#define SPM_DVFS_OPP_STA			(SPM_BASE + 0x1FC)
+#define SPM_MCUSYS_PWR_CON			(SPM_BASE + 0x200)
+#define SPM_CPUTOP_PWR_CON			(SPM_BASE + 0x204)
+#define SPM_CPU0_PWR_CON			(SPM_BASE + 0x208)
+#define SPM_CPU1_PWR_CON			(SPM_BASE + 0x20C)
+#define SPM_CPU2_PWR_CON			(SPM_BASE + 0x210)
+#define SPM_CPU3_PWR_CON			(SPM_BASE + 0x214)
+#define SPM_CPU4_PWR_CON			(SPM_BASE + 0x218)
+#define SPM_CPU5_PWR_CON			(SPM_BASE + 0x21C)
+#define SPM_CPU6_PWR_CON			(SPM_BASE + 0x220)
+#define SPM_CPU7_PWR_CON			(SPM_BASE + 0x224)
+#define ARMPLL_CLK_CON				(SPM_BASE + 0x22C)
+#define MCUSYS_IDLE_STA				(SPM_BASE + 0x230)
+#define GIC_WAKEUP_STA				(SPM_BASE + 0x234)
+#define CPU_SPARE_CON				(SPM_BASE + 0x238)
+#define CPU_SPARE_CON_SET			(SPM_BASE + 0x23C)
+#define CPU_SPARE_CON_CLR			(SPM_BASE + 0x240)
+#define ARMPLL_CLK_SEL				(SPM_BASE + 0x244)
+#define EXT_INT_WAKEUP_REQ			(SPM_BASE + 0x248)
+#define EXT_INT_WAKEUP_REQ_SET			(SPM_BASE + 0x24C)
+#define EXT_INT_WAKEUP_REQ_CLR			(SPM_BASE + 0x250)
+#define CPU_IRQ_MASK				(SPM_BASE + 0x260)
+#define CPU_IRQ_MASK_SET			(SPM_BASE + 0x264)
+#define CPU_IRQ_MASK_CLR			(SPM_BASE + 0x268)
+#define CPU_WFI_EN				(SPM_BASE + 0x280)
+#define CPU_WFI_EN_SET				(SPM_BASE + 0x284)
+#define CPU_WFI_EN_CLR				(SPM_BASE + 0x288)
+#define ROOT_CPUTOP_ADDR			(SPM_BASE + 0x2A0)
+#define ROOT_CORE_ADDR				(SPM_BASE + 0x2A4)
+#define SPM2SW_MAILBOX_0			(SPM_BASE + 0x2D0)
+#define SPM2SW_MAILBOX_1			(SPM_BASE + 0x2D4)
+#define SPM2SW_MAILBOX_2			(SPM_BASE + 0x2D8)
+#define SPM2SW_MAILBOX_3			(SPM_BASE + 0x2DC)
+#define SW2SPM_WAKEUP				(SPM_BASE + 0x2E0)
+#define SW2SPM_WAKEUP_SET			(SPM_BASE + 0x2E4)
+#define SW2SPM_WAKEUP_CLR			(SPM_BASE + 0x2E8)
+#define SW2SPM_MAILBOX_0			(SPM_BASE + 0x2EC)
+#define SW2SPM_MAILBOX_1			(SPM_BASE + 0x2F0)
+#define SW2SPM_MAILBOX_2			(SPM_BASE + 0x2F4)
+#define SW2SPM_MAILBOX_3			(SPM_BASE + 0x2F8)
+#define SW2SPM_CFG				(SPM_BASE + 0x2FC)
+#define MD1_PWR_CON				(SPM_BASE + 0x300)
+#define CONN_PWR_CON				(SPM_BASE + 0x304)
+#define MFG0_PWR_CON				(SPM_BASE + 0x308)
+#define MFG1_PWR_CON				(SPM_BASE + 0x30C)
+#define MFG2_PWR_CON				(SPM_BASE + 0x310)
+#define MFG3_PWR_CON				(SPM_BASE + 0x314)
+#define MFG4_PWR_CON				(SPM_BASE + 0x318)
+#define MFG5_PWR_CON				(SPM_BASE + 0x31C)
+#define MFG6_PWR_CON				(SPM_BASE + 0x320)
+#define IFR_PWR_CON				(SPM_BASE + 0x324)
+#define IFR_SUB_PWR_CON				(SPM_BASE + 0x328)
+#define DPY_PWR_CON				(SPM_BASE + 0x32C)
+#define DRAMC_MD32_PWR_CON			(SPM_BASE + 0x330)
+#define ISP_PWR_CON				(SPM_BASE + 0x334)
+#define ISP2_PWR_CON				(SPM_BASE + 0x338)
+#define IPE_PWR_CON				(SPM_BASE + 0x33C)
+#define VDE_PWR_CON				(SPM_BASE + 0x340)
+#define VDE2_PWR_CON				(SPM_BASE + 0x344)
+#define VEN_PWR_CON				(SPM_BASE + 0x348)
+#define VEN_CORE1_PWR_CON			(SPM_BASE + 0x34C)
+#define MDP_PWR_CON				(SPM_BASE + 0x350)
+#define DIS_PWR_CON				(SPM_BASE + 0x354)
+#define AUDIO_PWR_CON				(SPM_BASE + 0x358)
+#define CAM_PWR_CON				(SPM_BASE + 0x35C)
+#define CAM_RAWA_PWR_CON			(SPM_BASE + 0x360)
+#define CAM_RAWB_PWR_CON			(SPM_BASE + 0x364)
+#define CAM_RAWC_PWR_CON			(SPM_BASE + 0x368)
+#define SYSRAM_CON				(SPM_BASE + 0x36C)
+#define SYSROM_CON				(SPM_BASE + 0x370)
+#define SSPM_SRAM_CON				(SPM_BASE + 0x374)
+#define SCP_SRAM_CON				(SPM_BASE + 0x378)
+#define DPY_SHU_SRAM_CON			(SPM_BASE + 0x37C)
+#define UFS_SRAM_CON				(SPM_BASE + 0x380)
+#define DEVAPC_IFR_SRAM_CON			(SPM_BASE + 0x384)
+#define DEVAPC_SUBIFR_SRAM_CON			(SPM_BASE + 0x388)
+#define DEVAPC_ACP_SRAM_CON			(SPM_BASE + 0x38C)
+#define USB_SRAM_CON				(SPM_BASE + 0x390)
+#define DUMMY_SRAM_CON				(SPM_BASE + 0x394)
+#define MD_EXT_BUCK_ISO_CON			(SPM_BASE + 0x398)
+#define EXT_BUCK_ISO				(SPM_BASE + 0x39C)
+#define DXCC_SRAM_CON				(SPM_BASE + 0x3A0)
+#define MSDC_PWR_CON				(SPM_BASE + 0x3A4)
+#define DEBUGTOP_SRAM_CON			(SPM_BASE + 0x3A8)
+#define DP_TX_PWR_CON				(SPM_BASE + 0x3AC)
+#define DPMAIF_SRAM_CON				(SPM_BASE + 0x3B0)
+#define DPY_SHU2_SRAM_CON			(SPM_BASE + 0x3B4)
+#define DRAMC_MCU2_SRAM_CON			(SPM_BASE + 0x3B8)
+#define DRAMC_MCU_SRAM_CON			(SPM_BASE + 0x3BC)
+#define MCUPM_PWR_CON				(SPM_BASE + 0x3C0)
+#define DPY2_PWR_CON				(SPM_BASE + 0x3C4)
+#define SPM_SRAM_CON				(SPM_BASE + 0x3C8)
+#define PERI_PWR_CON				(SPM_BASE + 0x3D0)
+#define NNA0_PWR_CON				(SPM_BASE + 0x3D4)
+#define NNA1_PWR_CON				(SPM_BASE + 0x3D8)
+#define NNA2_PWR_CON				(SPM_BASE + 0x3DC)
+#define NNA_PWR_CON				(SPM_BASE + 0x3E0)
+#define ADSP_PWR_CON				(SPM_BASE + 0x3E4)
+#define DPY_SRAM_CON				(SPM_BASE + 0x3E8)
+#define SPM_MEM_CK_SEL				(SPM_BASE + 0x400)
+#define SPM_BUS_PROTECT_MASK_B			(SPM_BASE + 0x404)
+#define SPM_BUS_PROTECT1_MASK_B			(SPM_BASE + 0x408)
+#define SPM_BUS_PROTECT2_MASK_B			(SPM_BASE + 0x40C)
+#define SPM_BUS_PROTECT3_MASK_B			(SPM_BASE + 0x410)
+#define SPM_BUS_PROTECT4_MASK_B			(SPM_BASE + 0x414)
+#define SPM_EMI_BW_MODE				(SPM_BASE + 0x418)
+#define AP2MD_PEER_WAKEUP			(SPM_BASE + 0x41C)
+#define ULPOSC_CON				(SPM_BASE + 0x420)
+#define SPM2MM_CON				(SPM_BASE + 0x424)
+#define SPM_BUS_PROTECT5_MASK_B			(SPM_BASE + 0x428)
+#define SPM2MCUPM_CON				(SPM_BASE + 0x42C)
+#define AP_MDSRC_REQ				(SPM_BASE + 0x430)
+#define SPM2EMI_ENTER_ULPM			(SPM_BASE + 0x434)
+#define SPM2MD_DVFS_CON				(SPM_BASE + 0x438)
+#define MD2SPM_DVFS_CON				(SPM_BASE + 0x43C)
+#define SPM_BUS_PROTECT6_MASK_B			(SPM_BASE + 0x440)
+#define SPM_BUS_PROTECT7_MASK_B			(SPM_BASE + 0x444)
+#define SPM_BUS_PROTECT8_MASK_B			(SPM_BASE + 0x448)
+#define SPM_PLL_CON				(SPM_BASE + 0x44C)
+#define RC_SPM_CTRL				(SPM_BASE + 0x450)
+#define SPM_DRAM_MCU_SW_CON_0			(SPM_BASE + 0x454)
+#define SPM_DRAM_MCU_SW_CON_1			(SPM_BASE + 0x458)
+#define SPM_DRAM_MCU_SW_CON_2			(SPM_BASE + 0x45C)
+#define SPM_DRAM_MCU_SW_CON_3			(SPM_BASE + 0x460)
+#define SPM_DRAM_MCU_SW_CON_4			(SPM_BASE + 0x464)
+#define SPM_DRAM_MCU_STA_0			(SPM_BASE + 0x468)
+#define SPM_DRAM_MCU_STA_1			(SPM_BASE + 0x46C)
+#define SPM_DRAM_MCU_STA_2			(SPM_BASE + 0x470)
+#define SPM_DRAM_MCU_SW_SEL_0			(SPM_BASE + 0x474)
+#define RELAY_DVFS_LEVEL			(SPM_BASE + 0x478)
+#define DRAMC_DPY_CLK_SW_CON_0			(SPM_BASE + 0x480)
+#define DRAMC_DPY_CLK_SW_CON_1			(SPM_BASE + 0x484)
+#define DRAMC_DPY_CLK_SW_CON_2			(SPM_BASE + 0x488)
+#define DRAMC_DPY_CLK_SW_CON_3			(SPM_BASE + 0x48C)
+#define DRAMC_DPY_CLK_SW_SEL_0			(SPM_BASE + 0x490)
+#define DRAMC_DPY_CLK_SW_SEL_1			(SPM_BASE + 0x494)
+#define DRAMC_DPY_CLK_SW_SEL_2			(SPM_BASE + 0x498)
+#define DRAMC_DPY_CLK_SW_SEL_3			(SPM_BASE + 0x49C)
+#define DRAMC_DPY_CLK_SPM_CON			(SPM_BASE + 0x4A0)
+#define SPM_DVFS_LEVEL				(SPM_BASE + 0x4A4)
+#define SPM_CIRQ_CON				(SPM_BASE + 0x4A8)
+#define SPM_DVFS_MISC				(SPM_BASE + 0x4AC)
+#define RG_MODULE_SW_CG_0_MASK_REQ_0		(SPM_BASE + 0x4B4)
+#define RG_MODULE_SW_CG_0_MASK_REQ_1		(SPM_BASE + 0x4B8)
+#define RG_MODULE_SW_CG_0_MASK_REQ_2		(SPM_BASE + 0x4BC)
+#define RG_MODULE_SW_CG_1_MASK_REQ_0		(SPM_BASE + 0x4C0)
+#define RG_MODULE_SW_CG_1_MASK_REQ_1		(SPM_BASE + 0x4C4)
+#define RG_MODULE_SW_CG_1_MASK_REQ_2		(SPM_BASE + 0x4C8)
+#define RG_MODULE_SW_CG_2_MASK_REQ_0		(SPM_BASE + 0x4CC)
+#define RG_MODULE_SW_CG_2_MASK_REQ_1		(SPM_BASE + 0x4D0)
+#define RG_MODULE_SW_CG_2_MASK_REQ_2		(SPM_BASE + 0x4D4)
+#define RG_MODULE_SW_CG_3_MASK_REQ_0		(SPM_BASE + 0x4D8)
+#define RG_MODULE_SW_CG_3_MASK_REQ_1		(SPM_BASE + 0x4DC)
+#define RG_MODULE_SW_CG_3_MASK_REQ_2		(SPM_BASE + 0x4E0)
+#define PWR_STATUS_MASK_REQ_0			(SPM_BASE + 0x4E4)
+#define PWR_STATUS_MASK_REQ_1			(SPM_BASE + 0x4E8)
+#define PWR_STATUS_MASK_REQ_2			(SPM_BASE + 0x4EC)
+#define SPM_CG_CHECK_CON			(SPM_BASE + 0x4F0)
+#define SPM_SRC_RDY_STA				(SPM_BASE + 0x4F4)
+#define SPM_DVS_DFS_LEVEL			(SPM_BASE + 0x4F8)
+#define SPM_FORCE_DVFS				(SPM_BASE + 0x4FC)
+#define RC_M00_SRCLKEN_CFG			(SPM_BASE + 0x520)
+#define SPM_SW_FLAG_0				(SPM_BASE + 0x600)
+#define SPM_SW_DEBUG_0				(SPM_BASE + 0x604)
+#define SPM_SW_FLAG_1				(SPM_BASE + 0x608)
+#define SPM_SW_DEBUG_1				(SPM_BASE + 0x60C)
+#define SPM_SW_RSV_0				(SPM_BASE + 0x610)
+#define SPM_SW_RSV_1				(SPM_BASE + 0x614)
+#define SPM_SW_RSV_2				(SPM_BASE + 0x618)
+#define SPM_SW_RSV_3				(SPM_BASE + 0x61C)
+#define SPM_SW_RSV_4				(SPM_BASE + 0x620)
+#define SPM_SW_RSV_5				(SPM_BASE + 0x624)
+#define SPM_SW_RSV_6				(SPM_BASE + 0x628)
+#define SPM_SW_RSV_7				(SPM_BASE + 0x62C)
+#define SPM_SW_RSV_8				(SPM_BASE + 0x630)
+#define SPM_BK_WAKE_EVENT			(SPM_BASE + 0x634)
+#define SPM_BK_VTCXO_DUR			(SPM_BASE + 0x638)
+#define SPM_BK_WAKE_MISC			(SPM_BASE + 0x63C)
+#define SPM_BK_PCM_TIMER			(SPM_BASE + 0x640)
+#define SPM_RSV_CON_0				(SPM_BASE + 0x650)
+#define SPM_RSV_CON_1				(SPM_BASE + 0x654)
+#define SPM_RSV_STA_0				(SPM_BASE + 0x658)
+#define SPM_RSV_STA_1				(SPM_BASE + 0x65C)
+#define SPM_SPARE_CON				(SPM_BASE + 0x660)
+#define SPM_SPARE_CON_SET			(SPM_BASE + 0x664)
+#define SPM_SPARE_CON_CLR			(SPM_BASE + 0x668)
+#define SPM_CROSS_WAKE_M00_REQ			(SPM_BASE + 0x66C)
+#define SPM_CROSS_WAKE_M01_REQ			(SPM_BASE + 0x670)
+#define SPM_CROSS_WAKE_M02_REQ			(SPM_BASE + 0x674)
+#define SPM_CROSS_WAKE_M03_REQ			(SPM_BASE + 0x678)
+#define SCP_VCORE_LEVEL				(SPM_BASE + 0x67C)
+#define SC_MM_CK_SEL_CON			(SPM_BASE + 0x680)
+#define SPARE_ACK_MASK				(SPM_BASE + 0x684)
+#define SPM_SPARE_FUNCTION			(SPM_BASE + 0x688)
+#define SPM_DV_CON_0				(SPM_BASE + 0x68C)
+#define SPM_DV_CON_1				(SPM_BASE + 0x690)
+#define SPM_DV_STA				(SPM_BASE + 0x694)
+#define CONN_XOWCN_DEBUG_EN			(SPM_BASE + 0x698)
+#define SPM_SEMA_M0				(SPM_BASE + 0x69C)
+#define SPM_SEMA_M1				(SPM_BASE + 0x6A0)
+#define SPM_SEMA_M2				(SPM_BASE + 0x6A4)
+#define SPM_SEMA_M3				(SPM_BASE + 0x6A8)
+#define SPM_SEMA_M4				(SPM_BASE + 0x6AC)
+#define SPM_SEMA_M5				(SPM_BASE + 0x6B0)
+#define SPM_SEMA_M6				(SPM_BASE + 0x6B4)
+#define SPM_SEMA_M7				(SPM_BASE + 0x6B8)
+#define SPM2ADSP_MAILBOX			(SPM_BASE + 0x6BC)
+#define ADSP2SPM_MAILBOX			(SPM_BASE + 0x6C0)
+#define SPM_ADSP_IRQ				(SPM_BASE + 0x6C4)
+#define SPM_MD32_IRQ				(SPM_BASE + 0x6C8)
+#define SPM2PMCU_MAILBOX_0			(SPM_BASE + 0x6CC)
+#define SPM2PMCU_MAILBOX_1			(SPM_BASE + 0x6D0)
+#define SPM2PMCU_MAILBOX_2			(SPM_BASE + 0x6D4)
+#define SPM2PMCU_MAILBOX_3			(SPM_BASE + 0x6D8)
+#define PMCU2SPM_MAILBOX_0			(SPM_BASE + 0x6DC)
+#define PMCU2SPM_MAILBOX_1			(SPM_BASE + 0x6E0)
+#define PMCU2SPM_MAILBOX_2			(SPM_BASE + 0x6E4)
+#define PMCU2SPM_MAILBOX_3			(SPM_BASE + 0x6E8)
+#define UFS_PSRI_SW				(SPM_BASE + 0x6EC)
+#define UFS_PSRI_SW_SET				(SPM_BASE + 0x6F0)
+#define UFS_PSRI_SW_CLR				(SPM_BASE + 0x6F4)
+#define SPM_AP_SEMA				(SPM_BASE + 0x6F8)
+#define SPM_SPM_SEMA				(SPM_BASE + 0x6FC)
+#define SPM_DVFS_CON				(SPM_BASE + 0x700)
+#define SPM_DVFS_CON_STA			(SPM_BASE + 0x704)
+#define SPM_PMIC_SPMI_CON			(SPM_BASE + 0x708)
+#define SPM_DVFS_CMD0				(SPM_BASE + 0x710)
+#define SPM_DVFS_CMD1				(SPM_BASE + 0x714)
+#define SPM_DVFS_CMD2				(SPM_BASE + 0x718)
+#define SPM_DVFS_CMD3				(SPM_BASE + 0x71C)
+#define SPM_DVFS_CMD4				(SPM_BASE + 0x720)
+#define SPM_DVFS_CMD5				(SPM_BASE + 0x724)
+#define SPM_DVFS_CMD6				(SPM_BASE + 0x728)
+#define SPM_DVFS_CMD7				(SPM_BASE + 0x72C)
+#define SPM_DVFS_CMD8				(SPM_BASE + 0x730)
+#define SPM_DVFS_CMD9				(SPM_BASE + 0x734)
+#define SPM_DVFS_CMD10				(SPM_BASE + 0x738)
+#define SPM_DVFS_CMD11				(SPM_BASE + 0x73C)
+#define SPM_DVFS_CMD12				(SPM_BASE + 0x740)
+#define SPM_DVFS_CMD13				(SPM_BASE + 0x744)
+#define SPM_DVFS_CMD14				(SPM_BASE + 0x748)
+#define SPM_DVFS_CMD15				(SPM_BASE + 0x74C)
+#define SPM_DVFS_CMD16				(SPM_BASE + 0x750)
+#define SPM_DVFS_CMD17				(SPM_BASE + 0x754)
+#define SPM_DVFS_CMD18				(SPM_BASE + 0x758)
+#define SPM_DVFS_CMD19				(SPM_BASE + 0x75C)
+#define SPM_DVFS_CMD20				(SPM_BASE + 0x760)
+#define SPM_DVFS_CMD21				(SPM_BASE + 0x764)
+#define SPM_DVFS_CMD22				(SPM_BASE + 0x768)
+#define SPM_DVFS_CMD23				(SPM_BASE + 0x76C)
+#define SYS_TIMER_VALUE_L			(SPM_BASE + 0x770)
+#define SYS_TIMER_VALUE_H			(SPM_BASE + 0x774)
+#define SYS_TIMER_START_L			(SPM_BASE + 0x778)
+#define SYS_TIMER_START_H			(SPM_BASE + 0x77C)
+#define SYS_TIMER_LATCH_L_00			(SPM_BASE + 0x780)
+#define SYS_TIMER_LATCH_H_00			(SPM_BASE + 0x784)
+#define SYS_TIMER_LATCH_L_01			(SPM_BASE + 0x788)
+#define SYS_TIMER_LATCH_H_01			(SPM_BASE + 0x78C)
+#define SYS_TIMER_LATCH_L_02			(SPM_BASE + 0x790)
+#define SYS_TIMER_LATCH_H_02			(SPM_BASE + 0x794)
+#define SYS_TIMER_LATCH_L_03			(SPM_BASE + 0x798)
+#define SYS_TIMER_LATCH_H_03			(SPM_BASE + 0x79C)
+#define SYS_TIMER_LATCH_L_04			(SPM_BASE + 0x7A0)
+#define SYS_TIMER_LATCH_H_04			(SPM_BASE + 0x7A4)
+#define SYS_TIMER_LATCH_L_05			(SPM_BASE + 0x7A8)
+#define SYS_TIMER_LATCH_H_05			(SPM_BASE + 0x7AC)
+#define SYS_TIMER_LATCH_L_06			(SPM_BASE + 0x7B0)
+#define SYS_TIMER_LATCH_H_06			(SPM_BASE + 0x7B4)
+#define SYS_TIMER_LATCH_L_07			(SPM_BASE + 0x7B8)
+#define SYS_TIMER_LATCH_H_07			(SPM_BASE + 0x7BC)
+#define SYS_TIMER_LATCH_L_08			(SPM_BASE + 0x7C0)
+#define SYS_TIMER_LATCH_H_08			(SPM_BASE + 0x7C4)
+#define SYS_TIMER_LATCH_L_09			(SPM_BASE + 0x7C8)
+#define SYS_TIMER_LATCH_H_09			(SPM_BASE + 0x7CC)
+#define SYS_TIMER_LATCH_L_10			(SPM_BASE + 0x7D0)
+#define SYS_TIMER_LATCH_H_10			(SPM_BASE + 0x7D4)
+#define SYS_TIMER_LATCH_L_11			(SPM_BASE + 0x7D8)
+#define SYS_TIMER_LATCH_H_11			(SPM_BASE + 0x7DC)
+#define SYS_TIMER_LATCH_L_12			(SPM_BASE + 0x7E0)
+#define SYS_TIMER_LATCH_H_12			(SPM_BASE + 0x7E4)
+#define SYS_TIMER_LATCH_L_13			(SPM_BASE + 0x7E8)
+#define SYS_TIMER_LATCH_H_13			(SPM_BASE + 0x7EC)
+#define SYS_TIMER_LATCH_L_14			(SPM_BASE + 0x7F0)
+#define SYS_TIMER_LATCH_H_14			(SPM_BASE + 0x7F4)
+#define SYS_TIMER_LATCH_L_15			(SPM_BASE + 0x7F8)
+#define SYS_TIMER_LATCH_H_15			(SPM_BASE + 0x7FC)
+#define PCM_WDT_LATCH_0				(SPM_BASE + 0x800)
+#define PCM_WDT_LATCH_1				(SPM_BASE + 0x804)
+#define PCM_WDT_LATCH_2				(SPM_BASE + 0x808)
+#define PCM_WDT_LATCH_3				(SPM_BASE + 0x80C)
+#define PCM_WDT_LATCH_4				(SPM_BASE + 0x810)
+#define PCM_WDT_LATCH_5				(SPM_BASE + 0x814)
+#define PCM_WDT_LATCH_6				(SPM_BASE + 0x818)
+#define PCM_WDT_LATCH_7				(SPM_BASE + 0x81C)
+#define PCM_WDT_LATCH_8				(SPM_BASE + 0x820)
+#define PCM_WDT_LATCH_9				(SPM_BASE + 0x824)
+#define PCM_WDT_LATCH_10			(SPM_BASE + 0x828)
+#define PCM_WDT_LATCH_11			(SPM_BASE + 0x82C)
+#define PCM_WDT_LATCH_12			(SPM_BASE + 0x830)
+#define PCM_WDT_LATCH_13			(SPM_BASE + 0x834)
+#define PCM_WDT_LATCH_14			(SPM_BASE + 0x838)
+#define PCM_WDT_LATCH_15			(SPM_BASE + 0x83C)
+#define PCM_WDT_LATCH_16			(SPM_BASE + 0x840)
+#define PCM_WDT_LATCH_17			(SPM_BASE + 0x844)
+#define PCM_WDT_LATCH_18			(SPM_BASE + 0x848)
+#define PCM_WDT_LATCH_SPARE_0			(SPM_BASE + 0x84C)
+#define PCM_WDT_LATCH_SPARE_1			(SPM_BASE + 0x850)
+#define PCM_WDT_LATCH_SPARE_2			(SPM_BASE + 0x854)
+#define PCM_WDT_LATCH_CONN_0			(SPM_BASE + 0x870)
+#define PCM_WDT_LATCH_CONN_1			(SPM_BASE + 0x874)
+#define PCM_WDT_LATCH_CONN_2			(SPM_BASE + 0x878)
+#define DRAMC_GATING_ERR_LATCH_CH0_0		(SPM_BASE + 0x8A0)
+#define DRAMC_GATING_ERR_LATCH_CH0_1		(SPM_BASE + 0x8A4)
+#define DRAMC_GATING_ERR_LATCH_CH0_2		(SPM_BASE + 0x8A8)
+#define DRAMC_GATING_ERR_LATCH_CH0_3		(SPM_BASE + 0x8AC)
+#define DRAMC_GATING_ERR_LATCH_CH0_4		(SPM_BASE + 0x8B0)
+#define DRAMC_GATING_ERR_LATCH_CH0_5		(SPM_BASE + 0x8B4)
+#define DRAMC_GATING_ERR_LATCH_CH0_6		(SPM_BASE + 0x8B8)
+#define DRAMC_GATING_ERR_LATCH_SPARE_0		(SPM_BASE + 0x8F4)
+#define SPM_ACK_CHK_CON_0			(SPM_BASE + 0x900)
+#define SPM_ACK_CHK_PC_0			(SPM_BASE + 0x904)
+#define SPM_ACK_CHK_SEL_0			(SPM_BASE + 0x908)
+#define SPM_ACK_CHK_TIMER_0			(SPM_BASE + 0x90C)
+#define SPM_ACK_CHK_STA_0			(SPM_BASE + 0x910)
+#define SPM_ACK_CHK_SWINT_0			(SPM_BASE + 0x914)
+#define SPM_ACK_CHK_CON_1			(SPM_BASE + 0x918)
+#define SPM_ACK_CHK_PC_1			(SPM_BASE + 0x91C)
+#define SPM_ACK_CHK_SEL_1			(SPM_BASE + 0x920)
+#define SPM_ACK_CHK_TIMER_1			(SPM_BASE + 0x924)
+#define SPM_ACK_CHK_STA_1			(SPM_BASE + 0x928)
+#define SPM_ACK_CHK_SWINT_1			(SPM_BASE + 0x92C)
+#define SPM_ACK_CHK_CON_2			(SPM_BASE + 0x930)
+#define SPM_ACK_CHK_PC_2			(SPM_BASE + 0x934)
+#define SPM_ACK_CHK_SEL_2			(SPM_BASE + 0x938)
+#define SPM_ACK_CHK_TIMER_2			(SPM_BASE + 0x93C)
+#define SPM_ACK_CHK_STA_2			(SPM_BASE + 0x940)
+#define SPM_ACK_CHK_SWINT_2			(SPM_BASE + 0x944)
+#define SPM_ACK_CHK_CON_3			(SPM_BASE + 0x948)
+#define SPM_ACK_CHK_PC_3			(SPM_BASE + 0x94C)
+#define SPM_ACK_CHK_SEL_3			(SPM_BASE + 0x950)
+#define SPM_ACK_CHK_TIMER_3			(SPM_BASE + 0x954)
+#define SPM_ACK_CHK_STA_3			(SPM_BASE + 0x958)
+#define SPM_ACK_CHK_SWINT_3			(SPM_BASE + 0x95C)
+#define SPM_COUNTER_0				(SPM_BASE + 0x960)
+#define SPM_COUNTER_1				(SPM_BASE + 0x964)
+#define SPM_COUNTER_2				(SPM_BASE + 0x968)
+#define SYS_TIMER_CON				(SPM_BASE + 0x96C)
+#define SPM_TWAM_CON				(SPM_BASE + 0x970)
+#define SPM_TWAM_WINDOW_LEN			(SPM_BASE + 0x974)
+#define SPM_TWAM_IDLE_SEL			(SPM_BASE + 0x978)
+#define SPM_TWAM_EVENT_CLEAR			(SPM_BASE + 0x97C)
+#define OPP0_TABLE				(SPM_BASE + 0x980)
+#define OPP1_TABLE				(SPM_BASE + 0x984)
+#define OPP2_TABLE				(SPM_BASE + 0x988)
+#define OPP3_TABLE				(SPM_BASE + 0x98C)
+#define OPP4_TABLE				(SPM_BASE + 0x990)
+#define OPP5_TABLE				(SPM_BASE + 0x994)
+#define OPP6_TABLE				(SPM_BASE + 0x998)
+#define OPP7_TABLE				(SPM_BASE + 0x99C)
+#define OPP8_TABLE				(SPM_BASE + 0x9A0)
+#define OPP9_TABLE				(SPM_BASE + 0x9A4)
+#define OPP10_TABLE				(SPM_BASE + 0x9A8)
+#define OPP11_TABLE				(SPM_BASE + 0x9AC)
+#define OPP12_TABLE				(SPM_BASE + 0x9B0)
+#define OPP13_TABLE				(SPM_BASE + 0x9B4)
+#define OPP14_TABLE				(SPM_BASE + 0x9B8)
+#define OPP15_TABLE				(SPM_BASE + 0x9BC)
+#define OPP16_TABLE				(SPM_BASE + 0x9C0)
+#define OPP17_TABLE				(SPM_BASE + 0x9C4)
+#define SHU0_ARRAY				(SPM_BASE + 0x9C8)
+#define SHU1_ARRAY				(SPM_BASE + 0x9CC)
+#define SHU2_ARRAY				(SPM_BASE + 0x9D0)
+#define SHU3_ARRAY				(SPM_BASE + 0x9D4)
+#define SHU4_ARRAY				(SPM_BASE + 0x9D8)
+#define SHU5_ARRAY				(SPM_BASE + 0x9DC)
+#define SHU6_ARRAY				(SPM_BASE + 0x9E0)
+#define SHU7_ARRAY				(SPM_BASE + 0x9E4)
+#define SHU8_ARRAY				(SPM_BASE + 0x9E8)
+#define SHU9_ARRAY				(SPM_BASE + 0x9EC)
+
+/* POWERON_CONFIG_EN (0x10006000 + 0x000) */
+#define BCLK_CG_EN_LSB				(1U << 0)	/* 1b */
+#define PROJECT_CODE_LSB			(1U << 16)	/* 16b */
+
+/* SPM_POWER_ON_VAL0 (0x10006000 + 0x004) */
+#define POWER_ON_VAL0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_POWER_ON_VAL1 (0x10006000 + 0x008) */
+#define POWER_ON_VAL1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_CLK_CON (0x10006000 + 0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB			(1U << 0)	/* 2b */
+#define REG_SRCCLKEN1_CTL_LSB			(1U << 2)	/* 2b */
+#define RC_SW_SRCCLKEN_RC			(1U << 3)	/* 1b */
+#define RC_SW_SRCCLKEN_FPM			(1U << 4)	/* 1b */
+#define SYS_SETTLE_SEL_LSB			(1U << 4)	/* 1b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB		(1U << 5)	/* 1b */
+#define REG_SRCCLKEN_MASK_LSB			(1U << 6)	/* 3b */
+#define REG_MD1_C32RM_EN_LSB			(1U << 9)	/* 1b */
+#define REG_MD2_C32RM_EN_LSB			(1U << 10)	/* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB			(1U << 11)	/* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB			(1U << 12)	/* 1b */
+#define REG_SRCCLKEN0_EN_LSB			(1U << 13)	/* 1b */
+#define REG_SRCCLKEN1_EN_LSB			(1U << 14)	/* 1b */
+#define SCP_DCM_EN_LSB				(1U << 15)	/* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB		(1U << 16)	/* 8b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB		(1U << 24)	/* 8b */
+
+/* SPM_CLK_SETTLE (0x10006000 + 0x010) */
+#define SYSCLK_SETTLE_LSB			(1U << 0)	/* 28b */
+
+/* SPM_AP_STANDBY_CON (0x10006000 + 0x014) */
+#define REG_WFI_OP_LSB				(1U << 0)	/* 1b */
+#define REG_WFI_TYPE_LSB			(1U << 1)	/* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB		(1U << 4)	/* 1b */
+#define REG_MD_APSRC_1_SEL_LSB			(1U << 25)	/* 1b */
+#define REG_MD_APSRC_0_SEL_LSB			(1U << 26)	/* 1b */
+#define REG_CONN_APSRC_SEL_LSB			(1U << 29)	/* 1b */
+
+/* PCM_CON0 (0x10006000 + 0x018) */
+#define PCM_CK_EN_LSB				(1U << 2)	/* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB			(1U << 3)	/* 1b */
+#define PCM_CK_FROM_CKSYS_LSB			(1U << 4)	/* 1b */
+#define PCM_SW_RESET_LSB			(1U << 15)	/* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB		(1U << 16)	/* 16b */
+
+/* PCM_CON1 (0x10006000 + 0x01C) */
+#define REG_IM_SLEEP_EN_LSB			(1U << 1)	/* 1b */
+#define REG_SPM_SRAM_CTRL_MUX_LSB		(1U << 2)	/* 1b */
+#define RG_AHBMIF_APBEN_LSB			(1U << 3)	/* 1b */
+#define RG_PCM_TIMER_EN_LSB			(1U << 5)	/* 1b */
+#define REG_SPM_EVENT_COUNTER_CLR_LSB		(1U << 6)	/* 1b */
+#define RG_DIS_MIF_PROT_LSB			(1U << 7)	/* 1b */
+#define RG_PCM_WDT_EN_LSB			(1U << 8)	/* 1b */
+#define RG_PCM_WDT_WAKE_LSB			(1U << 9)	/* 1b */
+#define SPM_LEAVE_SUSPEND_MERGE_MASK_LSB	(1U << 10)	/* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB		(1U << 13)	/* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB		(1U << 14)	/* 1b */
+#define RG_PCM_IRQ_MSK_LSB			(1U << 15)	/* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB		(1U << 16)	/* 16b */
+
+/* SPM_POWER_ON_VAL2 (0x10006000 + 0x020) */
+#define POWER_ON_VAL2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_POWER_ON_VAL3 (0x10006000 + 0x024) */
+#define POWER_ON_VAL3_LSB			(1U << 0)	/* 32b */
+
+/* PCM_REG_DATA_INI (0x10006000 + 0x028) */
+#define PCM_REG_DATA_INI_LSB			(1U << 0)	/* 32b */
+
+/* PCM_PWR_IO_EN (0x10006000 + 0x02C) */
+#define PCM_PWR_IO_EN_LSB			(1U << 0)	/* 8b */
+#define RG_RF_SYNC_EN_LSB			(1U << 16)	/* 8b */
+
+/* PCM_TIMER_VAL (0x10006000 + 0x030) */
+#define REG_PCM_TIMER_VAL_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_VAL (0x10006000 + 0x034) */
+#define RG_PCM_WDT_VAL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RST_CON (0x10006000 + 0x040) */
+#define SPM_SW_RST_CON_LSB			(1U << 0)	/* 16b */
+#define SPM_SW_RST_CON_PROJECT_CODE_LSB		(1U << 16)	/* 16b */
+
+/* SPM_SW_RST_CON_SET (0x10006000 + 0x044) */
+#define SPM_SW_RST_CON_SET_LSB			(1U << 0)	/* 16b */
+#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB	(1U << 16)	/* 16b */
+
+/* SPM_SW_RST_CON_CLR (0x10006000 + 0x048) */
+#define SPM_SW_RST_CON_CLR_LSB			(1U << 0)	/* 16b */
+#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB	(1U << 16)	/* 16b */
+
+/* SPM_SRC6_MASK (0x10006000 + 0x04C) */
+#define REG_CCIF_EVENT_INFRA_REQ_MASK_B_LSB	(1U << 0)	/* 16b */
+#define REG_CCIF_EVENT_APSRC_REQ_MASK_B_LSB	(1U << 16)	/* 16b */
+
+/* MD32_CLK_CON (0x10006000 + 0x084) */
+#define REG_MD32_26M_CK_SEL_LSB			(1U << 0)	/* 1b */
+#define REG_MD32_DCM_EN_LSB			(1U << 1)	/* 1b */
+
+/* SPM_SRAM_RSV_CON (0x10006000 + 0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB		(1U << 0)	/* 1b */
+
+/* SPM_SWINT (0x10006000 + 0x08C) */
+#define SPM_SWINT_LSB				(1U << 0)	/* 32b */
+
+/* SPM_SWINT_SET (0x10006000 + 0x090) */
+#define SPM_SWINT_SET_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SWINT_CLR (0x10006000 + 0x094) */
+#define SPM_SWINT_CLR_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SCP_MAILBOX (0x10006000 + 0x098) */
+#define SPM_SCP_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* SCP_SPM_MAILBOX (0x10006000 + 0x09C) */
+#define SCP_SPM_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EVENT_SENS (0x10006000 + 0x0A0) */
+#define REG_WAKEUP_EVENT_SENS_LSB		(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EVENT_CLEAR (0x10006000 + 0x0A4) */
+#define REG_WAKEUP_EVENT_CLR_LSB		(1U << 0)	/* 32b */
+
+/* SPM_SCP_IRQ (0x10006000 + 0x0AC) */
+#define SC_SPM2SCP_WAKEUP_LSB			(1U << 0)	/* 1b */
+#define SC_SCP2SPM_WAKEUP_LSB			(1U << 4)	/* 1b */
+
+/* SPM_CPU_WAKEUP_EVENT (0x10006000 + 0x0B0) */
+#define REG_CPU_WAKEUP_LSB			(1U << 0)	/* 1b */
+
+/* SPM_IRQ_MASK (0x10006000 + 0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SRC_REQ (0x10006000 + 0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB			(1U << 0)	/* 1b */
+#define REG_SPM_F26M_REQ_LSB			(1U << 1)	/* 1b */
+#define REG_SPM_INFRA_REQ_LSB			(1U << 3)	/* 1b */
+#define REG_SPM_VRF18_REQ_LSB			(1U << 4)	/* 1b */
+#define REG_SPM_DDREN_REQ_LSB			(1U << 7)	/* 1b */
+#define REG_SPM_DVFS_REQ_LSB			(1U << 8)	/* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB		(1U << 9)	/* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB		(1U << 10)	/* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB		(1U << 11)	/* 1b */
+#define REG_SPM_SCP_MAILBOX_REQ_LSB		(1U << 12)	/* 1b */
+
+/* SPM_SRC_MASK (0x10006000 + 0x0BC) */
+#define REG_MD_0_SRCCLKENA_MASK_B_LSB		(1U << 0)	/* 1b */
+#define REG_MD_0_INFRA_REQ_MASK_B_LSB		(1U << 1)	/* 1b */
+#define REG_MD_0_APSRC_REQ_MASK_B_LSB		(1U << 2)	/* 1b */
+#define REG_MD_0_VRF18_REQ_MASK_B_LSB		(1U << 3)	/* 1b */
+#define REG_MD_0_DDREN_REQ_MASK_B_LSB		(1U << 4)	/* 1b */
+#define REG_MD_1_SRCCLKENA_MASK_B_LSB		(1U << 5)	/* 1b */
+#define REG_MD_1_INFRA_REQ_MASK_B_LSB		(1U << 6)	/* 1b */
+#define REG_MD_1_APSRC_REQ_MASK_B_LSB		(1U << 7)	/* 1b */
+#define REG_MD_1_VRF18_REQ_MASK_B_LSB		(1U << 8)	/* 1b */
+#define REG_MD_1_DDREN_REQ_MASK_B_LSB		(1U << 9)	/* 1b */
+#define REG_CONN_SRCCLKENA_MASK_B_LSB		(1U << 10)	/* 1b */
+#define REG_CONN_SRCCLKENB_MASK_B_LSB		(1U << 11)	/* 1b */
+#define REG_CONN_INFRA_REQ_MASK_B_LSB		(1U << 12)	/* 1b */
+#define REG_CONN_APSRC_REQ_MASK_B_LSB		(1U << 13)	/* 1b */
+#define REG_CONN_VRF18_REQ_MASK_B_LSB		(1U << 14)	/* 1b */
+#define REG_CONN_DDREN_REQ_MASK_B_LSB		(1U << 15)	/* 1b */
+#define REG_CONN_VFE28_MASK_B_LSB		(1U << 16)	/* 1b */
+#define REG_SRCCLKENI_SRCCLKENA_MASK_B_LSB	(1U << 17)	/* 3b */
+#define REG_SRCCLKENI_INFRA_REQ_MASK_B_LSB	(1U << 20)	/* 3b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB	(1U << 25)	/* 1b */
+#define REG_INFRASYS_DDREN_REQ_MASK_B_LSB	(1U << 26)	/* 1b */
+#define REG_SSPM_SRCCLKENA_MASK_B_LSB		(1U << 27)	/* 1b */
+#define REG_SSPM_INFRA_REQ_MASK_B_LSB		(1U << 28)	/* 1b */
+#define REG_SSPM_APSRC_REQ_MASK_B_LSB		(1U << 29)	/* 1b */
+#define REG_SSPM_VRF18_REQ_MASK_B_LSB		(1U << 30)	/* 1b */
+#define REG_SSPM_DDREN_REQ_MASK_B_LSB		(1U << 31)	/* 1b */
+
+/* SPM_SRC2_MASK (0x10006000 + 0x0C0) */
+#define REG_SCP_SRCCLKENA_MASK_B_LSB		(1U << 0)	/* 1b */
+#define REG_SCP_INFRA_REQ_MASK_B_LSB		(1U << 1)	/* 1b */
+#define REG_SCP_APSRC_REQ_MASK_B_LSB		(1U << 2)	/* 1b */
+#define REG_SCP_VRF18_REQ_MASK_B_LSB		(1U << 3)	/* 1b */
+#define REG_SCP_DDREN_REQ_MASK_B_LSB		(1U << 4)	/* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB	(1U << 5)	/* 1b */
+#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB	(1U << 6)	/* 1b */
+#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB	(1U << 7)	/* 1b */
+#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB	(1U << 8)	/* 1b */
+#define REG_AUDIO_DSP_DDREN_REQ_MASK_B_LSB	(1U << 9)	/* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB		(1U << 10)	/* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB		(1U << 11)	/* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB		(1U << 12)	/* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB		(1U << 13)	/* 1b */
+#define REG_UFS_DDREN_REQ_MASK_B_LSB		(1U << 14)	/* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB		(1U << 15)	/* 1b */
+#define REG_DISP0_DDREN_REQ_MASK_B_LSB		(1U << 16)	/* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB		(1U << 17)	/* 1b */
+#define REG_DISP1_DDREN_REQ_MASK_B_LSB		(1U << 18)	/* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB		(1U << 19)	/* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB		(1U << 20)	/* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB		(1U << 21)	/* 1b */
+#define REG_GCE_DDREN_REQ_MASK_B_LSB		(1U << 22)	/* 1b */
+#define REG_APU_SRCCLKENA_MASK_B_LSB		(1U << 23)	/* 1b */
+#define REG_APU_INFRA_REQ_MASK_B_LSB		(1U << 24)	/* 1b */
+#define REG_APU_APSRC_REQ_MASK_B_LSB		(1U << 25)	/* 1b */
+#define REG_APU_VRF18_REQ_MASK_B_LSB		(1U << 26)	/* 1b */
+#define REG_APU_DDREN_REQ_MASK_B_LSB		(1U << 27)	/* 1b */
+#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB	(1U << 28)	/* 1b */
+#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB	(1U << 29)	/* 1b */
+#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB	(1U << 30)	/* 1b */
+#define REG_CG_CHECK_DDREN_REQ_MASK_B_LSB	(1U << 31)	/* 1b */
+
+/* SPM_SRC3_MASK (0x10006000 + 0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB	(1U << 0)	/* 1b */
+#define REG_SW2SPM_WAKEUP_MASK_B_LSB		(1U << 1)	/* 4b */
+#define REG_ADSP2SPM_WAKEUP_MASK_B_LSB		(1U << 5)	/* 1b */
+#define REG_SSPM2SPM_WAKEUP_MASK_B_LSB		(1U << 6)	/* 4b */
+#define REG_SCP2SPM_WAKEUP_MASK_B_LSB		(1U << 10)	/* 1b */
+#define REG_CSYSPWRUP_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_SPM_RESERVED_SRCCLKENA_MASK_B_LSB	(1U << 12)	/* 1b */
+#define REG_SPM_RESERVED_INFRA_REQ_MASK_B_LSB	(1U << 13)	/* 1b */
+#define REG_SPM_RESERVED_APSRC_REQ_MASK_B_LSB	(1U << 14)	/* 1b */
+#define REG_SPM_RESERVED_VRF18_REQ_MASK_B_LSB	(1U << 15)	/* 1b */
+#define REG_SPM_RESERVED_DDREN_REQ_MASK_B_LSB	(1U << 16)	/* 1b */
+#define REG_MCUPM_SRCCLKENA_MASK_B_LSB		(1U << 17)	/* 1b */
+#define REG_MCUPM_INFRA_REQ_MASK_B_LSB		(1U << 18)	/* 1b */
+#define REG_MCUPM_APSRC_REQ_MASK_B_LSB		(1U << 19)	/* 1b */
+#define REG_MCUPM_VRF18_REQ_MASK_B_LSB		(1U << 20)	/* 1b */
+#define REG_MCUPM_DDREN_REQ_MASK_B_LSB		(1U << 21)	/* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB		(1U << 22)	/* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB		(1U << 23)	/* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB		(1U << 24)	/* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB		(1U << 25)	/* 1b */
+#define REG_MSDC0_DDREN_REQ_MASK_B_LSB		(1U << 26)	/* 1b */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB		(1U << 27)	/* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB		(1U << 28)	/* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB		(1U << 29)	/* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB		(1U << 30)	/* 1b */
+#define REG_MSDC1_DDREN_REQ_MASK_B_LSB		(1U << 31)	/* 1b */
+
+/* SPM_SRC4_MASK (0x10006000 + 0x0C8) */
+#define REG_CCIF_EVENT_SRCCLKENA_MASK_B_LSB	(1U << 0)	/* 16b */
+#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB	(1U << 16)	/* 1b */
+#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB	(1U << 17)	/* 1b */
+#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB	(1U << 18)	/* 1b */
+#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB	(1U << 19)	/* 1b */
+#define REG_BAK_PSRI_DDREN_REQ_MASK_B_LSB	(1U << 20)	/* 1b */
+#define REG_DRAMC_MD32_INFRA_REQ_MASK_B_LSB	(1U << 21)	/* 2b */
+#define REG_DRAMC_MD32_VRF18_REQ_MASK_B_LSB	(1U << 23)	/* 2b */
+#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB	(1U << 25)	/* 1b */
+#define REG_DRAMC_MD32_APSRC_REQ_MASK_B_LSB	(1U << 26)	/* 2b */
+
+/* SPM_SRC5_MASK (0x10006000 + 0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB	(1U << 0)	/* 9b */
+#define REG_MCUSYS_MERGE_DDREN_REQ_MASK_B_LSB	(1U << 9)	/* 9b */
+#define REG_AFE_SRCCLKENA_MASK_B_LSB		(1U << 18)	/* 1b */
+#define REG_AFE_INFRA_REQ_MASK_B_LSB		(1U << 19)	/* 1b */
+#define REG_AFE_APSRC_REQ_MASK_B_LSB		(1U << 20)	/* 1b */
+#define REG_AFE_VRF18_REQ_MASK_B_LSB		(1U << 21)	/* 1b */
+#define REG_AFE_DDREN_REQ_MASK_B_LSB		(1U << 22)	/* 1b */
+#define REG_MSDC2_SRCCLKENA_MASK_B_LSB		(1U << 23)	/* 1b */
+#define REG_MSDC2_INFRA_REQ_MASK_B_LSB		(1U << 24)	/* 1b */
+#define REG_MSDC2_APSRC_REQ_MASK_B_LSB		(1U << 25)	/* 1b */
+#define REG_MSDC2_VRF18_REQ_MASK_B_LSB		(1U << 26)	/* 1b */
+#define REG_MSDC2_DDREN_REQ_MASK_B_LSB		(1U << 27)	/* 1b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000 + 0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB		(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000 + 0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB		(1U << 0)	/* 32b */
+
+/* SPM_SRC7_MASK (0x10006000 + 0x0D8) */
+#define REG_PCIE_SRCCLKENA_MASK_B_LSB		(1U << 0)	/* 1b */
+#define REG_PCIE_INFRA_REQ_MASK_B_LSB		(1U << 1)	/* 1b */
+#define REG_PCIE_APSRC_REQ_MASK_B_LSB		(1U << 2)	/* 1b */
+#define REG_PCIE_VRF18_REQ_MASK_B_LSB		(1U << 3)	/* 1b */
+#define REG_PCIE_DDREN_REQ_MASK_B_LSB		(1U << 4)	/* 1b */
+#define REG_DPMAIF_SRCCLKENA_MASK_B_LSB		(1U << 5)	/* 1b */
+#define REG_DPMAIF_INFRA_REQ_MASK_B_LSB		(1U << 6)	/* 1b */
+#define REG_DPMAIF_APSRC_REQ_MASK_B_LSB		(1U << 7)	/* 1b */
+#define REG_DPMAIF_VRF18_REQ_MASK_B_LSB		(1U << 8)	/* 1b */
+#define REG_DPMAIF_DDREN_REQ_MASK_B_LSB		(1U << 9)	/* 1b */
+
+/* SCP_CLK_CON (0x10006000 + 0x0DC) */
+#define REG_SCP_26M_CK_SEL_LSB			(1U << 0)	/* 1b */
+#define REG_SCP_DCM_EN_LSB			(1U << 1)	/* 1b */
+#define SCP_SECURE_VREQ_MASK_LSB		(1U << 2)	/* 1b */
+#define SCP_SLP_REQ_LSB				(1U << 3)	/* 1b */
+#define SCP_SLP_ACK_LSB				(1U << 4)	/* 1b */
+
+/* PCM_DEBUG_CON (0x10006000 + 0x0E0) */
+#define PCM_DEBUG_OUT_ENABLE_LSB		(1U << 0)	/* 1b */
+
+/* DDREN_DBC_CON (0x10006000 + 0x0E8) */
+#define REG_DDREN_DBC_LEN_LSB			(1U << 0)	/* 10b */
+#define REG_DDREN_DBC_EN_LSB			(1U << 16)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON4 (0x10006000 + 0x0EC) */
+#define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB	(1U << 0)	/* 1b */
+#define REG_DPMAIF_INFRA_ACK_MASK_LSB		(1U << 1)	/* 1b */
+#define REG_DPMAIF_APSRC_ACK_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_DPMAIF_VRF18_ACK_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_DPMAIF_DDREN_ACK_MASK_LSB		(1U << 4)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON0 (0x10006000 + 0x0F0) */
+#define REG_MD_0_SRCCLKENA_ACK_MASK_LSB		(1U << 0)	/* 1b */
+#define REG_MD_0_INFRA_ACK_MASK_LSB		(1U << 1)	/* 1b */
+#define REG_MD_0_APSRC_ACK_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_MD_0_VRF18_ACK_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_MD_0_DDREN_ACK_MASK_LSB		(1U << 4)	/* 1b */
+#define REG_MD_1_SRCCLKENA_ACK_MASK_LSB		(1U << 5)	/* 1b */
+#define REG_MD_1_INFRA_ACK_MASK_LSB		(1U << 6)	/* 1b */
+#define REG_MD_1_APSRC_ACK_MASK_LSB		(1U << 7)	/* 1b */
+#define REG_MD_1_VRF18_ACK_MASK_LSB		(1U << 8)	/* 1b */
+#define REG_MD_1_DDREN_ACK_MASK_LSB		(1U << 9)	/* 1b */
+#define REG_CONN_SRCCLKENA_ACK_MASK_LSB		(1U << 10)	/* 1b */
+#define REG_CONN_INFRA_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_CONN_APSRC_ACK_MASK_LSB		(1U << 12)	/* 1b */
+#define REG_CONN_VRF18_ACK_MASK_LSB		(1U << 13)	/* 1b */
+#define REG_CONN_DDREN_ACK_MASK_LSB		(1U << 14)	/* 1b */
+#define REG_SSPM_SRCCLKENA_ACK_MASK_LSB		(1U << 15)	/* 1b */
+#define REG_SSPM_INFRA_ACK_MASK_LSB		(1U << 16)	/* 1b */
+#define REG_SSPM_APSRC_ACK_MASK_LSB		(1U << 17)	/* 1b */
+#define REG_SSPM_VRF18_ACK_MASK_LSB		(1U << 18)	/* 1b */
+#define REG_SSPM_DDREN_ACK_MASK_LSB		(1U << 19)	/* 1b */
+#define REG_SCP_SRCCLKENA_ACK_MASK_LSB		(1U << 20)	/* 1b */
+#define REG_SCP_INFRA_ACK_MASK_LSB		(1U << 21)	/* 1b */
+#define REG_SCP_APSRC_ACK_MASK_LSB		(1U << 22)	/* 1b */
+#define REG_SCP_VRF18_ACK_MASK_LSB		(1U << 23)	/* 1b */
+#define REG_SCP_DDREN_ACK_MASK_LSB		(1U << 24)	/* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB	(1U << 25)	/* 1b */
+#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB	(1U << 26)	/* 1b */
+#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB	(1U << 27)	/* 1b */
+#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB	(1U << 28)	/* 1b */
+#define REG_AUDIO_DSP_DDREN_ACK_MASK_LSB	(1U << 29)	/* 1b */
+#define REG_DISP0_DDREN_ACK_MASK_LSB		(1U << 30)	/* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB		(1U << 31)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON1 (0x10006000 + 0x0F4) */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB		(1U << 0)	/* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB		(1U << 1)	/* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB		(1U << 2)	/* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB		(1U << 3)	/* 1b */
+#define REG_UFS_DDREN_ACK_MASK_LSB		(1U << 4)	/* 1b */
+#define REG_APU_SRCCLKENA_ACK_MASK_LSB		(1U << 5)	/* 1b */
+#define REG_APU_INFRA_ACK_MASK_LSB		(1U << 6)	/* 1b */
+#define REG_APU_APSRC_ACK_MASK_LSB		(1U << 7)	/* 1b */
+#define REG_APU_VRF18_ACK_MASK_LSB		(1U << 8)	/* 1b */
+#define REG_APU_DDREN_ACK_MASK_LSB		(1U << 9)	/* 1b */
+#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB	(1U << 10)	/* 1b */
+#define REG_MCUPM_INFRA_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_MCUPM_APSRC_ACK_MASK_LSB		(1U << 12)	/* 1b */
+#define REG_MCUPM_VRF18_ACK_MASK_LSB		(1U << 13)	/* 1b */
+#define REG_MCUPM_DDREN_ACK_MASK_LSB		(1U << 14)	/* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB	(1U << 15)	/* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB		(1U << 16)	/* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB		(1U << 17)	/* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB		(1U << 18)	/* 1b */
+#define REG_MSDC0_DDREN_ACK_MASK_LSB		(1U << 19)	/* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB	(1U << 20)	/* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB		(1U << 21)	/* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB		(1U << 22)	/* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB		(1U << 23)	/* 1b */
+#define REG_MSDC1_DDREN_ACK_MASK_LSB		(1U << 24)	/* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB		(1U << 25)	/* 1b */
+#define REG_DISP1_DDREN_ACK_MASK_LSB		(1U << 26)	/* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB		(1U << 27)	/* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB		(1U << 28)	/* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB		(1U << 29)	/* 1b */
+#define REG_GCE_DDREN_ACK_MASK_LSB		(1U << 30)	/* 1b */
+
+/* SPM_RESOURCE_ACK_CON2 (0x10006000 + 0x0F8) */
+#define SPM_SRCCLKENA_ACK_WAIT_CYCLE_LSB	(1U << 0)	/* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB		(1U << 8)	/* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB		(1U << 16)	/* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB		(1U << 24)	/* 8b */
+
+/* SPM_RESOURCE_ACK_CON3 (0x10006000 + 0x0FC) */
+#define SPM_DDREN_ACK_WAIT_CYCLE_LSB		(1U << 0)	/* 8b */
+#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB	(1U << 8)	/* 1b */
+#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB		(1U << 9)	/* 1b */
+#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB		(1U << 10)	/* 1b */
+#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB		(1U << 11)	/* 1b */
+#define REG_BAK_PSRI_DDREN_ACK_MASK_LSB		(1U << 12)	/* 1b */
+#define REG_AFE_SRCCLKENA_ACK_MASK_LSB		(1U << 13)	/* 1b */
+#define REG_AFE_INFRA_ACK_MASK_LSB		(1U << 14)	/* 1b */
+#define REG_AFE_APSRC_ACK_MASK_LSB		(1U << 15)	/* 1b */
+#define REG_AFE_VRF18_ACK_MASK_LSB		(1U << 16)	/* 1b */
+#define REG_AFE_DDREN_ACK_MASK_LSB		(1U << 17)	/* 1b */
+#define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB	(1U << 18)	/* 1b */
+#define REG_MSDC2_INFRA_ACK_MASK_LSB		(1U << 19)	/* 1b */
+#define REG_MSDC2_APSRC_ACK_MASK_LSB		(1U << 20)	/* 1b */
+#define REG_MSDC2_VRF18_ACK_MASK_LSB		(1U << 21)	/* 1b */
+#define REG_MSDC2_DDREN_ACK_MASK_LSB		(1U << 22)	/* 1b */
+#define REG_PCIE_SRCCLKENA_ACK_MASK_LSB		(1U << 23)	/* 1b */
+#define REG_PCIE_INFRA_ACK_MASK_LSB		(1U << 24)	/* 1b */
+#define REG_PCIE_APSRC_ACK_MASK_LSB		(1U << 25)	/* 1b */
+#define REG_PCIE_VRF18_ACK_MASK_LSB		(1U << 26)	/* 1b */
+#define REG_PCIE_DDREN_ACK_MASK_LSB		(1U << 27)	/* 1b */
+
+/* PCM_REG0_DATA (0x10006000 + 0x100) */
+#define PCM_REG0_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG2_DATA (0x10006000 + 0x104) */
+#define PCM_REG2_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG6_DATA (0x10006000 + 0x108) */
+#define PCM_REG6_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG7_DATA (0x10006000 + 0x10C) */
+#define PCM_REG7_RF_LSB				(1U << 0)	/* 32b */
+
+/* PCM_REG13_DATA (0x10006000 + 0x110) */
+#define PCM_REG13_RF_LSB			(1U << 0)	/* 32b */
+
+/* SRC_REQ_STA_0 (0x10006000 + 0x114) */
+#define MD_0_SRCCLKENA_LSB			(1U << 0)	/* 1b */
+#define MD_0_INFRA_REQ_LSB			(1U << 1)	/* 1b */
+#define MD_0_APSRC_REQ_LSB			(1U << 2)	/* 1b */
+#define MD_0_VRF18_REQ_LSB			(1U << 4)	/* 1b */
+#define MD_0_DDREN_REQ_LSB			(1U << 5)	/* 1b */
+#define MD_1_SRCCLKENA_LSB			(1U << 6)	/* 1b */
+#define MD_1_INFRA_REQ_LSB			(1U << 7)	/* 1b */
+#define MD_1_APSRC_REQ_LSB			(1U << 8)	/* 1b */
+#define MD_1_VRF18_REQ_LSB			(1U << 10)	/* 1b */
+#define MD_1_DDREN_REQ_LSB			(1U << 11)	/* 1b */
+#define CONN_SRCCLKENA_LSB			(1U << 12)	/* 1b */
+#define CONN_SRCCLKENB_LSB			(1U << 13)	/* 1b */
+#define CONN_INFRA_REQ_LSB			(1U << 14)	/* 1b */
+#define CONN_APSRC_REQ_LSB			(1U << 15)	/* 1b */
+#define CONN_VRF18_REQ_LSB			(1U << 16)	/* 1b */
+#define CONN_DDREN_REQ_LSB			(1U << 17)	/* 1b */
+#define SRCCLKENI_LSB				(1U << 18)	/* 3b */
+#define SSPM_SRCCLKENA_LSB			(1U << 21)	/* 1b */
+#define SSPM_INFRA_REQ_LSB			(1U << 22)	/* 1b */
+#define SSPM_APSRC_REQ_LSB			(1U << 23)	/* 1b */
+#define SSPM_VRF18_REQ_LSB			(1U << 24)	/* 1b */
+#define SSPM_DDREN_REQ_LSB			(1U << 25)	/* 1b */
+#define DISP0_APSRC_REQ_LSB			(1U << 26)	/* 1b */
+#define DISP0_DDREN_REQ_LSB			(1U << 27)	/* 1b */
+#define DISP1_APSRC_REQ_LSB			(1U << 28)	/* 1b */
+#define DISP1_DDREN_REQ_LSB			(1U << 29)	/* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB		(1U << 30)	/* 1b */
+
+/* SRC_REQ_STA_1 (0x10006000 + 0x118) */
+#define SCP_SRCCLKENA_LSB			(1U << 0)	/* 1b */
+#define SCP_INFRA_REQ_LSB			(1U << 1)	/* 1b */
+#define SCP_APSRC_REQ_LSB			(1U << 2)	/* 1b */
+#define SCP_VRF18_REQ_LSB			(1U << 3)	/* 1b */
+#define SCP_DDREN_REQ_LSB			(1U << 4)	/* 1b */
+#define AUDIO_DSP_SRCCLKENA_LSB			(1U << 5)	/* 1b */
+#define AUDIO_DSP_INFRA_REQ_LSB			(1U << 6)	/* 1b */
+#define AUDIO_DSP_APSRC_REQ_LSB			(1U << 7)	/* 1b */
+#define AUDIO_DSP_VRF18_REQ_LSB			(1U << 8)	/* 1b */
+#define AUDIO_DSP_DDREN_REQ_LSB			(1U << 9)	/* 1b */
+#define UFS_SRCCLKENA_LSB			(1U << 10)	/* 1b */
+#define UFS_INFRA_REQ_LSB			(1U << 11)	/* 1b */
+#define UFS_APSRC_REQ_LSB			(1U << 12)	/* 1b */
+#define UFS_VRF18_REQ_LSB			(1U << 13)	/* 1b */
+#define UFS_DDREN_REQ_LSB			(1U << 14)	/* 1b */
+#define GCE_INFRA_REQ_LSB			(1U << 15)	/* 1b */
+#define GCE_APSRC_REQ_LSB			(1U << 16)	/* 1b */
+#define GCE_VRF18_REQ_LSB			(1U << 17)	/* 1b */
+#define GCE_DDREN_REQ_LSB			(1U << 18)	/* 1b */
+#define INFRASYS_APSRC_REQ_LSB			(1U << 19)	/* 1b */
+#define INFRASYS_DDREN_REQ_LSB			(1U << 20)	/* 1b */
+#define MSDC0_SRCCLKENA_LSB			(1U << 21)	/* 1b */
+#define MSDC0_INFRA_REQ_LSB			(1U << 22)	/* 1b */
+#define MSDC0_APSRC_REQ_LSB			(1U << 23)	/* 1b */
+#define MSDC0_VRF18_REQ_LSB			(1U << 24)	/* 1b */
+#define MSDC0_DDREN_REQ_LSB			(1U << 25)	/* 1b */
+#define MSDC1_SRCCLKENA_LSB			(1U << 26)	/* 1b */
+#define MSDC1_INFRA_REQ_LSB			(1U << 27)	/* 1b */
+#define MSDC1_APSRC_REQ_LSB			(1U << 28)	/* 1b */
+#define MSDC1_VRF18_REQ_LSB			(1U << 29)	/* 1b */
+#define MSDC1_DDREN_REQ_LSB			(1U << 30)	/* 1b */
+
+/* SRC_REQ_STA_2 (0x10006000 + 0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB			(1U << 0)	/* 9b */
+#define EMI_SELF_REFRESH_CH_LSB			(1U << 9)	/* 2b */
+#define SW2SPM_WAKEUP_LSB			(1U << 11)	/* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB			(1U << 15)	/* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB			(1U << 16)	/* 4b */
+#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB	(1U << 20)	/* 1b */
+#define SPM_RESERVED_SRCCLKENA_LSB		(1U << 21)	/* 1b */
+#define SPM_RESERVED_INFRA_REQ_LSB		(1U << 22)	/* 1b */
+#define SPM_RESERVED_APSRC_REQ_LSB		(1U << 23)	/* 1b */
+#define SPM_RESERVED_VRF18_REQ_LSB		(1U << 24)	/* 1b */
+#define SPM_RESERVED_DDREN_REQ_LSB		(1U << 25)	/* 1b */
+#define MCUPM_SRCCLKENA_LSB			(1U << 26)	/* 1b */
+#define MCUPM_INFRA_REQ_LSB			(1U << 27)	/* 1b */
+#define MCUPM_APSRC_REQ_LSB			(1U << 28)	/* 1b */
+#define MCUPM_VRF18_REQ_LSB			(1U << 29)	/* 1b */
+#define MCUPM_DDREN_REQ_LSB			(1U << 30)	/* 1b */
+
+/* PCM_TIMER_OUT (0x10006000 + 0x120) */
+#define PCM_TIMER_LSB				(1U << 0)	/* 32b */
+
+/* PCM_WDT_OUT (0x10006000 + 0x124) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB		(1U << 0)	/* 32b */
+
+/* SPM_IRQ_STA (0x10006000 + 0x128) */
+#define TWAM_IRQ_LSB				(1U << 2)	/* 1b */
+#define PCM_IRQ_LSB				(1U << 3)	/* 1b */
+
+/* SRC_REQ_STA_4 (0x10006000 + 0x12C) */
+#define APU_SRCCLKENA_LSB			(1U << 0)	/* 1b */
+#define APU_INFRA_REQ_LSB			(1U << 1)	/* 1b */
+#define APU_APSRC_REQ_LSB			(1U << 2)	/* 1b */
+#define APU_VRF18_REQ_LSB			(1U << 3)	/* 1b */
+#define APU_DDREN_REQ_LSB			(1U << 4)	/* 1b */
+#define BAK_PSRI_SRCCLKENA_LSB			(1U << 5)	/* 1b */
+#define BAK_PSRI_INFRA_REQ_LSB			(1U << 6)	/* 1b */
+#define BAK_PSRI_APSRC_REQ_LSB			(1U << 7)	/* 1b */
+#define BAK_PSRI_VRF18_REQ_LSB			(1U << 8)	/* 1b */
+#define BAK_PSRI_DDREN_REQ_LSB			(1U << 9)	/* 1b */
+#define MSDC2_SRCCLKENA_LSB			(1U << 10)	/* 1b */
+#define MSDC2_INFRA_REQ_LSB			(1U << 11)	/* 1b */
+#define MSDC2_APSRC_REQ_LSB			(1U << 12)	/* 1b */
+#define MSDC2_VRF18_REQ_LSB			(1U << 13)	/* 1b */
+#define MSDC2_DDREN_REQ_LSB			(1U << 14)	/* 1b */
+#define PCIE_SRCCLKENA_LSB			(1U << 15)	/* 1b */
+#define PCIE_INFRA_REQ_LSB			(1U << 16)	/* 1b */
+#define PCIE_APSRC_REQ_LSB			(1U << 17)	/* 1b */
+#define PCIE_VRF18_REQ_LSB			(1U << 18)	/* 1b */
+#define PCIE_DDREN_REQ_LSB			(1U << 19)	/* 1b */
+#define DPMAIF_SRCCLKENA_LSB			(1U << 20)	/* 1b */
+#define DPMAIF_INFRA_REQ_LSB			(1U << 21)	/* 1b */
+#define DPMAIF_APSRC_REQ_LSB			(1U << 22)	/* 1b */
+#define DPMAIF_VRF18_REQ_LSB			(1U << 23)	/* 1b */
+#define DPMAIF_DDREN_REQ_LSB			(1U << 24)	/* 1b */
+#define AFE_SRCCLKENA_LSB			(1U << 25)	/* 1b */
+#define AFE_INFRA_REQ_LSB			(1U << 26)	/* 1b */
+#define AFE_APSRC_REQ_LSB			(1U << 27)	/* 1b */
+#define AFE_VRF18_REQ_LSB			(1U << 28)	/* 1b */
+#define AFE_DDREN_REQ_LSB			(1U << 29)	/* 1b */
+
+/* MD32PCM_WAKEUP_STA (0x10006000 + 0x130) */
+#define MD32PCM_WAKEUP_STA_LSB			(1U << 0)	/* 32b */
+
+/* MD32PCM_EVENT_STA (0x10006000 + 0x134) */
+#define MD32PCM_EVENT_STA_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_STA (0x10006000 + 0x138) */
+#define SPM_WAKEUP_EVENT_L_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_EXT_STA (0x10006000 + 0x13C) */
+#define EXT_WAKEUP_EVENT_LSB			(1U << 0)	/* 32b */
+
+/* SPM_WAKEUP_MISC (0x10006000 + 0x140) */
+#define GIC_WAKEUP_LSB				(1U << 0)	/* 10b */
+#define DVFSRC_IRQ_LSB				(1U << 16)	/* 1b */
+#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB	(1U << 17)	/* 1b */
+#define PCM_TIMER_EVENT_LSB			(1U << 18)	/* 1b */
+#define PMIC_EINT_OUT_B_LSB			(1U << 19)	/* 2b */
+#define TWAM_IRQ_B_LSB				(1U << 21)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB		(1U << 25)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB		(1U << 26)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB		(1U << 27)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB		(1U << 28)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB		(1U << 29)	/* 1b */
+#define PMIC_IRQ_ACK_LSB			(1U << 30)	/* 1b */
+#define PMIC_SCP_IRQ_LSB			(1U << 31)	/* 1b */
+
+/* MM_DVFS_HALT (0x10006000 + 0x144) */
+#define MM_DVFS_HALT_LSB			(1U << 0)	/* 5b */
+
+/* BUS_PROTECT_RDY (0x10006000 + 0x150) */
+#define PROTECT_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT1_RDY (0x10006000 + 0x154) */
+#define PROTECT1_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT2_RDY (0x10006000 + 0x158) */
+#define PROTECT2_READY_LSB			(1U << 0)	/* 32b */
+/* BUS_PROTECT3_RDY (0x10006000 + 0x15C) */
+
+#define PROTECT3_READY_LSB			(1U << 0)	/* 32b */
+/* SUBSYS_IDLE_STA (0x10006000 + 0x160) */
+#define SUBSYS_IDLE_SIGNALS_LSB			(1U << 0)	/* 32b */
+/* PCM_STA (0x10006000 + 0x164) */
+
+#define PCM_CK_SEL_O_LSB			(1U << 0)	/* 4b */
+#define EXT_SRC_STA_LSB				(1U << 4)	/* 3b */
+
+/* SRC_REQ_STA_3 (0x10006000 + 0x168) */
+#define CCIF_EVENT_STATE_LSB			(1U << 0)	/* 1b */
+#define F26M_STATE_LSB				(1U << 16)	/* 1b */
+#define INFRA_STATE_LSB				(1U << 17)	/* 1b */
+#define APSRC_STATE_LSB				(1U << 18)	/* 1b */
+#define VRF18_STATE_LSB				(1U << 19)	/* 1b */
+#define DDREN_STATE_LSB				(1U << 20)	/* 1b */
+#define DVFS_STATE_LSB				(1U << 21)	/* 1b */
+#define SW_MAILBOX_STATE_LSB			(1U << 22)	/* 1b */
+#define SSPM_MAILBOX_STATE_LSB			(1U << 23)	/* 1b */
+#define ADSP_MAILBOX_STATE_LSB			(1U << 24)	/* 1b */
+#define SCP_MAILBOX_STATE_LSB			(1U << 25)	/* 1b */
+
+/* PWR_STATUS (0x10006000 + 0x16C) */
+#define PWR_STATUS_LSB				(1U << 0)	/* 32b */
+
+/* PWR_STATUS_2ND (0x10006000 + 0x170) */
+#define PWR_STATUS_2ND_LSB			(1U << 0)	/* 32b */
+
+/* CPU_PWR_STATUS (0x10006000 + 0x174) */
+#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB		(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB		(1U << 1)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB		(1U << 2)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB		(1U << 3)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB		(1U << 4)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB		(1U << 5)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB		(1U << 6)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB		(1U << 7)	/* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB		(1U << 8)	/* 1b */
+#define MCUSYS_SPMC_PWR_ON_ACK_LSB		(1U << 9)	/* 1b */
+
+/* OTHER_PWR_STATUSi (0x10006000 + 0x178) */
+#define OTHER_PWR_STATUS_LSB			(1U << 0)	/* 32b */
+
+/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000 + 0x17C) */
+#define SPM_SRCCLKENA_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_SRCCLKENA_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_INFRA_EVENT_COUNT_STA (0x10006000 + 0x180) */
+#define SPM_INFRA_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_VRF18_EVENT_COUNT_STA (0x10006000 + 0x184) */
+#define SPM_VRF18_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_APSRC_EVENT_COUNT_STA (0x10006000 + 0x188) */
+#define SPM_APSRC_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* SPM_DDREN_EVENT_COUNT_STA (0x10006000 + 0x18C) */
+#define SPM_DDREN_SLEEP_COUNT_LSB		(1U << 0)	/* 16b */
+#define SPM_DDREN_WAKE_COUNT_LSB		(1U << 16)	/* 16b */
+
+/* MD32PCM_STA (0x10006000 + 0x190) */
+#define MD32PCM_HALT_LSB			(1U << 0)	/* 1b */
+#define MD32PCM_GATED_LSB			(1U << 1)	/* 1b */
+
+/* MD32PCM_PC (0x10006000 + 0x194) */
+#define MON_PC_LSB				(1U << 0)	/* 32b */
+
+/* DVFSRC_EVENT_STA (0x10006000 + 0x1A4) */
+#define DVFSRC_EVENT_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT4_RDY (0x10006000 + 0x1A8) */
+#define PROTECT4_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT5_RDY (0x10006000 + 0x1AC) */
+#define PROTECT5_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT6_RDY (0x10006000 + 0x1B0) */
+#define PROTECT6_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT7_RDY (0x10006000 + 0x1B4) */
+#define PROTECT7_READY_LSB			(1U << 0)	/* 32b */
+
+/* BUS_PROTECT8_RDY (0x10006000 + 0x1B8) */
+#define PROTECT8_READY_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA0 (0x10006000 + 0x1D0) */
+#define LAST_IDLE_CNT_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA1 (0x10006000 + 0x1D4) */
+#define LAST_IDLE_CNT_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA2 (0x10006000 + 0x1D8) */
+#define LAST_IDLE_CNT_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_LAST_STA3 (0x10006000 + 0x1DC) */
+#define LAST_IDLE_CNT_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA0 (0x10006000 + 0x1E0) */
+#define CURRENT_IDLE_CNT_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA1 (0x10006000 + 0x1E4) */
+#define CURRENT_IDLE_CNT_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA2 (0x10006000 + 0x1E8) */
+#define CURRENT_IDLE_CNT_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_CURR_STA3 (0x10006000 + 0x1EC) */
+#define CURRENT_IDLE_CNT_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_TIMER_OUT (0x10006000 + 0x1F0) */
+#define TWAM_TIMER_LSB				(1U << 0)	/* 32b */
+
+/* SPM_CG_CHECK_STA (0x10006000 + 0x1F4) */
+#define SPM_CG_CHECK_SLEEP_REQ_0_LSB		(1U << 0)	/* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_1_LSB		(1U << 1)	/* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_2_LSB		(1U << 2)	/* 1b */
+
+/* SPM_DVFS_STA (0x10006000 + 0x1F8) */
+#define TARGET_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_OPP_STA (0x10006000 + 0x1FC) */
+#define TARGET_DVFS_OPP_LSB			(1U << 0)	/* 5b */
+#define CURRENT_DVFS_OPP_LSB			(1U << 5)	/* 5b */
+#define RELAY_DVFS_OPP_LSB			(1U << 10)	/* 5b */
+
+/* SPM_MCUSYS_PWR_CON (0x10006000 + 0x200) */
+#define MCUSYS_SPMC_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MCUSYS_SPMC_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MCUSYS_SPMC_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB		(1U << 5)	/* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB			(1U << 6)	/* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB			(1U << 7)	/* 1b */
+#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPUTOP_PWR_CON (0x10006000 + 0x204) */
+#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB				(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPUTOP_LSB				(1U << 2)	/* 1b */
+#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB				(1U << 4)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB			(1U << 5)	/* 1b */
+#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB				(1U << 6)	/* 1b */
+#define MP0_VPROC_EXT_OFF_LSB					(1U << 7)	/* 1b */
+#define MP0_VSRAM_EXT_OFF_LSB					(1U << 8)	/* 1b */
+#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB	(1U << 31)	/* 1b */
+/* SPM_CPU0_PWR_CON (0x10006000 + 0x208) */
+#define MP0_SPMC_PWR_RST_B_CPU0_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU0_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU0_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU1_PWR_CON (0x10006000 + 0x20C) */
+#define MP0_SPMC_PWR_RST_B_CPU1_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU1_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU1_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU2_PWR_CON (0x10006000 + 0x210) */
+#define MP0_SPMC_PWR_RST_B_CPU2_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU2_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU2_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU3_PWR_CON (0x10006000 + 0x214) */
+#define MP0_SPMC_PWR_RST_B_CPU3_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU3_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU3_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU4_PWR_CON (0x10006000 + 0x218) */
+#define MP0_SPMC_PWR_RST_B_CPU4_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU4_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU4_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU5_PWR_CON (0x10006000 + 0x21C) */
+#define MP0_SPMC_PWR_RST_B_CPU5_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU5_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU5_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU6_PWR_CON (0x10006000 + 0x220) */
+#define MP0_SPMC_PWR_RST_B_CPU6_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU6_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU6_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB	(1U << 31)	/* 1b */
+
+/* SPM_CPU7_PWR_CON (0x10006000 + 0x224) */
+#define MP0_SPMC_PWR_RST_B_CPU7_LSB			(1U << 0)	/* 1b */
+#define MP0_SPMC_PWR_ON_CPU7_LSB			(1U << 2)	/* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB		(1U << 5)	/* 1b */
+#define MP0_VPROC_EXT_OFF_CPU7_LSB			(1U << 7)	/* 1b */
+#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB	(1U << 31)	/* 1b */
+
+/* ARMPLL_CLK_CON (0x10006000 + 0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB			(1U << 0)	/* 6b */
+#define SC_ARM_CK_OFF_LSB			(1U << 6)	/* 6b */
+#define SC_ARMPLL_OFF_LSB			(1U << 12)	/* 1b */
+#define SC_ARMBPLL_OFF_LSB			(1U << 13)	/* 1b */
+#define SC_ARMBPLL1_OFF_LSB			(1U << 14)	/* 1b */
+#define SC_ARMBPLL2_OFF_LSB			(1U << 15)	/* 1b */
+#define SC_ARMBPLL3_OFF_LSB			(1U << 16)	/* 1b */
+#define SC_CCIPLL_CKOFF_LSB			(1U << 17)	/* 1b */
+#define SC_ARMDDS_OFF_LSB			(1U << 18)	/* 1b */
+#define SC_ARMBPLL_S_OFF_LSB			(1U << 19)	/* 1b */
+#define SC_ARMBPLL1_S_OFF_LSB			(1U << 20)	/* 1b */
+#define SC_ARMBPLL2_S_OFF_LSB			(1U << 21)	/* 1b */
+#define SC_ARMBPLL3_S_OFF_LSB			(1U << 22)	/* 1b */
+#define SC_CCIPLL_PWROFF_LSB			(1U << 23)	/* 1b */
+#define SC_ARMPLLOUT_OFF_LSB			(1U << 24)	/* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB			(1U << 25)	/* 1b */
+#define SC_ARMBPLLOUT1_OFF_LSB			(1U << 26)	/* 1b */
+#define SC_ARMBPLLOUT2_OFF_LSB			(1U << 27)	/* 1b */
+#define SC_ARMBPLLOUT3_OFF_LSB			(1U << 28)	/* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB			(1U << 29)	/* 1b */
+
+/* MCUSYS_IDLE_STA (0x10006000 + 0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB			(1U << 0)	/* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB		(1U << 1)	/* 1b */
+#define MCUSYS_DDR_EN_0_LSB			(1U << 2)	/* 1b */
+#define MCUSYS_DDR_EN_1_LSB			(1U << 3)	/* 1b */
+#define MCUSYS_DDR_EN_2_LSB			(1U << 4)	/* 1b */
+#define MCUSYS_DDR_EN_3_LSB			(1U << 5)	/* 1b */
+#define MCUSYS_DDR_EN_4_LSB			(1U << 6)	/* 1b */
+#define MCUSYS_DDR_EN_5_LSB			(1U << 7)	/* 1b */
+#define MCUSYS_DDR_EN_6_LSB			(1U << 8)	/* 1b */
+#define MCUSYS_DDR_EN_7_LSB			(1U << 9)	/* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB		(1U << 16)	/* 8b */
+#define WFI_AF_SEL_LSB				(1U << 24)	/* 8b */
+
+/* GIC_WAKEUP_STA (0x10006000 + 0x234) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB		(1U << 10)	/* 10b */
+
+/* CPU_SPARE_CON (0x10006000 + 0x238) */
+#define CPU_SPARE_CON_LSB			(1U << 0)	/* 32b */
+
+/* CPU_SPARE_CON_SET (0x10006000 + 0x23C) */
+#define CPU_SPARE_CON_SET_LSB			(1U << 0)	/* 32b */
+
+/* CPU_SPARE_CON_CLR (0x10006000 + 0x240) */
+#define CPU_SPARE_CON_CLR_LSB			(1U << 0)	/* 32b */
+
+/* ARMPLL_CLK_SEL (0x10006000 + 0x244) */
+#define ARMPLL_CLK_SEL_LSB			(1U << 0)	/* 15b */
+
+/* EXT_INT_WAKEUP_REQ (0x10006000 + 0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB			(1U << 0)	/* 10b */
+
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000 + 0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB		(1U << 0)	/* 10b */
+
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000 + 0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB		(1U << 0)	/* 10b */
+
+/* CPU_IRQ_MASK (0x10006000 + 0x260) */
+#define CPU_IRQ_MASK_LSB			(1U << 0)	/* 8b */
+
+/* CPU_IRQ_MASK_SET (0x10006000 + 0x264) */
+#define CPU_IRQ_MASK_SET_LSB			(1U << 0)	/* 8b */
+
+/* CPU_IRQ_MASK_CLR (0x10006000 + 0x268) */
+#define CPU_IRQ_MASK_CLR_LSB			(1U << 0)	/* 8b */
+
+/* CPU_WFI_EN (0x10006000 + 0x280) */
+#define CPU_WFI_EN_LSB				(1U << 0)	/* 8b */
+
+/* CPU_WFI_EN_SET (0x10006000 + 0x284) */
+#define CPU_WFI_EN_SET_LSB			(1U << 0)	/* 8b */
+
+/* CPU_WFI_EN_CLR (0x10006000 + 0x288) */
+#define CPU_WFI_EN_CLR_LSB			(1U << 0)	/* 8b */
+
+/* ROOT_CPUTOP_ADDR (0x10006000 + 0x2A0) */
+#define ROOT_CPUTOP_ADDR_LSB			(1U << 0)	/* 32b */
+
+/* ROOT_CORE_ADDR (0x10006000 + 0x2A4) */
+#define ROOT_CORE_ADDR_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_0 (0x10006000 + 0x2D0) */
+#define SPM2SW_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_1 (0x10006000 + 0x2D4) */
+#define SPM2SW_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_2 (0x10006000 + 0x2D8) */
+#define SPM2SW_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM2SW_MAILBOX_3 (0x10006000 + 0x2DC) */
+#define SPM2SW_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_WAKEUP (0x10006000 + 0x2E0) */
+#define SW2SPM_WAKEUP_SW2SPM_WAKEUP_LSB		(1U << 0)	/* 4b */
+
+/* SW2SPM_WAKEUP_SET (0x10006000 + 0x2E4) */
+#define SW2SPM_WAKEUP_SET_LSB			(1U << 0)	/* 4b */
+
+/* SW2SPM_WAKEUP_CLR (0x10006000 + 0x2E8) */
+#define SW2SPM_WAKEUP_CLR_LSB			(1U << 0)	/* 4b */
+
+/* SW2SPM_MAILBOX_0 (0x10006000 + 0x2EC) */
+#define SW2SPM_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_MAILBOX_1 (0x10006000 + 0x2F0) */
+#define SW2SPM_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_MAILBOX_2 (0x10006000 + 0x2F4) */
+#define SW2SPM_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_MAILBOX_3 (0x10006000 + 0x2F8) */
+#define SW2SPM_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* SW2SPM_CFG (0x10006000 + 0x2FC) */
+#define SWU2SPM_INT_MASK_B_LSB			(1U << 0)	/* 4b */
+
+/* MD1_PWR_CON (0x10006000 + 0x300) */
+#define MD1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MD1_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define MD1_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MD1_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MD1_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MD1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MD1_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* CONN_PWR_CON (0x10006000 + 0x304) */
+#define CONN_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CONN_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CONN_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define CONN_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CONN_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+
+/* MFG0_PWR_CON (0x10006000 + 0x308) */
+#define MFG0_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG0_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG0_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG0_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG0_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG0_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG0_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG1_PWR_CON (0x10006000 + 0x30C) */
+#define MFG1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG1_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG1_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG1_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG1_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG1_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG2_PWR_CON (0x10006000 + 0x310) */
+#define MFG2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG3_PWR_CON (0x10006000 + 0x314) */
+#define MFG3_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG3_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG3_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG3_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG3_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG3_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG3_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG4_PWR_CON (0x10006000 + 0x318) */
+#define MFG4_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG4_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG4_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG4_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG4_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG4_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG4_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG5_PWR_CON (0x10006000 + 0x31C) */
+#define MFG5_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG5_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG5_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG5_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG5_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG5_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG5_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MFG6_PWR_CON (0x10006000 + 0x320) */
+#define MFG6_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MFG6_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MFG6_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MFG6_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MFG6_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MFG6_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MFG6_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* IFR_PWR_CON (0x10006000 + 0x324) */
+#define IFR_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define IFR_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define IFR_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define IFR_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define IFR_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define IFR_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_IFR_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* IFR_SUB_PWR_CON (0x10006000 + 0x328) */
+#define IFR_SUB_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define IFR_SUB_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define IFR_SUB_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define IFR_SUB_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define IFR_SUB_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define IFR_SUB_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_IFR_SUB_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* DPY_PWR_CON (0x10006000 + 0x32C) */
+#define DPY_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DPY_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define DPY_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define DPY_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DPY_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+
+/* DRAMC_MD32_PWR_CON (0x10006000 + 0x330) */
+#define DRAMC_MD32_PWR_RST_B_LSB		(1U << 0)	/* 1b */
+#define DRAMC_MD32_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define DRAMC_MD32_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define DRAMC_MD32_PWR_ON_2ND_LSB		(1U << 3)	/* 1b */
+#define DRAMC_MD32_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define DRAMC_MD32_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DRAMC_MD32_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* ISP_PWR_CON (0x10006000 + 0x334) */
+#define ISP_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define ISP_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define ISP_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define ISP_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define ISP_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define ISP_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_ISP_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* ISP2_PWR_CON (0x10006000 + 0x338) */
+#define ISP2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define ISP2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define ISP2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define ISP2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define ISP2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define ISP2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_ISP2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* IPE_PWR_CON (0x10006000 + 0x33C) */
+#define IPE_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define IPE_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define IPE_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define IPE_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define IPE_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define IPE_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_IPE_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* VDE_PWR_CON (0x10006000 + 0x340) */
+#define VDE_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VDE_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define VDE_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define VDE_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define VDE_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define VDE_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VDE_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* VDE2_PWR_CON (0x10006000 + 0x344) */
+#define VDE2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VDE2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define VDE2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define VDE2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define VDE2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define VDE2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VDE2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* VEN_PWR_CON (0x10006000 + 0x348) */
+#define VEN_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VEN_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define VEN_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define VEN_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define VEN_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define VEN_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VEN_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* VEN_CORE1_PWR_CON (0x10006000 + 0x34C) */
+#define VEN_CORE1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define VEN_CORE1_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define VEN_CORE1_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define VEN_CORE1_PWR_ON_2ND_LSB		(1U << 3)	/* 1b */
+#define VEN_CORE1_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define VEN_CORE1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* MDP_PWR_CON (0x10006000 + 0x350) */
+#define MDP_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MDP_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define MDP_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MDP_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MDP_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MDP_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_MDP_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* DIS_PWR_CON (0x10006000 + 0x354) */
+#define DIS_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DIS_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define DIS_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define DIS_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DIS_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define DIS_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DIS_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* AUDIO_PWR_CON (0x10006000 + 0x358) */
+#define AUDIO_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define AUDIO_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define AUDIO_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define AUDIO_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define AUDIO_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define AUDIO_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_AUDIO_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* CAM_PWR_CON (0x10006000 + 0x35C) */
+#define CAM_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define CAM_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define CAM_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define CAM_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* CAM_RAWA_PWR_CON (0x10006000 + 0x360) */
+#define CAM_RAWA_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_RAWA_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CAM_RAWA_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define CAM_RAWA_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_RAWA_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define CAM_RAWA_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* CAM_RAWB_PWR_CON (0x10006000 + 0x364) */
+#define CAM_RAWB_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_RAWB_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CAM_RAWB_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define CAM_RAWB_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_RAWB_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define CAM_RAWB_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* CAM_RAWC_PWR_CON (0x10006000 + 0x368) */
+#define CAM_RAWC_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define CAM_RAWC_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define CAM_RAWC_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define CAM_RAWC_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define CAM_RAWC_PWR_CLK_DIS_LSB		(1U << 4)	/* 1b */
+#define CAM_RAWC_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* SYSRAM_CON (0x10006000 + 0x36C) */
+#define SYSRAM_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB			(1U << 4)	/* 4b */
+#define SYSRAM_SRAM_PDN_LSB			(1U << 16)	/* 4b */
+
+/* SYSROM_CON (0x10006000 + 0x370) */
+#define SYSROM_SRAM_PDN_LSB			(1U << 0)	/* 8b */
+
+/* SSPM_SRAM_CON (0x10006000 + 0x374) */
+#define SSPM_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB			(1U << 4)	/* 1b */
+#define SSPM_SRAM_PDN_LSB			(1U << 16)	/* 1b */
+
+/* SCP_SRAM_CON (0x10006000 + 0x378) */
+#define SCP_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define SCP_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define SCP_SRAM_SLEEP_B_LSB			(1U << 4)	/* 1b */
+#define SCP_SRAM_PDN_LSB			(1U << 16)	/* 1b */
+
+/* DPY_SHU_SRAM_CON (0x10006000 + 0x37C) */
+#define DPY_SHU_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB		(1U << 4)	/* 2b */
+#define DPY_SHU_SRAM_PDN_LSB			(1U << 16)	/* 2b */
+
+/* UFS_SRAM_CON (0x10006000 + 0x380) */
+#define UFS_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define UFS_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define UFS_SRAM_SLEEP_B_LSB			(1U << 4)	/* 8b */
+#define UFS_SRAM_PDN_LSB			(1U << 16)	/* 8b */
+
+/* DEVAPC_IFR_SRAM_CON (0x10006000 + 0x384) */
+#define DEVAPC_IFR_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DEVAPC_IFR_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DEVAPC_IFR_SRAM_SLEEP_B_LSB		(1U << 4)	/* 6b */
+#define DEVAPC_IFR_SRAM_PDN_LSB			(1U << 16)	/* 6b */
+
+/* DEVAPC_SUBIFR_SRAM_CON (0x10006000 + 0x388) */
+#define DEVAPC_SUBIFR_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DEVAPC_SUBIFR_SRAM_PDN_LSB		(1U << 16)	/* 12b */
+
+/* DEVAPC_ACP_SRAM_CON (0x10006000 + 0x38C) */
+#define DEVAPC_ACP_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DEVAPC_ACP_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DEVAPC_ACP_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DEVAPC_ACP_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* USB_SRAM_CON (0x10006000 + 0x390) */
+#define USB_SRAM_PDN_LSB			(1U << 0)	/* 9b */
+
+/* DUMMY_SRAM_CONi (0x10006000 + 0x394) */
+#define DUMMY_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB			(1U << 4)	/* 12b */
+#define DUMMY_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* MD_EXT_BUCK_ISO_CON (0x10006000 + 0x398) */
+#define VMODEM_EXT_BUCK_ISO_LSB			(1U << 0)	/* 1b */
+#define VMD_EXT_BUCK_ISO_LSB			(1U << 1)	/* 1b */
+
+/* EXT_BUCK_ISO (0x10006000 + 0x39C) */
+#define VIMVO_EXT_BUCK_ISO_LSB			(1U << 0)	/* 1b */
+#define GPU_EXT_BUCK_ISO_LSB			(1U << 1)	/* 1b */
+#define ADSP_EXT_BUCK_ISO_LSB			(1U << 2)	/* 1b */
+#define IPU_EXT_BUCK_ISO_LSB			(1U << 5)	/* 3b */
+
+/* DXCC_SRAM_CON (0x10006000 + 0x3A0) */
+#define DXCC_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DXCC_SRAM_ISOINT_B_LSB			(1U << 1)	/* 1b */
+#define DXCC_SRAM_SLEEP_B_LSB			(1U << 4)	/* 8b */
+#define DXCC_SRAM_PDN_LSB			(1U << 16)	/* 8b */
+
+/* MSDC_PWR_CON (0x10006000 + 0x3A4) */
+#define MSDC_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MSDC_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MSDC_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define MSDC_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MSDC_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MSDC_SRAM_CKISO_LSB			(1U << 5)	/* 1b */
+#define MSDC_SRAM_ISOINT_B_LSB			(1U << 6)	/* 1b */
+#define MSDC_SRAM_PDN_LSB			(1U << 8)	/* 5b */
+#define MSDC_SRAM_SLEEP_B_LSB			(1U << 13)	/* 5b */
+#define SC_MSDC_SRAM_PDN_ACK_LSB		(1U << 18)	/* 5b */
+#define SC_MSDC_SRAM_SLEEP_B_ACK_LSB		(1U << 23)	/* 5b */
+
+/* DEBUGTOP_SRAM_CON (0x10006000 + 0x3A8) */
+#define DEBUGTOP_SRAM_PDN_LSB			(1U << 0)	/* 1b */
+
+/* DP_TX_PWR_CON (0x10006000 + 0x3AC) */
+#define DP_TX_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DP_TX_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define DP_TX_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define DP_TX_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DP_TX_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define DP_TX_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DP_TX_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* DPMAIF_SRAM_CON (0x10006000 + 0x3B0) */
+#define DPMAIF_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DPMAIF_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DPMAIF_SRAM_SLEEP_B_LSB			(1U << 4)	/* 1b */
+#define DPMAIF_SRAM_PDN_LSB			(1U << 16)	/* 1b */
+
+/* DPY_SHU2_SRAM_CON (0x10006000 + 0x3B4) */
+#define DPY_SHU2_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define DPY_SHU2_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DPY_SHU2_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DPY_SHU2_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* DRAMC_MCU2_SRAM_CON (0x10006000 + 0x3B8) */
+#define DRAMC_MCU2_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DRAMC_MCU2_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* DRAMC_MCU_SRAM_CON (0x10006000 + 0x3BC) */
+#define DRAMC_MCU_SRAM_CKISO_LSB		(1U << 0)	/* 1b */
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB		(1U << 4)	/* 12b */
+#define DRAMC_MCU_SRAM_PDN_LSB			(1U << 16)	/* 12b */
+
+/* MCUPM_PWR_CON (0x10006000 + 0x3C0) */
+#define MCUPM_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define MCUPM_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define MCUPM_PWR_ON_LSB			(1U << 2)	/* 1b */
+#define MCUPM_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define MCUPM_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define MCUPM_SRAM_CKISO_LSB			(1U << 5)	/* 1b */
+#define MCUPM_SRAM_ISOINT_B_LSB			(1U << 6)	/* 1b */
+#define MCUPM_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define MCUPM_SRAM_SLEEP_B_LSB			(1U << 9)	/* 1b */
+#define SC_MCUPM_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+#define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB		(1U << 13)	/* 1b */
+#define MCUPM_WFI_LSB				(1U << 14)	/* 1b */
+
+/* DPY2_PWR_CON (0x10006000 + 0x3C4) */
+#define DPY2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define DPY2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define DPY2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define DPY2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define DPY2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define DPY2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_DPY2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* SPM_SRAM_CON (0x10006000 + 0x3C8) */
+#define SPM_SRAM_CKISO_LSB			(1U << 0)	/* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB		(1U << 1)	/* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB		(1U << 4)	/* 2b */
+#define SPM_SRAM_PDN_LSB			(1U << 16)	/* 2b */
+
+/* PERI_PWR_CON (0x10006000 + 0x3D0) */
+#define PERI_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define PERI_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define PERI_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define PERI_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define PERI_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define PERI_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_PERI_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA0_PWR_CON (0x10006000 + 0x3D4) */
+#define NNA0_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA0_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define NNA0_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA0_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA0_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA0_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA0_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA1_PWR_CON (0x10006000 + 0x3D8) */
+#define NNA1_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA1_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define NNA1_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA1_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA1_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA1_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA1_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA2_PWR_CON (0x10006000 + 0x3DC) */
+#define NNA2_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA2_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define NNA2_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA2_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA2_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA2_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA2_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+
+/* NNA_PWR_CON (0x10006000 + 0x3E0) */
+#define NNA_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define NNA_PWR_ISO_LSB				(1U << 1)	/* 1b */
+#define NNA_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define NNA_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define NNA_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define NNA_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define SC_NNA_SRAM_PDN_ACK_LSB			(1U << 12)	/* 1b */
+
+/* ADSP_PWR_CON (0x10006000 + 0x3E4) */
+#define ADSP_PWR_RST_B_LSB			(1U << 0)	/* 1b */
+#define ADSP_PWR_ISO_LSB			(1U << 1)	/* 1b */
+#define ADSP_PWR_ON_LSB				(1U << 2)	/* 1b */
+#define ADSP_PWR_ON_2ND_LSB			(1U << 3)	/* 1b */
+#define ADSP_PWR_CLK_DIS_LSB			(1U << 4)	/* 1b */
+#define ADSP_SRAM_CKISO_LSB			(1U << 5)	/* 1b */
+#define ADSP_SRAM_ISOINT_B_LSB			(1U << 6)	/* 1b */
+#define ADSP_SRAM_PDN_LSB			(1U << 8)	/* 1b */
+#define ADSP_SRAM_SLEEP_B_LSB			(1U << 9)	/* 1b */
+#define SC_ADSP_SRAM_PDN_ACK_LSB		(1U << 12)	/* 1b */
+#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB		(1U << 13)	/* 1b */
+
+/* DPY_SRAM_CON (0x10006000 + 0x3E8) */
+#define DPY_SRAM_PDN_LSB			(1U << 16)	/* 4b */
+#define SC_DPY_SRAM_PDN_ACK_LSB			(1U << 24)	/* 4b */
+
+/* SPM_MEM_CK_SEL (0x10006000 + 0x400) */
+#define SC_MEM_CK_SEL_LSB			(1U << 0)	/* 1b */
+#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB		(1U << 1)	/* 1b */
+
+/* SPM_BUS_PROTECT_MASK_B (0x10006000 + 0X404) */
+#define SPM_BUS_PROTECT_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT1_MASK_B (0x10006000 + 0x408) */
+#define SPM_BUS_PROTECT1_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT2_MASK_B (0x10006000 + 0x40C) */
+#define SPM_BUS_PROTECT2_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT3_MASK_B (0x10006000 + 0x410) */
+#define SPM_BUS_PROTECT3_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT4_MASK_B (0x10006000 + 0x414) */
+#define SPM_BUS_PROTECT4_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_EMI_BW_MODE (0x10006000 + 0x418) */
+#define EMI_BW_MODE_LSB				(1U << 0)	/* 1b */
+#define EMI_BOOST_MODE_LSB			(1U << 1)	/* 1b */
+#define EMI_BW_MODE_2_LSB			(1U << 2)	/* 1b */
+#define EMI_BOOST_MODE_2_LSB			(1U << 3)	/* 1b */
+#define SPM_S1_MODE_CH_LSB			(1U << 16)	/* 2b */
+
+/* AP2MD_PEER_WAKEUP (0x10006000 + 0x41C) */
+#define AP2MD_PEER_WAKEUP_LSB			(1U << 0)	/* 1b */
+
+/* ULPOSC_CON (0x10006000 + 0x420) */
+#define ULPOSC_EN_LSB				(1U << 0)	/* 1b */
+#define ULPOSC_RST_LSB				(1U << 1)	/* 1b */
+#define ULPOSC_CG_EN_LSB			(1U << 2)	/* 1b */
+#define ULPOSC_CLK_SEL_LSB			(1U << 3)	/* 1b */
+
+/* SPM2MM_CON (0x10006000 + 0x424) */
+#define SPM2MM_FORCE_ULTRA_LSB			(1U << 0)	/* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB			(1U << 1)	/* 1b */
+#define SPM2MM_ULTRAREQ_LSB			(1U << 2)	/* 1b */
+#define SPM2MD_ULTRAREQ_LSB			(1U << 3)	/* 1b */
+#define SPM2ISP_ULTRAREQ_LSB			(1U << 4)	/* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB		(1U << 16)	/* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB		(1U << 17)	/* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB		(1U << 18)	/* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB			(1U << 19)	/* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB			(1U << 20)	/* 1b */
+
+/* SPM_BUS_PROTECT5_MASK_B (0x10006000 + 0x428) */
+#define SPM_BUS_PROTECT5_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM2MCUPM_CON (0x10006000 + 0x42C) */
+#define SPM2MCUPM_SW_RST_B_LSB			(1U << 0)	/* 1b */
+#define SPM2MCUPM_SW_INT_LSB			(1U << 1)	/* 1b */
+
+/* AP_MDSRC_REQ (0x10006000 + 0x430) */
+#define AP_MDSMSRC_REQ_LSB			(1U << 0)	/* 1b */
+#define AP_L1SMSRC_REQ_LSB			(1U << 1)	/* 1b */
+#define AP_MD2SRC_REQ_LSB			(1U << 2)	/* 1b */
+#define AP_MDSMSRC_ACK_LSB			(1U << 4)	/* 1b */
+#define AP_L1SMSRC_ACK_LSB			(1U << 5)	/* 1b */
+#define AP_MD2SRC_ACK_LSB			(1U << 6)	/* 1b */
+
+/* SPM2EMI_ENTER_ULPM (0x10006000 + 0x434) */
+#define SPM2EMI_ENTER_ULPM_LSB			(1U << 0)	/* 1b */
+
+/* SPM2MD_DVFS_CON (0x10006000 + 0x438) */
+#define SPM2MD_DVFS_CON_LSB			(1U << 0)	/* 32b */
+
+/* MD2SPM_DVFS_CON (0x10006000 + 0x43C) */
+#define MD2SPM_DVFS_CON_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT6_MASK_B (0x10006000 + 0X440) */
+#define SPM_BUS_PROTECT6_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT7_MASK_B (0x10006000 + 0x444) */
+#define SPM_BUS_PROTECT7_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_BUS_PROTECT8_MASK_B (0x10006000 + 0x448) */
+#define SPM_BUS_PROTECT8_MASK_B_LSB		(1U << 0)	/* 32b */
+
+/* SPM_PLL_CON (0x10006000 + 0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB			(1U << 0)	/* 1b */
+#define SC_UNIPLLOUT_OFF_LSB			(1U << 1)	/* 1b */
+#define SC_SPAREPLLOUT_OFF_LSB			(1U << 2)	/* 2b */
+#define SC_MAINPLL_OFF_LSB			(1U << 4)	/* 1b */
+#define SC_UNIPLL_OFF_LSB			(1U << 5)	/* 1b */
+#define SC_SPAREPLL_OFF_LSB			(1U << 6)	/* 2b */
+#define SC_MAINPLL_S_OFF_LSB			(1U << 8)	/* 1b */
+#define SC_UNIPLL_S_OFF_LSB			(1U << 9)	/* 1b */
+#define SC_SPAREPLL_S_OFF_LSB			(1U << 10)	/* 2b */
+#define SC_SPARE_CK_OFF_LSB			(1U << 12)	/* 4b */
+#define SC_SMI_CK_OFF_LSB			(1U << 16)	/* 1b */
+#define SC_MD32K_CK_OFF_LSB			(1U << 17)	/* 1b */
+#define SC_CKSQ1_OFF_LSB			(1U << 18)	/* 1b */
+#define SC_AXI_MEM_CK_OFF_LSB			(1U << 19)	/* 1b */
+#define SC_CLK_BACKUP_LSB			(1U << 20)	/* 12b */
+
+/* RC_SPM_CTRL (0x10006000 + 0x450) */
+#define SPM_AP_26M_RDY_LSB			(1U << 0)	/* 1b */
+#define SPM2RC_DMY_CTRL_LSB			(1U << 2)	/* 6b */
+#define RC2SPM_SRCCLKENO_0_ACK_LSB		(1U << 16)	/* 1b */
+
+/* SPM_DRAM_MCU_SW_CON_0 (0x10006000 + 0x454) */
+#define SW_DDR_PST_REQ_LSB			(1U << 0)	/* 2b */
+#define SW_DDR_PST_ABORT_REQ_LSB		(1U << 2)	/* 2b */
+
+/* SPM_DRAM_MCU_SW_CON_1 (0x10006000 + 0x458) */
+#define SW_DDR_PST_CH0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_CON_2 (0x10006000 + 0x45C) */
+#define SW_DDR_PST_CH1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_CON_3 (0x10006000 + 0x460) */
+#define SW_DDR_RESERVED_CH0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_CON_4 (0x10006000 + 0x464) */
+#define SW_DDR_RESERVED_CH1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_STA_0 (0x10006000 + 0x468) */
+#define SC_DDR_PST_ACK_LSB			(1U << 0)	/* 2b */
+#define SC_DDR_PST_ABORT_ACK_LSB		(1U << 2)	/* 2b */
+
+/* SPM_DRAM_MCU_STA_1 (0x10006000 + 0x46C) */
+#define SC_DDR_CUR_PST_STA_CH0_LSB		(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_STA_2 (0x10006000 + 0x470) */
+#define SC_DDR_CUR_PST_STA_CH1_LSB		(1U << 0)	/* 32b */
+
+/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000 + 0x474) */
+#define SW_DDR_PST_REQ_SEL_LSB			(1U << 0)	/* 2b */
+#define SW_DDR_PST_SEL_LSB			(1U << 2)	/* 2b */
+#define SW_DDR_PST_ABORT_REQ_SEL_LSB		(1U << 4)	/* 2b */
+#define SW_DDR_RESERVED_SEL_LSB			(1U << 6)	/* 2b */
+#define SW_DDR_PST_ACK_SEL_LSB			(1U << 8)	/* 2b */
+#define SW_DDR_PST_ABORT_ACK_SEL_LSB		(1U << 10)	/* 2b */
+
+/* RELAY_DVFS_LEVEL (0x10006000 + 0x478) */
+#define RELAY_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000 + 0x480) */
+#define SW_PHYPLL_EN_LSB			(1U << 0)	/* 2b */
+#define SW_DPY_VREF_EN_LSB			(1U << 2)	/* 2b */
+#define SW_DPY_DLL_CK_EN_LSB			(1U << 4)	/* 2b */
+#define SW_DPY_DLL_EN_LSB			(1U << 6)	/* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB			(1U << 8)	/* 2b */
+#define SW_MEM_CK_OFF_LSB			(1U << 10)	/* 2b */
+#define SW_DMSUS_OFF_LSB			(1U << 12)	/* 2b */
+#define SW_DPY_MODE_SW_LSB			(1U << 14)	/* 2b */
+#define SW_EMI_CLK_OFF_LSB			(1U << 16)	/* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB			(1U << 18)	/* 2b */
+#define SW_DR_GATE_RETRY_EN_LSB			(1U << 20)	/* 2b */
+#define SW_DPHY_PRECAL_UP_LSB			(1U << 24)	/* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB			(1U << 26)	/* 2b */
+#define SW_TX_TRACKING_DIS_LSB			(1U << 28)	/* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB		(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000 + 0x484) */
+#define SW_SHU_RESTORE_LSB			(1U << 0)	/* 2b */
+#define SW_DMYRD_MOD_LSB			(1U << 2)	/* 2b */
+#define SW_DMYRD_INTV_LSB			(1U << 4)	/* 2b */
+#define SW_DMYRD_EN_LSB				(1U << 6)	/* 2b */
+#define SW_DRS_DIS_REQ_LSB			(1U << 8)	/* 2b */
+#define SW_DR_SRAM_LOAD_LSB			(1U << 10)	/* 2b */
+#define SW_DR_SRAM_RESTORE_LSB			(1U << 12)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB		(1U << 14)	/* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB		(1U << 16)	/* 2b */
+#define SW_DPY_MIDPI_EN_LSB			(1U << 18)	/* 2b */
+#define SW_DPY_PI_RESETB_EN_LSB			(1U << 20)	/* 2b */
+#define SW_DPY_MCK8X_EN_LSB			(1U << 22)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB		(1U << 24)	/* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB		(1U << 28)	/* 4b */
+
+/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000 + 0x488) */
+#define SW_DR_SHU_LEVEL_LSB			(1U << 0)	/* 2b */
+#define SW_DR_SHU_EN_LSB			(1U << 2)	/* 1b */
+#define SW_DR_SHORT_QUEUE_LSB			(1U << 3)	/* 1b */
+#define SW_PHYPLL_MODE_SW_LSB			(1U << 4)	/* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB			(1U << 5)	/* 1b */
+#define SW_PHYPLL_SHU_EN_LSB			(1U << 6)	/* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB			(1U << 7)	/* 1b */
+#define SW_DR_RESERVED_0_LSB			(1U << 24)	/* 2b */
+#define SW_DR_RESERVED_1_LSB			(1U << 26)	/* 2b */
+#define SW_DR_RESERVED_2_LSB			(1U << 28)	/* 2b */
+#define SW_DR_RESERVED_3_LSB			(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000 + 0x48C) */
+#define SC_DR_SHU_EN_ACK_LSB			(1U << 0)	/* 4b */
+#define SC_EMI_CLK_OFF_ACK_LSB			(1U << 4)	/* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB		(1U << 8)	/* 4b */
+#define SC_DRAMC_DFS_STA_LSB			(1U << 12)	/* 4b */
+#define SC_DRS_DIS_ACK_LSB			(1U << 16)	/* 4b */
+#define SC_DR_SRAM_LOAD_ACK_LSB			(1U << 20)	/* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB		(1U << 24)	/* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB		(1U << 28)	/* 4b */
+
+/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000 + 0x490) */
+#define SW_PHYPLL_EN_SEL_LSB			(1U << 0)	/* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB			(1U << 2)	/* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB		(1U << 4)	/* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB			(1U << 6)	/* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB		(1U << 8)	/* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB			(1U << 10)	/* 2b */
+#define SW_DMSUS_OFF_SEL_LSB			(1U << 12)	/* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB			(1U << 14)	/* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB			(1U << 16)	/* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB		(1U << 18)	/* 2b */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB		(1U << 20)	/* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB		(1U << 24)	/* 2b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB		(1U << 26)	/* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB		(1U << 28)	/* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB	(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000 + 0x494) */
+#define SW_SHU_RESTORE_SEL_LSB			(1U << 0)	/* 2b */
+#define SW_DMYRD_MOD_SEL_LSB			(1U << 2)	/* 2b */
+#define SW_DMYRD_INTV_SEL_LSB			(1U << 4)	/* 2b */
+#define SW_DMYRD_EN_SEL_LSB			(1U << 6)	/* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB			(1U << 8)	/* 2b */
+#define SW_DR_SRAM_LOAD_SEL_LSB			(1U << 10)	/* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB		(1U << 12)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB	(1U << 14)	/* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB		(1U << 16)	/* 2b */
+#define SW_DPY_MIDPI_EN_SEL_LSB			(1U << 18)	/* 2b */
+#define SW_DPY_PI_RESETB_EN_SEL_LSB		(1U << 20)	/* 2b */
+#define SW_DPY_MCK8X_EN_SEL_LSB			(1U << 22)	/* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB		(1U << 24)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000 + 0x498) */
+#define SW_DR_SHU_LEVEL_SEL_LSB			(1U << 0)	/* 1b */
+#define SW_DR_SHU_EN_SEL_LSB			(1U << 2)	/* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB		(1U << 3)	/* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB		(1U << 4)	/* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB		(1U << 5)	/* 1b */
+#define SW_PHYPLL_SHU_EN_SEL_LSB		(1U << 6)	/* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB		(1U << 7)	/* 1b */
+#define SW_DR_RESERVED_0_SEL_LSB		(1U << 24)	/* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB		(1U << 26)	/* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB		(1U << 28)	/* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB		(1U << 30)	/* 2b */
+
+/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000 + 0x49C) */
+#define SC_DR_SHU_EN_ACK_SEL_LSB		(1U << 0)	/* 4b */
+#define SC_EMI_CLK_OFF_ACK_SEL_LSB		(1U << 4)	/* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB		(1U << 8)	/* 4b */
+#define SC_DRAMC_DFS_STA_SEL_LSB		(1U << 12)	/* 4b */
+#define SC_DRS_DIS_ACK_SEL_LSB			(1U << 16)	/* 4b */
+#define SC_DR_SRAM_LOAD_ACK_SEL_LSB		(1U << 20)	/* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB		(1U << 24)	/* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB		(1U << 28)	/* 4b */
+
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000 + 0x4A0) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB		(1U << 0)	/* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB		(1U << 1)	/* 1b */
+#define SC_DMYRD_EN_PCM_LSB			(1U << 2)	/* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB			(1U << 3)	/* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB		(1U << 4)	/* 4b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB		(1U << 8)	/* 1b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB		(1U << 9)	/* 1b */
+#define SC_DPY_MIDPI_EN_PCM_LSB			(1U << 10)	/* 1b */
+#define SC_DPY_PI_RESETB_EN_PCM_LSB		(1U << 11)	/* 1b */
+#define SC_DPY_MCK8X_EN_PCM_LSB			(1U << 12)	/* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB		(1U << 13)	/* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB		(1U << 14)	/* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB		(1U << 15)	/* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB		(1U << 16)	/* 1b */
+#define SC_DMDRAMCSHU_ACK_ALL_LSB		(1U << 24)	/* 1b */
+#define SC_EMI_CLK_OFF_ACK_ALL_LSB		(1U << 25)	/* 1b */
+#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB		(1U << 26)	/* 1b */
+#define SC_DRAMC_DFS_STA_ALL_LSB		(1U << 27)	/* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB			(1U << 28)	/* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB		(1U << 29)	/* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB		(1U << 30)	/* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB		(1U << 31)	/* 1b */
+
+/* SPM_DVFS_LEVEL (0x10006000 + 0x4A4) */
+#define SPM_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_CIRQ_CON (0x10006000 + 0x4A8) */
+#define CIRQ_CLK_SEL_LSB			(1U << 0)	/* 1b */
+
+/* SPM_DVFS_MISC (0x10006000 + 0x4AC) */
+#define MSDC_DVFS_REQUEST_LSB			(1U << 0)	/* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB			(1U << 1)	/* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB		(1U << 2)	/* 1b */
+#define FORCE_DVFS_WAKE_LSB			(1U << 3)	/* 1b */
+#define SPM_DVFSRC_ENABLE_LSB			(1U << 4)	/* 1b */
+#define SPM_DVFS_DONE_LSB			(1U << 5)	/* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB	(1U << 6)	/* 1b */
+#define SPM2RC_EVENT_ABORT_LSB			(1U << 7)	/* 1b */
+#define EMI_SLP_IDLE_LSB			(1U << 14)	/* 1b */
+#define SDIO_READY_TO_SPM_LSB			(1U << 15)	/* 1b */
+
+/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000 + 0x4B4) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000 + 0x4B8) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000 + 0x4BC) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000 + 0x4C0) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000 + 0x4C4) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000 + 0x4C8) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000 + 0x4CC) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000 + 0x4D0) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000 + 0x4D4) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000 + 0x4D8) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000 + 0x4DC) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB	(1U << 0)	/* 32b */
+
+/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000 + 0x4E0) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB	(1U << 0)	/* 32b */
+
+/* PWR_STATUS_MASK_REQ_0 (0x10006000 + 0x4E4) */
+#define PWR_STATUS_MASK_REQ_0_LSB		(1U << 0)	/* 32b */
+
+/* PWR_STATUS_MASK_REQ_1 (0x10006000 + 0x4E8) */
+#define PWR_STATUS_MASK_REQ_1_LSB		(1U << 0)	/* 32b */
+
+/* PWR_STATUS_MASK_REQ_2 (0x10006000 + 0x4EC) */
+#define PWR_STATUS_MASK_REQ_2_LSB		(1U << 0)	/* 32b */
+
+/* SPM_CG_CHECK_CON (0x10006000 + 0x4F0) */
+#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB		(1U << 0)	/* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB		(1U << 8)	/* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB		(1U << 16)	/* 5b */
+#define AUDIOSYS_BUSY_MASK_REQ_0_LSB		(1U << 24)	/* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_1_LSB		(1U << 25)	/* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_2_LSB		(1U << 26)	/* 1b */
+#define SSUSB_BUSY_MASK_REQ_0_LSB		(1U << 27)	/* 1b */
+#define SSUSB_BUSY_MASK_REQ_1_LSB		(1U << 28)	/* 1b */
+#define SSUSB_BUSY_MASK_REQ_2_LSB		(1U << 29)	/* 1b */
+
+/* SPM_SRC_RDY_STA (0x10006000 + 0x4F4) */
+#define SPM_INFRA_INTERNAL_ACK_LSB		(1U << 0)	/* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB		(1U << 1)	/* 1b */
+
+/* SPM_DVS_DFS_LEVEL (0x10006000 + 0x4F8) */
+#define SPM_DFS_LEVEL_LSB			(1U << 0)	/* 16b */
+#define SPM_DVS_LEVEL_LSB			(1U << 16)	/* 16b */
+
+/* SPM_FORCE_DVFS (0x10006000 + 0x4FC) */
+#define FORCE_DVFS_LEVEL_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_FLAG_0 (0x10006000 + 0x600) */
+#define SPM_SW_FLAG_LSB				(1U << 0)	/* 32b */
+
+/* SPM_SW_DEBUG_0 (0x10006000 + 0x604) */
+#define SPM_SW_DEBUG_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_FLAG_1 (0x10006000 + 0x608) */
+#define SPM_SW_FLAG_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_DEBUG_1 (0x10006000 + 0x60C) */
+#define SPM_SW_DEBUG_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_0 (0x10006000 + 0x610) */
+#define SPM_SW_RSV_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_1 (0x10006000 + 0x614) */
+#define SPM_SW_RSV_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_2 (0x10006000 + 0x618) */
+#define SPM_SW_RSV_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_3 (0x10006000 + 0x61C) */
+#define SPM_SW_RSV_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_4 (0x10006000 + 0x620) */
+#define SPM_SW_RSV_4_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_5 (0x10006000 + 0x624) */
+#define SPM_SW_RSV_5_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_6 (0x10006000 + 0x628) */
+#define SPM_SW_RSV_6_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_7 (0x10006000 + 0x62C) */
+#define SPM_SW_RSV_7_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SW_RSV_8 (0x10006000 + 0x630) */
+#define SPM_SW_RSV_8_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_WAKE_EVENT (0x10006000 + 0x634) */
+#define SPM_BK_WAKE_EVENT_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_VTCXO_DUR (0x10006000 + 0x638) */
+#define SPM_BK_VTCXO_DUR_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_WAKE_MISC (0x10006000 + 0x63C) */
+#define SPM_BK_WAKE_MISC_LSB			(1U << 0)	/* 32b */
+
+/* SPM_BK_PCM_TIMER (0x10006000 + 0x640) */
+#define SPM_BK_PCM_TIMER_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_CON_0 (0x10006000 + 0x650) */
+#define SPM_RSV_CON_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_CON_1 (0x10006000 + 0x654) */
+#define SPM_RSV_CON_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_STA_0 (0x10006000 + 0x658) */
+#define SPM_RSV_STA_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_RSV_STA_1 (0x10006000 + 0x65C) */
+#define SPM_RSV_STA_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_CON (0x10006000 + 0x660) */
+#define SPM_SPARE_CON_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_CON_SET (0x10006000 + 0x664) */
+#define SPM_SPARE_CON_SET_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_CON_CLR (0x10006000 + 0x668) */
+#define SPM_SPARE_CON_CLR_LSB			(1U << 0)	/* 32b */
+
+/* SPM_CROSS_WAKE_M00_REQ (0x10006000 + 0x66C) */
+#define SPM_CROSS_WAKE_M00_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M00_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SPM_CROSS_WAKE_M01_REQ (0x10006000 + 0x670) */
+#define SPM_CROSS_WAKE_M01_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M01_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SPM_CROSS_WAKE_M02_REQ (0x10006000 + 0x674) */
+#define SPM_CROSS_WAKE_M02_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M02_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SPM_CROSS_WAKE_M03_REQ (0x10006000 + 0x678) */
+#define SPM_CROSS_WAKE_M03_REQ_LSB		(1U << 0)	/* 4b */
+#define SPM_CROSS_WAKE_M03_CHK_LSB		(1U << 4)	/* 4b */
+
+/* SCP_VCORE_LEVEL (0x10006000 + 0x67C) */
+#define SCP_VCORE_LEVEL_LSB			(1U << 0)	/* 16b */
+
+/* SC_MM_CK_SEL_CON (0x10006000 + 0x680) */
+#define SC_MM_CK_SEL_LSB			(1U << 0)	/* 4b */
+#define SC_MM_CK_SEL_EN_LSB			(1U << 4)	/* 1b */
+
+/* SPARE_ACK_MASK (0x10006000 + 0x684) */
+#define SPARE_ACK_MASK_B_LSB			(1U << 0)	/* 32b */
+
+/* SPM_SPARE_FUNCTION (0x10006000 + 0x688) */
+#define SPM_SPARE_FUNCTION_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DV_CON_0 (0x10006000 + 0x68C) */
+#define SPM_DV_CON_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DV_CON_1 (0x10006000 + 0x690) */
+#define SPM_DV_CON_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DV_STA (0x10006000 + 0x694) */
+#define SPM_DV_STA_LSB				(1U << 0)	/* 32b */
+
+/* CONN_XOWCN_DEBUG_EN (0x10006000 + 0x698) */
+#define CONN_XOWCN_DEBUG_EN_LSB			(1U << 0)	/* 1b */
+
+/* SPM_SEMA_M0 (0x10006000 + 0x69C) */
+#define SPM_SEMA_M0_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M1 (0x10006000 + 0x6A0) */
+#define SPM_SEMA_M1_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M2 (0x10006000 + 0x6A4) */
+#define SPM_SEMA_M2_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M3 (0x10006000 + 0x6A8) */
+#define SPM_SEMA_M3_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M4 (0x10006000 + 0x6AC) */
+#define SPM_SEMA_M4_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M5 (0x10006000 + 0x6B0) */
+#define SPM_SEMA_M5_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M6 (0x10006000 + 0x6B4) */
+#define SPM_SEMA_M6_LSB				(1U << 0)	/* 8b */
+
+/* SPM_SEMA_M7 (0x10006000 + 0x6B8) */
+#define SPM_SEMA_M7_LSB				(1U << 0)	/* 8b */
+
+/* SPM2ADSP_MAILBOXi (0x10006000 + 0x6BC) */
+#define SPM2ADSP_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* ADSP2SPM_MAILBOX (0x10006000 + 0x6C0) */
+#define ADSP2SPM_MAILBOX_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ADSP_IRQ (0x10006000 + 0x6C4) */
+#define SC_SPM2ADSP_WAKEUP_LSB			(1U << 0)	/* 1b */
+#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB	(1U << 4)	/* 1b */
+
+/* SPM_MD32_IRQ (0x10006000 + 0x6C8) */
+#define SC_SPM2SSPM_WAKEUP_LSB			(1U << 0)	/* 4b */
+#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB	(1U << 4)	/* 4b */
+
+/* SPM2PMCU_MAILBOX_0 (0x10006000 + 0x6CC) */
+#define SPM2PMCU_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM2PMCU_MAILBOX_1 (0x10006000 + 0x6D0) */
+#define SPM2PMCU_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM2PMCU_MAILBOX_2 (0x10006000 + 0x6D4) */
+#define SPM2PMCU_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM2PMCU_MAILBOX_3 (0x10006000 + 0x6D8) */
+#define SPM2PMCU_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_0 (0x10006000 + 0x6DC) */
+#define PMCU2SPM_MAILBOX_0_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_1 (0x10006000 + 0x6E0) */
+#define PMCU2SPM_MAILBOX_1_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_2 (0x10006000 + 0x6E4) */
+#define PMCU2SPM_MAILBOX_2_LSB			(1U << 0)	/* 32b */
+
+/* PMCU2SPM_MAILBOX_3 (0x10006000 + 0x6E8) */
+#define PMCU2SPM_MAILBOX_3_LSB			(1U << 0)	/* 32b */
+
+/* UFS_PSRI_SW (0x10006000 + 0x6EC) */
+#define UFS_PSRI_SW_LSB				(1U << 0)	/* 1b */
+
+/* UFS_PSRI_SW_SET (0x10006000 + 0x6F0) */
+#define UFS_PSRI_SW_SET_LSB			(1U << 0)	/* 1b */
+
+/* UFS_PSRI_SW_CLR (0x10006000 + 0x6F4) */
+#define UFS_PSRI_SW_CLR_LSB			(1U << 0)	/* 1b */
+
+/* SPM_AP_SEMA (0x10006000 + 0x6F8) */
+#define SPM_AP_SEMA_LSB				(1U << 0)	/* 1b */
+
+/* SPM_SPM_SEMA (0x10006000 + 0x6FC) */
+#define SPM_SPM_SEMA_LSB			(1U << 0)	/* 1b */
+
+/* SPM_DVFS_CON (0x10006000 + 0x700) */
+#define SPM_DVFS_CON_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CON_STA (0x10006000 + 0x704) */
+#define SPM_DVFS_CON_STA_LSB			(1U << 0)	/* 32b */
+
+/* SPM_PMIC_SPMI_CON (0x10006000 + 0x708) */
+#define SPM_PMIC_SPMI_CMD_LSB			(1U << 0)	/* 2b */
+#define SPM_PMIC_SPMI_SLAVEID_LSB		(1U << 2)	/* 4b */
+#define SPM_PMIC_SPMI_PMIFID_LSB		(1U << 6)	/* 1b */
+#define SPM_PMIC_SPMI_DBCNT_LSB			(1U << 7)	/* 1b */
+
+/* SPM_DVFS_CMD0 (0x10006000 + 0x710) */
+#define SPM_DVFS_CMD0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD1 (0x10006000 + 0x714) */
+#define SPM_DVFS_CMD1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD2 (0x10006000 + 0x718) */
+#define SPM_DVFS_CMD2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD3 (0x10006000 + 0x71C) */
+#define SPM_DVFS_CMD3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD4 (0x10006000 + 0x720) */
+#define SPM_DVFS_CMD4_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD5 (0x10006000 + 0x724) */
+#define SPM_DVFS_CMD5_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD6 (0x10006000 + 0x728) */
+#define SPM_DVFS_CMD6_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD7 (0x10006000 + 0x72C) */
+#define SPM_DVFS_CMD7_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD8 (0x10006000 + 0x730) */
+#define SPM_DVFS_CMD8_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD9 (0x10006000 + 0x734) */
+#define SPM_DVFS_CMD9_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD10 (0x10006000 + 0x738) */
+#define SPM_DVFS_CMD10_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD11 (0x10006000 + 0x73C) */
+#define SPM_DVFS_CMD11_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD12 (0x10006000 + 0x740) */
+#define SPM_DVFS_CMD12_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD13 (0x10006000 + 0x744) */
+#define SPM_DVFS_CMD13_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD14 (0x10006000 + 0x748) */
+#define SPM_DVFS_CMD14_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD15 (0x10006000 + 0x74C) */
+#define SPM_DVFS_CMD15_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD16i (0x10006000 + 0x750) */
+#define SPM_DVFS_CMD16_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD17 (0x10006000 + 0x754) */
+#define SPM_DVFS_CMD17_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD18 (0x10006000 + 0x758) */
+#define SPM_DVFS_CMD18_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD19 (0x10006000 + 0x75C) */
+#define SPM_DVFS_CMD19_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD20 (0x10006000 + 0x760) */
+#define SPM_DVFS_CMD20_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD21 (0x10006000 + 0x764) */
+#define SPM_DVFS_CMD21_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD22 (0x10006000 + 0x768) */
+#define SPM_DVFS_CMD22_LSB			(1U << 0)	/* 32b */
+
+/* SPM_DVFS_CMD23 (0x10006000 + 0x76C) */
+#define SPM_DVFS_CMD23_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_VALUE_L (0x10006000 + 0x770) */
+#define SYS_TIMER_VALUE_L_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_VALUE_H (0x10006000 + 0x774) */
+#define SYS_TIMER_VALUE_H_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_START_L (0x10006000 + 0x778) */
+#define SYS_TIMER_START_L_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_START_H (0x10006000 + 0x77C) */
+#define SYS_TIMER_START_H_LSB			(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_00 (0x10006000 + 0x780) */
+#define SYS_TIMER_LATCH_L_00_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_00 (0x10006000 + 0x784) */
+#define SYS_TIMER_LATCH_H_00_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_01 (0x10006000 + 0x788) */
+#define SYS_TIMER_LATCH_L_01_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_01 (0x10006000 + 0x78C) */
+#define SYS_TIMER_LATCH_H_01_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_02 (0x10006000 + 0x790) */
+#define SYS_TIMER_LATCH_L_02_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_02 (0x10006000 + 0x794) */
+#define SYS_TIMER_LATCH_H_02_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_03 (0x10006000 + 0x798) */
+#define SYS_TIMER_LATCH_L_03_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_03 (0x10006000 + 0x79C) */
+#define SYS_TIMER_LATCH_H_03_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_04 (0x10006000 + 0x7A0) */
+#define SYS_TIMER_LATCH_L_04_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_04 (0x10006000 + 0x7A4) */
+#define SYS_TIMER_LATCH_H_04_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_05 (0x10006000 + 0x7A8) */
+#define SYS_TIMER_LATCH_L_05_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_05 (0x10006000 + 0x7AC) */
+#define SYS_TIMER_LATCH_H_05_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_06 (0x10006000 + 0x7B0) */
+#define SYS_TIMER_LATCH_L_06_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_06 (0x10006000 + 0x7B4) */
+#define SYS_TIMER_LATCH_H_06_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_07 (0x10006000 + 0x7B8) */
+#define SYS_TIMER_LATCH_L_07_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_07 (0x10006000 + 0x7BC) */
+#define SYS_TIMER_LATCH_H_07_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_08 (0x10006000 + 0x7C0) */
+#define SYS_TIMER_LATCH_L_08_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_08 (0x10006000 + 0x7C4) */
+#define SYS_TIMER_LATCH_H_08_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_09 (0x10006000 + 0x7C8) */
+#define SYS_TIMER_LATCH_L_09_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_09 (0x10006000 + 0x7CC) */
+#define SYS_TIMER_LATCH_H_09_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_10 (0x10006000 + 0x7D0) */
+#define SYS_TIMER_LATCH_L_10_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_10 (0x10006000 + 0x7D4) */
+#define SYS_TIMER_LATCH_H_10_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_11 (0x10006000 + 0x7D8) */
+#define SYS_TIMER_LATCH_L_11_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_11 (0x10006000 + 0x7DC) */
+#define SYS_TIMER_LATCH_H_11_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_12 (0x10006000 + 0x7E0) */
+#define SYS_TIMER_LATCH_L_12_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_12 (0x10006000 + 0x7E4) */
+#define SYS_TIMER_LATCH_H_12_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_13 (0x10006000 + 0x7E8) */
+#define SYS_TIMER_LATCH_L_13_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_13 (0x10006000 + 0x7EC) */
+#define SYS_TIMER_LATCH_H_13_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_14 (0x10006000 + 0x7F0) */
+#define SYS_TIMER_LATCH_L_14_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_14 (0x10006000 + 0x7F4) */
+#define SYS_TIMER_LATCH_H_14_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_L_15 (0x10006000 + 0x7F8) */
+#define SYS_TIMER_LATCH_L_15_LSB		(1U << 0)	/* 32b */
+
+/* SYS_TIMER_LATCH_H_15 (0x10006000 + 0x7FC) */
+#define SYS_TIMER_LATCH_H_15_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_0 (0x10006000 + 0x800) */
+#define PCM_WDT_LATCH_0_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_1 (0x10006000 + 0x804) */
+#define PCM_WDT_LATCH_1_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_2 (0x10006000 + 0x808) */
+#define PCM_WDT_LATCH_2_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_3 (0x10006000 + 0x80C) */
+#define PCM_WDT_LATCH_3_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_4 (0x10006000 + 0x810) */
+#define PCM_WDT_LATCH_4_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_5 (0x10006000 + 0x814) */
+#define PCM_WDT_LATCH_5_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_6 (0x10006000 + 0x818) */
+#define PCM_WDT_LATCH_6_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_7 (0x10006000 + 0x81C) */
+#define PCM_WDT_LATCH_7_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_8 (0x10006000 + 0x820) */
+#define PCM_WDT_LATCH_8_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_9 (0x10006000 + 0x824) */
+#define PCM_WDT_LATCH_9_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_10 (0x10006000 + 0x828) */
+#define PCM_WDT_LATCH_10_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_11 (0x10006000 + 0x82C) */
+#define PCM_WDT_LATCH_11_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_12 (0x10006000 + 0x830) */
+#define PCM_WDT_LATCH_12_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_13 (0x10006000 + 0x834) */
+#define PCM_WDT_LATCH_13_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_14 (0x10006000 + 0x838) */
+#define PCM_WDT_LATCH_14_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_15 (0x10006000 + 0x83C) */
+#define PCM_WDT_LATCH_15_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_16 (0x10006000 + 0x840) */
+#define PCM_WDT_LATCH_16_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_17 (0x10006000 + 0x844) */
+#define PCM_WDT_LATCH_17_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_18 (0x10006000 + 0x848) */
+#define PCM_WDT_LATCH_18_LSB			(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000 + 0x84C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000 + 0x850) */
+#define PCM_WDT_LATCH_SPARE_1_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000 + 0x854) */
+#define PCM_WDT_LATCH_SPARE_2_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_CONN_0 (0x10006000 + 0x870) */
+#define PCM_WDT_LATCH_CONN_0_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_CONN_1 (0x10006000 + 0x874) */
+#define PCM_WDT_LATCH_CONN_1_LSB		(1U << 0)	/* 32b */
+
+/* PCM_WDT_LATCH_CONN_2 (0x10006000 + 0x878) */
+#define PCM_WDT_LATCH_CONN_2_LSB		(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000 + 0x8A0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000 + 0x8A4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000 + 0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000 + 0x8AC) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000 + 0x8B0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000 + 0x8B4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000 + 0x8B8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB	(1U << 0)	/* 32b */
+
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000 + 0x8F4) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB	(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_0 (0x10006000 + 0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_0 (0x10006000 + 0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_0 (0x10006000 + 0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_0 (0x10006000 + 0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_0 (0x10006000 + 0x910) */
+#define SPM_ACK_CHK_STA_0_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_0 (0x10006000 + 0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB		(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_1 (0x10006000 + 0x918) */
+#define SPM_ACK_CHK_SW_EN_1_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_1 (0x10006000 + 0x91C) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_1 (0x10006000 + 0x920) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_1 (0x10006000 + 0x924) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_1 (0x10006000 + 0x928) */
+#define SPM_ACK_CHK_STA_1_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_1 (0x10006000 + 0x92C) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB		(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_2 (0x10006000 + 0x930) */
+#define SPM_ACK_CHK_SW_EN_2_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_2 (0x10006000 + 0x934) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_2 (0x10006000 + 0x938) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_2 (0x10006000 + 0x93C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_2 (0x10006000 + 0x940) */
+#define SPM_ACK_CHK_STA_2_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_2 (0x10006000 + 0x944) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB		(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_CON_3 (0x10006000 + 0x948) */
+#define SPM_ACK_CHK_SW_EN_3_LSB			(1U << 0)	/* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB		(1U << 1)	/* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB		(1U << 2)	/* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB		(1U << 3)	/* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB		(1U << 4)	/* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB		(1U << 5)	/* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB		(1U << 6)	/* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB	(1U << 7)	/* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB			(1U << 8)	/* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB		(1U << 9)	/* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB			(1U << 15)	/* 1b */
+
+/* SPM_ACK_CHK_PC_3 (0x10006000 + 0x94C) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB	(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB	(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_SEL_3 (0x10006000 + 0x950) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB	(1U << 0)	/* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB	(1U << 5)	/* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB	(1U << 16)	/* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB	(1U << 21)	/* 3b */
+
+/* SPM_ACK_CHK_TIMER_3 (0x10006000 + 0x954) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB		(1U << 0)	/* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB			(1U << 16)	/* 16b */
+
+/* SPM_ACK_CHK_STA_3 (0x10006000 + 0x958) */
+#define SPM_ACK_CHK_STA_3_LSB			(1U << 0)	/* 32b */
+
+/* SPM_ACK_CHK_SWINT_3 (0x10006000 + 0x95C) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB		(1U << 0)	/* 32b */
+
+/* SPM_COUNTER_0 (0x10006000 + 0x960) */
+#define SPM_COUNTER_VAL_0_LSB			(1U << 0)	/* 14b */
+#define SPM_COUNTER_OUT_0_LSB			(1U << 14)	/* 14b */
+#define SPM_COUNTER_EN_0_LSB			(1U << 28)	/* 1b */
+#define SPM_COUNTER_CLR_0_LSB			(1U << 29)	/* 1b */
+#define SPM_COUNTER_TIMEOUT_0_LSB		(1U << 30)	/* 1b */
+#define SPM_COUNTER_WAKEUP_EN_0_LSB		(1U << 31)	/* 1b */
+
+/* SPM_COUNTER_1 (0x10006000 + 0x964) */
+#define SPM_COUNTER_VAL_1_LSB			(1U << 0)	/* 14b */
+#define SPM_COUNTER_OUT_1_LSB			(1U << 14)	/* 14b */
+#define SPM_COUNTER_EN_1_LSB			(1U << 28)	/* 1b */
+#define SPM_COUNTER_CLR_1_LSB			(1U << 29)	/* 1b */
+#define SPM_COUNTER_TIMEOUT_1_LSB		(1U << 30)	/* 1b */
+#define SPM_COUNTER_WAKEUP_EN_1_LSB		(1U << 31)	/* 1b */
+
+/* SPM_COUNTER_2 (0x10006000 + 0x968) */
+#define SPM_COUNTER_VAL_2_LSB			(1U << 0)	/* 14b */
+#define SPM_COUNTER_OUT_2_LSB			(1U << 14)	/* 14b */
+#define SPM_COUNTER_EN_2_LSB			(1U << 28)	/* 1b */
+#define SPM_COUNTER_CLR_2_LSB			(1U << 29)	/* 1b */
+#define SPM_COUNTER_TIMEOUT_2_LSB		(1U << 30)	/* 1b */
+#define SPM_COUNTER_WAKEUP_EN_2_LSB		(1U << 31)	/* 1b */
+
+/* SYS_TIMER_CON (0x10006000 + 0x96C) */
+#define SYS_TIMER_START_EN_LSB			(1U << 0)	/* 1b */
+#define SYS_TIMER_LATCH_EN_LSB			(1U << 1)	/* 1b */
+#define SYS_TIMER_ID_LSB			(1U << 8)	/* 8b */
+#define SYS_TIMER_VALID_LSB			(1U << 31)	/* 1b */
+
+/* SPM_TWAM_CON (0x10006000 + 0x970) */
+#define REG_TWAM_ENABLE_LSB			(1U << 0)	/* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB		(1U << 1)	/* 1b */
+#define REG_TWAM_SW_RST_LSB			(1U << 2)	/* 1b */
+#define REG_TWAM_IRQ_MASK_LSB			(1U << 3)	/* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB			(1U << 4)	/* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB			(1U << 6)	/* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB			(1U << 8)	/* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB			(1U << 10)	/* 2b */
+
+/* SPM_TWAM_WINDOW_LEN (0x10006000 + 0x974) */
+#define REG_TWAM_WINDOW_LEN_LSB			(1U << 0)	/* 32b */
+
+/* SPM_TWAM_IDLE_SEL (0x10006000 + 0x978) */
+#define REG_TWAM_SIG_SEL_0_LSB			(1U << 0)	/* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB			(1U << 8)	/* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB			(1U << 16)	/* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB			(1U << 24)	/* 7b */
+
+/* SPM_TWAM_EVENT_CLEAR (0x10006000 + 0x97C) */
+#define SPM_TWAM_EVENT_CLEAR_LSB		(1U << 0)	/* 1b */
+
+/* OPP0_TABLE (0x10006000 + 0x980) */
+#define OPP0_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP1_TABLE (0x10006000 + 0x984) */
+#define OPP1_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP2_TABLE (0x10006000 + 0x988) */
+#define OPP2_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP3_TABLE (0x10006000 + 0x98C) */
+#define OPP3_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP4_TABLE (0x10006000 + 0x990) */
+#define OPP4_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP5_TABLE (0x10006000 + 0x994) */
+#define OPP5_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP6_TABLE (0x10006000 + 0x998) */
+#define OPP6_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP7_TABLE (0x10006000 + 0x99C) */
+#define OPP7_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP8_TABLE (0x10006000 + 0x9A0) */
+#define OPP8_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP9_TABLE (0x10006000 + 0x9A4) */
+#define OPP9_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP10_TABLE (0x10006000 + 0x9A8) */
+#define OPP10_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP11_TABLE (0x10006000 + 0x9AC) */
+#define OPP11_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP12_TABLE (0x10006000 + 0x9B0) */
+#define OPP12_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP13_TABLE (0x10006000 + 0x9B4) */
+#define OPP13_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP14_TABLE (0x10006000 + 0x9B8) */
+#define OPP14_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP15_TABLE (0x10006000 + 0x9BC) */
+#define OPP15_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP16_TABLE (0x10006000 + 0x9C0) */
+#define OPP16_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* OPP17_TABLE (0x10006000 + 0x9C4) */
+#define OPP17_TABLE_LSB				(1U << 0)	/* 32b */
+
+/* SHU0_ARRAY (0x10006000 + 0x9C8) */
+#define SHU0_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU1_ARRAY (0x10006000 + 0x9CC) */
+#define SHU1_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU2_ARRAY (0x10006000 + 0x9D0) */
+#define SHU2_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU3_ARRAY (0x10006000 + 0x9D4) */
+#define SHU3_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU4_ARRAY (0x10006000 + 0x9D8) */
+#define SHU4_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU5_ARRAY (0x10006000 + 0x9DC) */
+#define SHU5_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU6_ARRAY (0x10006000 + 0x9E0) */
+#define SHU6_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU7_ARRAY (0x10006000 + 0x9E4) */
+#define SHU7_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU8_ARRAY (0x10006000 + 0x9E8) */
+#define SHU8_ARRAY_LSB				(1U << 0)	/* 32b */
+
+/* SHU9_ARRAY (0x10006000 + 0x9EC) */
+#define SHU9_ARRAY_LSB				(1U << 0)	/* 32b */
+
+#define SPM_PROJECT_CODE			(0xb16)
+#define SPM_REGWR_CFG_KEY			(SPM_PROJECT_CODE << 16)
+
+#endif /* MT_SPM_REG */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_resource_req.h
new file mode 100644
index 0000000..d370daf
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_resource_req.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM	0U
+#define MT_SPM_BIT_26M		1U
+#define MT_SPM_BIT_INFRA	2U
+#define MT_SPM_BIT_SYSPLL	3U
+#define MT_SPM_BIT_DRAM_S0	4U
+#define MT_SPM_BIT_DRAM_S1	5U
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM	BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M	BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA	BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL	BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0	BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1	BIT(MT_SPM_BIT_DRAM_S1)
+
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.c b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.c
new file mode 100644
index 0000000..ef1fff8
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <uart.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG		\
+	(SPM_FLAG_DISABLE_INFRA_PDN |		\
+	 SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS |		\
+	 SPM_FLAG_USE_SRCCLKENO2)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1		(0U)
+
+#define SPM_SUSPEND_PCM_FLAG			\
+	(SPM_FLAG_DISABLE_VCORE_DVS |		\
+	 SPM_FLAG_DISABLE_VCORE_DFS)
+
+#define SPM_SUSPEND_PCM_FLAG1			(0U)
+
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__		\
+	(R12_PCM_TIMER |			\
+	 R12_KP_IRQ_B |				\
+	 R12_APWDT_EVENT_B |			\
+	 R12_CONN2AP_SPM_WAKEUP_B |		\
+	 R12_EINT_EVENT_B |			\
+	 R12_CONN_WDT_IRQ_B |			\
+	 R12_SSPM2SPM_WAKEUP_B |		\
+	 R12_SCP2SPM_WAKEUP_B |			\
+	 R12_ADSP2SPM_WAKEUP_B |		\
+	 R12_USBX_CDSC_B |			\
+	 R12_USBX_POWERDWN_B |			\
+	 R12_SYS_TIMER_EVENT_B |		\
+	 R12_EINT_EVENT_SECURE_B |		\
+	 R12_SYS_CIRQ_IRQ_B |			\
+	 R12_NNA_WAKEUP |			\
+	 R12_REG_CPU_WAKEUP)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND			\
+	(__WAKE_SRC_FOR_SUSPEND_COMMON__ |	\
+	 R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+	.wake_src = WAKE_SRC_FOR_SUSPEND,
+
+	/* Auto-gen Start */
+
+	/* SPM_AP_STANDBY_CON */
+	.reg_wfi_op = 0,
+	.reg_wfi_type = 0,
+	.reg_mp0_cputop_idle_mask = 0,
+	.reg_mp1_cputop_idle_mask = 0,
+	.reg_mcusys_idle_mask = 0,
+	.reg_md_apsrc_1_sel = 0,
+	.reg_md_apsrc_0_sel = 0,
+	.reg_conn_apsrc_sel = 0,
+
+	/* SPM_SRC6_MASK */
+	.reg_ccif_event_infra_req_mask_b = 0,
+	.reg_ccif_event_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC_REQ */
+	.reg_spm_apsrc_req = 1,
+	.reg_spm_f26m_req = 1,
+	.reg_spm_infra_req = 1,
+	.reg_spm_vrf18_req = 1,
+	.reg_spm_ddren_req = 1,
+	.reg_spm_dvfs_req = 0,
+	.reg_spm_sw_mailbox_req = 0,
+	.reg_spm_sspm_mailbox_req = 0,
+	.reg_spm_adsp_mailbox_req = 0,
+	.reg_spm_scp_mailbox_req = 0,
+
+	/* SPM_SRC_MASK */
+	.reg_md_0_srcclkena_mask_b = 0,
+	.reg_md_0_infra_req_mask_b = 0,
+	.reg_md_0_apsrc_req_mask_b = 0,
+	.reg_md_0_vrf18_req_mask_b = 0,
+	.reg_md_0_ddren_req_mask_b = 0,
+	.reg_md_1_srcclkena_mask_b = 0,
+	.reg_md_1_infra_req_mask_b = 0,
+	.reg_md_1_apsrc_req_mask_b = 0,
+	.reg_md_1_vrf18_req_mask_b = 0,
+	.reg_md_1_ddren_req_mask_b = 0,
+	.reg_conn_srcclkena_mask_b = 1,
+	.reg_conn_srcclkenb_mask_b = 0,
+	.reg_conn_infra_req_mask_b = 1,
+	.reg_conn_apsrc_req_mask_b = 1,
+	.reg_conn_vrf18_req_mask_b = 1,
+	.reg_conn_ddren_req_mask_b = 1,
+	.reg_conn_vfe28_mask_b = 0,
+	.reg_srcclkeni_srcclkena_mask_b = 1,
+	.reg_srcclkeni_infra_req_mask_b = 1,
+	.reg_infrasys_apsrc_req_mask_b = 0,
+	.reg_infrasys_ddren_req_mask_b = 1,
+	.reg_sspm_srcclkena_mask_b = 1,
+	.reg_sspm_infra_req_mask_b = 1,
+	.reg_sspm_apsrc_req_mask_b = 1,
+	.reg_sspm_vrf18_req_mask_b = 1,
+	.reg_sspm_ddren_req_mask_b = 1,
+
+	/* SPM_SRC2_MASK */
+	.reg_scp_srcclkena_mask_b = 1,
+	.reg_scp_infra_req_mask_b = 1,
+	.reg_scp_apsrc_req_mask_b = 1,
+	.reg_scp_vrf18_req_mask_b = 1,
+	.reg_scp_ddren_req_mask_b = 1,
+	.reg_audio_dsp_srcclkena_mask_b = 1,
+	.reg_audio_dsp_infra_req_mask_b = 1,
+	.reg_audio_dsp_apsrc_req_mask_b = 1,
+	.reg_audio_dsp_vrf18_req_mask_b = 1,
+	.reg_audio_dsp_ddren_req_mask_b = 1,
+	.reg_ufs_srcclkena_mask_b = 1,
+	.reg_ufs_infra_req_mask_b = 1,
+	.reg_ufs_apsrc_req_mask_b = 1,
+	.reg_ufs_vrf18_req_mask_b = 1,
+	.reg_ufs_ddren_req_mask_b = 1,
+	.reg_disp0_apsrc_req_mask_b = 1,
+	.reg_disp0_ddren_req_mask_b = 1,
+	.reg_disp1_apsrc_req_mask_b = 1,
+	.reg_disp1_ddren_req_mask_b = 1,
+	.reg_gce_infra_req_mask_b = 1,
+	.reg_gce_apsrc_req_mask_b = 1,
+	.reg_gce_vrf18_req_mask_b = 1,
+	.reg_gce_ddren_req_mask_b = 1,
+	.reg_apu_srcclkena_mask_b = 0,
+	.reg_apu_infra_req_mask_b = 0,
+	.reg_apu_apsrc_req_mask_b = 0,
+	.reg_apu_vrf18_req_mask_b = 0,
+	.reg_apu_ddren_req_mask_b = 0,
+	.reg_cg_check_srcclkena_mask_b = 0,
+	.reg_cg_check_apsrc_req_mask_b = 0,
+	.reg_cg_check_vrf18_req_mask_b = 0,
+	.reg_cg_check_ddren_req_mask_b = 0,
+
+	/* SPM_SRC3_MASK */
+	.reg_dvfsrc_event_trigger_mask_b = 1,
+	.reg_sw2spm_wakeup_mask_b = 0,
+	.reg_adsp2spm_wakeup_mask_b = 0,
+	.reg_sspm2spm_wakeup_mask_b = 0,
+	.reg_scp2spm_wakeup_mask_b = 0,
+	.reg_csyspwrup_ack_mask = 1,
+	.reg_spm_reserved_srcclkena_mask_b = 0,
+	.reg_spm_reserved_infra_req_mask_b = 0,
+	.reg_spm_reserved_apsrc_req_mask_b = 0,
+	.reg_spm_reserved_vrf18_req_mask_b = 0,
+	.reg_spm_reserved_ddren_req_mask_b = 0,
+	.reg_mcupm_srcclkena_mask_b = 0,
+	.reg_mcupm_infra_req_mask_b = 0,
+	.reg_mcupm_apsrc_req_mask_b = 0,
+	.reg_mcupm_vrf18_req_mask_b = 0,
+	.reg_mcupm_ddren_req_mask_b = 0,
+	.reg_msdc0_srcclkena_mask_b = 1,
+	.reg_msdc0_infra_req_mask_b = 1,
+	.reg_msdc0_apsrc_req_mask_b = 1,
+	.reg_msdc0_vrf18_req_mask_b = 1,
+	.reg_msdc0_ddren_req_mask_b = 1,
+	.reg_msdc1_srcclkena_mask_b = 1,
+	.reg_msdc1_infra_req_mask_b = 1,
+	.reg_msdc1_apsrc_req_mask_b = 1,
+	.reg_msdc1_vrf18_req_mask_b = 1,
+	.reg_msdc1_ddren_req_mask_b = 1,
+
+	/* SPM_SRC4_MASK */
+	.reg_ccif_event_srcclkena_mask_b = 0,
+	.reg_bak_psri_srcclkena_mask_b = 0,
+	.reg_bak_psri_infra_req_mask_b = 0,
+	.reg_bak_psri_apsrc_req_mask_b = 0,
+	.reg_bak_psri_vrf18_req_mask_b = 0,
+	.reg_bak_psri_ddren_req_mask_b = 0,
+	.reg_dramc_md32_infra_req_mask_b = 0,
+	.reg_dramc_md32_vrf18_req_mask_b = 0,
+	.reg_conn_srcclkenb2pwrap_mask_b = 0,
+	.reg_dramc_md32_apsrc_req_mask_b = 0,
+
+	/* SPM_SRC5_MASK */
+	.reg_mcusys_merge_apsrc_req_mask_b = 0x83,
+	.reg_mcusys_merge_ddren_req_mask_b = 0x83,
+	.reg_afe_srcclkena_mask_b = 1,
+	.reg_afe_infra_req_mask_b = 1,
+	.reg_afe_apsrc_req_mask_b = 1,
+	.reg_afe_vrf18_req_mask_b = 1,
+	.reg_afe_ddren_req_mask_b = 1,
+	.reg_msdc2_srcclkena_mask_b = 0,
+	.reg_msdc2_infra_req_mask_b = 0,
+	.reg_msdc2_apsrc_req_mask_b = 0,
+	.reg_msdc2_vrf18_req_mask_b = 0,
+	.reg_msdc2_ddren_req_mask_b = 0,
+
+	/* SPM_WAKEUP_EVENT_MASK */
+	.reg_wakeup_event_mask = 0x1383213,
+
+	/* SPM_WAKEUP_EVENT_EXT_MASK */
+	.reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+	/* SPM_SRC7_MASK */
+	.reg_pcie_srcclkena_mask_b = 0,
+	.reg_pcie_infra_req_mask_b = 0,
+	.reg_pcie_apsrc_req_mask_b = 0,
+	.reg_pcie_vrf18_req_mask_b = 0,
+	.reg_pcie_ddren_req_mask_b = 0,
+	.reg_dpmaif_srcclkena_mask_b = 1,
+	.reg_dpmaif_infra_req_mask_b = 1,
+	.reg_dpmaif_apsrc_req_mask_b = 1,
+	.reg_dpmaif_vrf18_req_mask_b = 1,
+	.reg_dpmaif_ddren_req_mask_b = 1,
+
+	/* Auto-gen End */
+
+	/*sw flag setting */
+	.pcm_flags = SPM_SUSPEND_PCM_FLAG,
+	.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
+};
+
+struct spm_lp_scen __spm_suspend = {
+	.pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode)
+{
+	if (mode == MT_SPM_SUSPEND_SLEEP) {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+	} else {
+		suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+		suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+	}
+
+	return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+			 unsigned int resource_req)
+{
+	/* If FMAudio / ADSP is active, change to sleep suspend mode */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
+	}
+
+	/* Notify MCUPM that device is going suspend flow */
+	mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
+
+	/* Notify UART to sleep */
+	mt_uart_save();
+
+	return spm_conservation(state_id, ext_opand,
+				&__spm_suspend, resource_req);
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+			   struct wake_status **status)
+{
+	spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
+
+	/* Notify UART to wakeup */
+	mt_uart_restore();
+
+	/* Notify MCUPM that device leave suspend */
+	mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
+
+	/* If FMAudio / ADSP is active, change back to suspend mode */
+	if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+		mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
+	}
+}
+
+void mt_spm_suspend_init(void)
+{
+	spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h
new file mode 100644
index 0000000..f7c066a
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/mt_spm_suspend.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef MT_SPM_SUSPEDN_H
+#define MT_SPM_SUSPEDN_H
+
+#include <mt_spm_internal.h>
+
+#define MCUPM_MBOX_OFFSET_PDN	(0x0C55FDA8)
+#define MCUPM_POWER_DOWN	(0x4D50444E)
+
+enum MT_SPM_SUSPEND_MODE {
+	MT_SPM_SUSPEND_SYSTEM_PDN	= 0U,
+	MT_SPM_SUSPEND_SLEEP		= 1U,
+};
+
+extern int mt_spm_suspend_mode_set(int mode);
+extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+				unsigned int reosuce_req);
+extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+				  struct wake_status **status);
+extern void mt_spm_suspend_init(void);
+
+#endif /* MT_SPM_SUSPEND_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_notifier.h b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_notifier.h
new file mode 100644
index 0000000..89aa163
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_notifier.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_NOTIFIER_H
+#define MT_SPM_SSPM_NOTIFIER_H
+
+enum MT_SPM_SSPM_NOTIFY_ID {
+	MT_SPM_NOTIFY_LP_ENTER			= 0U,
+	MT_SPM_NOTIFY_LP_LEAVE			= 1U,
+	MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE	= 2U,
+};
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode);
+
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
+{
+	return mt_spm_sspm_notify(type, lp_mode);
+}
+
+#endif /* MT_SPM_SSPM_NOTIFIER_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_intc.h b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_intc.h
new file mode 100644
index 0000000..0b85c60
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_intc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0	(0x10)
+#define MT_SPM_SSPM_INTC_SEL_1	(0x20)
+#define MT_SPM_SSPM_INTC_SEL_2	(0x40)
+#define MT_SPM_SSPM_INTC_SEL_3	(0x80)
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
+	(((0x10 << id) | (sg << id)) & 0xff)
+
+#define MT_SPM_SSPM_INTC0_HIGH	MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW	MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+#define MT_SPM_SSPM_INTC1_HIGH	MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW	MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+#define MT_SPM_SSPM_INTC2_HIGH	MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW	MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+#define MT_SPM_SSPM_INTC3_HIGH	MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW	MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+/*
+ * mt8186 use cpc pbi as notify.
+ * Therefore, it won't need be notified by spm driver.
+ */
+#define DO_SPM_SSPM_LP_SUSPEND()
+#define DO_SPM_SSPM_LP_RESUME()
+
+#endif /* MT_SPM_SSPM_INTC_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c
new file mode 100644
index 0000000..198bac5
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/notifier/mt_spm_sspm_notifier.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <lib/mmio.h>
+
+#include <mt_spm_notifier.h>
+#include <mt_spm_sspm_intc.h>
+#include <sspm_reg.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x)		(SSPM_MBOX_3_BASE + x)
+#define MT_SPM_MBOX(slot)		MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+#define SSPM_MBOX_SPM_LP_LOOKUP1	MT_SPM_MBOX(0)
+#define SSPM_MBOX_SPM_LP_LOOKUP2	MT_SPM_MBOX(1)
+#define SSPM_MBOX_SPM_LP1		MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2		MT_SPM_MBOX(3)
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode)
+{
+	switch (type) {
+	case MT_SPM_NOTIFY_LP_ENTER:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+		DO_SPM_SSPM_LP_SUSPEND();
+		break;
+	case MT_SPM_NOTIFY_LP_LEAVE:
+		mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+		DO_SPM_SSPM_LP_RESUME();
+		break;
+	case MT_SPM_NOTIFY_SUSPEND_VCORE_VOLTAGE:
+		mmio_write_32(SSPM_MBOX_SPM_LP2, lp_mode);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
diff --git a/plat/mediatek/mt8186/drivers/spm/pcm_def.h b/plat/mediatek/mt8186/drivers/spm/pcm_def.h
new file mode 100644
index 0000000..eb2db33
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/pcm_def.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF			(1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN			(1U << 1)
+#define R0_SC_MEM_CK_OFF			(1U << 2)
+#define R0_SC_AXI_CK_OFF			(1U << 3)
+#define R0_SC_DR_SRAM_LOAD			(1U << 4)
+#define R0_SC_MD26M_CK_OFF			(1U << 5)
+#define R0_SC_DPY_MODE_SW			(1U << 6)
+#define R0_SC_DMSUS_OFF				(1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN			(1U << 8)
+#define R0_SC_DR_SRAM_RESTORE			(1U << 9)
+#define R0_SC_MPLLOUT_OFF			(1U << 10)
+#define R0_SC_TX_TRACKING_DIS			(1U << 11)
+#define R0_SC_DPY_DLL_EN			(1U << 12)
+#define R0_SC_DPY_DLL_CK_EN			(1U << 13)
+#define R0_SC_DPY_VREF_EN			(1U << 14)
+#define R0_SC_PHYPLL_EN				(1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN			(1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE			(1U << 17)
+#define R0_SC_MPLL_OFF				(1U << 18)
+#define R0_SC_SHU_RESTORE			(1U << 19)
+#define R0_SC_CKSQ0_OFF				(1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH		(1U << 21)
+#define R0_SC_DR_SHU_EN				(1U << 22)
+#define R0_SC_DPHY_PRECAL_UP			(1U << 23)
+#define R0_SC_MPLL_S_OFF			(1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN		(1U << 25)
+#define R0_SC_PHYPLL_SHU_EN			(1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN			(1U << 27)
+#define R0_SC_PHYPLL_MODE_SW			(1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW			(1U << 29)
+#define R0_SC_DR0_SHU_LEVEL			(1U << 30)
+#define R0_SC_DR1_SHU_LEVEL			(1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ			(1U << 0)
+#define R7_EMI_CLK_OFF_REQ_PCM			(1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ			(1U << 2)
+#define R7_SPM_CK_UPDATE			(1U << 3)
+#define R7_SPM_CK_SEL0				(1U << 4)
+#define R7_SPM_CK_SEL1				(1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ		(1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL			(1U << 7)
+#define R7_SC_26M_CK_SEL			(1U << 8)
+#define R7_PCM_TIMER_SET			(1U << 9)
+#define R7_PCM_TIMER_CLR			(1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ		(1U << 11)
+#define R7_CSYSPWRUPACK				(1U << 12)
+#define R7_PCM_IM_SLP_EN			(1U << 13)
+#define R7_SRCCLKENO0				(1U << 14)
+#define R7_FORCE_DDR_EN_WAKE			(1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK		(1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL		(1U << 17)
+#define R7_SC_AXI_DCM_DIS			(1U << 18)
+#define R7_SC_FHC_PAUSE_MEM			(1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN			(1U << 20)
+#define R7_SRCCLKENO1				(1U << 21)
+#define R7_PCM_WDT_KICK_P			(1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC		(1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM			(1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM		(1U << 25)
+#define R7_PMIC_IRQ_REQ_EN			(1U << 26)
+#define R7_FORCE_F26M_WAKE			(1U << 27)
+#define R7_FORCE_APSRC_WAKE			(1U << 28)
+#define R7_FORCE_INFRA_WAKE			(1U << 29)
+#define R7_FORCE_VRF18_WAKE			(1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK		(1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER				(1U << 0)
+#define R12_TWAM_IRQ_B				(1U << 1)
+#define R12_KP_IRQ_B				(1U << 2)
+#define R12_APWDT_EVENT_B			(1U << 3)
+#define R12_APXGPT1_EVENT_B			(1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B		(1U << 5)
+#define R12_EINT_EVENT_B			(1U << 6)
+#define R12_CONN_WDT_IRQ_B			(1U << 7)
+#define R12_CCIF0_EVENT_B			(1U << 8)
+#define R12_LOWBATTERY_IRQ_B			(1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B			(1U << 10)
+#define R12_SCP2SPM_WAKEUP_B			(1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B			(1U << 12)
+#define R12_PCM_WDT_WAKEUP_B			(1U << 13)
+#define R12_USBX_CDSC_B				(1U << 14)
+#define R12_USBX_POWERDWN_B			(1U << 15)
+#define R12_SYS_TIMER_EVENT_B			(1U << 16)
+#define R12_EINT_EVENT_SECURE_B			(1U << 17)
+#define R12_CCIF1_EVENT_B			(1U << 18)
+#define R12_UART0_IRQ_B				(1U << 19)
+#define R12_AFE_IRQ_MCU_B			(1U << 20)
+#define R12_THERM_CTRL_EVENT_B			(1U << 21)
+#define R12_SYS_CIRQ_IRQ_B			(1U << 22)
+#define R12_MD2AP_PEER_EVENT_B			(1U << 23)
+#define R12_CSYSPWREQ_B				(1U << 24)
+#define R12_NNA_WAKEUP				(1U << 25)
+#define R12_CLDMA_EVENT_B			(1U << 26)
+#define R12_SEJ_EVENT_B				(1U << 27)
+#define R12_REG_CPU_WAKEUP			(1U << 28)
+#define R12_CPU_IRQOUT				(1U << 29)
+#define R12_CPU_WFI				(1U << 30)
+#define R12_MCUSYS_IDLE				(1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE				(1U << 0)
+#define R12EXT_26M_SLEEP			(1U << 1)
+#define R12EXT_INFRA_WAKE			(1U << 2)
+#define R12EXT_INFRA_SLEEP			(1U << 3)
+#define R12EXT_APSRC_WAKE			(1U << 4)
+#define R12EXT_APSRC_SLEEP			(1U << 5)
+#define R12EXT_VRF18_WAKE			(1U << 6)
+#define R12EXT_VRF18_SLEEP			(1U << 7)
+#define R12EXT_DVFS_WAKE			(1U << 8)
+#define R12EXT_DDREN_WAKE			(1U << 9)
+#define R12EXT_DDREN_SLEEP			(1U << 10)
+#define R12EXT_MCU_PM_WFI			(1U << 11)
+#define R12EXT_SSPM_IDLE			(1U << 12)
+#define R12EXT_CONN_SRCCLKENB			(1U << 13)
+#define R12EXT_DRAMC_MD32_WFI_MERGE		(1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE			(1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE		(1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE		(1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE			(1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK		(1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK		(1U << 20)
+#define R12EXT_BIT21				(1U << 21)
+#define R12EXT_BIT22				(1U << 22)
+#define R12EXT_BIT23				(1U << 23)
+#define R12EXT_BIT24				(1U << 24)
+#define R12EXT_BIT25				(1U << 25)
+#define R12EXT_BIT26				(1U << 26)
+#define R12EXT_BIT27				(1U << 27)
+#define R12EXT_BIT28				(1U << 28)
+#define R12EXT_BIT29				(1U << 29)
+#define R12EXT_BIT30				(1U << 30)
+#define R12EXT_BIT31				(1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0				(1U << 0)
+#define R13_SRCCLKENI1				(1U << 1)
+#define R13_MD_0_SRCCLKENA			(1U << 2)
+#define R13_MD_0_APSRC_REQ			(1U << 3)
+#define R13_CONN_DDREN				(1U << 4)
+#define R13_MD_1_SRCCLKENA			(1U << 5)
+#define R13_SSPM_SRCCLKENA			(1U << 6)
+#define R13_SSPM_APSRC_REQ			(1U << 7)
+#define R13_MD_1_STATE				(1U << 8)
+#define R13_RC_SRCCLKENO_ACK			(1U << 9)
+#define R13_MM_STATE				(1U << 10)
+#define R13_SSPM_STATE				(1U << 11)
+#define R13_MD_0_DDREN				(1U << 12)
+#define R13_CONN_STATE				(1U << 13)
+#define R13_CONN_SRCCLKENA			(1U << 14)
+#define R13_CONN_APSRC_REQ			(1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL			(1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL		(1U << 17)
+#define R13_SCP_STATE				(1U << 18)
+#define R13_CSYSPWRUPREQ			(1U << 19)
+#define R13_PWRAP_SLEEP_ACK			(1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL		(1U << 21)
+#define R13_AUDIO_DSP_STATE			(1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL		(1U << 23)
+#define R13_CONN_SRCCLKENB			(1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL		(1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0		(1U << 26)
+#define R13_DVFS_STATE				(1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL		(1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL		(1U << 29)
+#define R13_MD_0_VRF18_REQ			(1U << 30)
+#define R13_DDR_EN_STATE			(1U << 31)
+
+#endif /* PCM_DEF_H */
diff --git a/plat/mediatek/mt8186/drivers/spm/sleep_def.h b/plat/mediatek/mt8186/drivers/spm/sleep_def.h
new file mode 100644
index 0000000..d007939
--- /dev/null
+++ b/plat/mediatek/mt8186/drivers/spm/sleep_def.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN			(1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN			(1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN			(1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS			(1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS			(1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO		(1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF			(1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF			(1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH			(1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND			(1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO			(1U << 10)
+#define SPM_FLAG_SSPM_INFRA_SLEEP_MODE			(1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP		(1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2				(1U << 13)
+#define SPM_FLAG_RESERVED_BIT14				(1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND			(1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP			(1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP		(1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP		(1U << 18)
+#define SPM_FLAG_RESERVED_BIT19				(1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN			(1U << 20)
+#define SPM_FLAG_RESERVED_BIT21				(1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP		(1U << 22)
+#define SPM_FLAG_DISABLE_SRAM_EVENT			(1U << 23)
+#define SPM_FLAG_RESERVED_BIT24				(1U << 24)
+#define SPM_FLAG_RESERVED_BIT25				(1U << 25)
+#define SPM_FLAG_RESERVED_BIT26				(1U << 26)
+#define SPM_FLAG_DDREN_STATE				(1U << 27)
+#define SPM_FLAG_VTCXO_STATE				(1U << 28)
+#define SPM_FLAG_INFRA_STATE				(1U << 29)
+#define SPM_FLAG_VRF18_STATE				(1U << 30)
+#define SPM_FLAG_APSRC_STATE				(1U << 31)
+#define SPM_FLAG_SYSTEM_POWER_STATE			(1U << 28)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M		(1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF			(1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH		(1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF			(1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON			(1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5				(1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK				(1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7				(1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8				(1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9				(1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW			(1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH		(1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12			(1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13			(1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14			(1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15			(1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16			(1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17			(1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18			(1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19			(1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP		(1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21			(1U << 21)
+#define SPM_FLAG1_RESERVED_BIT22			(1U << 22)
+#define SPM_FLAG1_RESERVED_BIT23			(1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL		(1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25			(1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26			(1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27			(1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28			(1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29			(1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30			(1U << 30)
+#define SPM_FLAG1_ENABLE_MCUPM_OFF			(1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE			(1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP			(1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE			(1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP			(1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE			(1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP			(1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE			(1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP			(1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE			(1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP			(1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC	(1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE		(1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE		(1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN	(1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE		(1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP			(1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON			(1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP		(1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON			(1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP			(1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON			(1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP		(1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON		(1U << 22)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP_ABORT		(1U << 23)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW		(1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE			(1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE			(1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE			(1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE			(1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP		(1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START		(1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF			(1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON			(1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS	(1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF		(1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON		(1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT		(1U << 7)
+#define SPM_DBG1_RESERVED_BIT8				(1U << 8)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC		(1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M		(1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K		(1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M		(1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF			(1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON			(1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW			(1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH		(1U << 18)
+#define SPM_DBG1_DEBUG_IDX_MCUPM_WAKE_IRQ		(1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON	(1U << 20)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT	(1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT	(1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT		(1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT	(1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT	(1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT	(1U << 28)
+#define SPM_DBG1_DEBUG_IDX_SPM_TIMER_RST_DVFS		(1U << 29)
+#define SPM_DBG1_DEBUG_IDX_SPM_DISABLE_DDREN_EVENT	(1U << 30)
+#define MCUPM_RESTORE					(1U << 31)
+
+/* Macro and Inline */
+#define is_cpu_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
+#define is_infra_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
+#define is_ddrphy_pdn(flags)	(((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
+
+#endif /* SLEEP_DEF_H */
diff --git a/plat/mediatek/mt8186/include/mt_spm_resource_req.h b/plat/mediatek/mt8186/include/mt_spm_resource_req.h
new file mode 100644
index 0000000..9761e79
--- /dev/null
+++ b/plat/mediatek/mt8186/include/mt_spm_resource_req.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM	(0U)
+#define MT_SPM_BIT_26M		(1U)
+#define MT_SPM_BIT_INFRA	(2U)
+#define MT_SPM_BIT_SYSPLL	(3U)
+#define MT_SPM_BIT_DRAM_S0	(4U)
+#define MT_SPM_BIT_DRAM_S1	(5U)
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM	BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M	BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA	BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL	BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0	BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1	BIT(MT_SPM_BIT_DRAM_S1)
+
+char spm_resource_req(unsigned int user, unsigned int req_mask);
+
+#define IS_PLAT_SUSPEND_ID(stateid)\
+	((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)\
+	 || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8186/include/plat_mtk_lpm.h b/plat/mediatek/mt8186/include/plat_mtk_lpm.h
index 347f358..12ea9d7 100644
--- a/plat/mediatek/mt8186/include/plat_mtk_lpm.h
+++ b/plat/mediatek/mt8186/include/plat_mtk_lpm.h
@@ -44,5 +44,6 @@
 };
 
 const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
+int plat_mt_pm_register(struct mt_lpm_tz *mt_pm);
 
 #endif /* PLAT_MTK_LPM_H */
diff --git a/plat/mediatek/mt8186/include/plat_pm.h b/plat/mediatek/mt8186/include/plat_pm.h
index 436db34..ec70e4b 100644
--- a/plat/mediatek/mt8186/include/plat_pm.h
+++ b/plat/mediatek/mt8186/include/plat_pm.h
@@ -9,6 +9,10 @@
 
 #include <lib/utils_def.h>
 
+#ifndef __ASSEMBLY__
+extern uintptr_t mtk_suspend_footprint_addr;
+extern uintptr_t mtk_suspend_timestamp_addr;
+
 #define MT_PLAT_PWR_STATE_CPU			U(1)
 #define MT_PLAT_PWR_STATE_CLUSTER		U(2)
 #define MT_PLAT_PWR_STATE_MCUSYS		U(3)
@@ -24,6 +28,12 @@
 #define MTK_AFFLVL_MCUSYS			U(2)
 #define MTK_AFFLVL_SYSTEM			U(3)
 
+void mtk_suspend_footprint_log(int idx);
+void mtk_suspend_timestamp_log(int idx);
+
+int mt_cluster_ops(int cputop_mpx, int mode, int state);
+int mt_core_ops(int cpux, int state);
+
 #define IS_CLUSTER_OFF_STATE(s)					\
 		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
 #define IS_MCUSYS_OFF_STATE(s)					\
@@ -31,8 +41,88 @@
 #define IS_SYSTEM_SUSPEND_STATE(s)				\
 		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
 
+/* SMC secure magic number */
+#define SPM_LP_SMC_MAGIC	(0xDAF10000)
+
+#define IS_SPM_LP_SMC(_type, _id)	(_id == (SPM_LP_SMC_MAGIC | _type))
+
+enum mtk_suspend_mode {
+	MTK_MCDI_MODE		= 1U,
+	MTK_IDLEDRAM_MODE	= 2U,
+	MTK_IDLESYSPLL_MODE	= 3U,
+	MTK_IDLEBUS26M_MODE	= 4U,
+	MTK_SUSPEND_MODE	= 5U,
+};
+#endif
+
+enum mt8169_idle_model {
+	IDLE_MODEL_START		= 0U,
+	IDLE_MODEL_RESOURCE_HEAD	= IDLE_MODEL_START,
+	IDLE_MODEL_BUS26M		= IDLE_MODEL_RESOURCE_HEAD,
+	IDLE_MODEL_SYSPLL		= 1U,
+	IDLE_MODEL_DRAM			= 2U,
+	IDLE_MODEL_NUM			= 3U,
+};
+
+#define footprint_addr(cpu)		(mtk_suspend_footprint_addr + (cpu << 2))
+#define timestamp_addr(cpu, idx)	(mtk_suspend_timestamp_addr +	\
+					 ((cpu * MTK_SUSPEND_TIMESTAMP_MAX + idx) << 3))
+
+#define MTK_SUSPEND_FOOTPRINT_ENTER_CPUIDLE		(0U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_ATF		(1U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_ATF			(2U)
+#define MTK_SUSPEND_FOOTPRINT_RESERVE_P1		(3U)
+#define MTK_SUSPEND_FOOTPRINT_RESERVE_P2		(4U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND		(5U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND		(6U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_WFI		(7U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_WFI			(8U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_MMU		(9U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_MMU			(10U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND_FINISH	(11U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND_FINISH	(12U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_ATF			(13U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_ATF			(14U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_CPUIDLE		(15U)
+
+#define MTK_SUSPEND_TIMESTAMP_ENTER_CPUIDLE		(0U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_ATF		(1U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_ATF			(2U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_L2_FLUSH		(3U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_L2_FLUSH		(4U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND		(5U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND		(6U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P1			(7U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P2			(8U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_WFI		(9U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_WFI			(10U)
+#define MTK_SUSPEND_TIMESTAMP_RESERVE_P1		(11U)
+#define MTK_SUSPEND_TIMESTAMP_RESERVE_P2		(12U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P3			(13U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P4			(14U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND_FINISH	(15U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND_FINISH	(16U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_ATF			(17U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_ATF			(18U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_CPUIDLE		(19U)
+#define MTK_SUSPEND_TIMESTAMP_MAX			(20U)
+
+/*
+ * definition platform power state menas.
+ * PLAT_MT_SYSTEM_SUSPEND	- system suspend pwr level
+ * PLAT_MT_CPU_SUSPEND_CLUSTER	- cluster off pwr level
+ */
+#define PLAT_MT_SYSTEM_SUSPEND		PLAT_MAX_OFF_STATE
+#define PLAT_MT_CPU_SUSPEND_CLUSTER	PLAT_MAX_RET_STATE
+
+#define IS_PLAT_SYSTEM_SUSPEND(aff)	(aff == PLAT_MT_SYSTEM_SUSPEND)
+#define IS_PLAT_SYSTEM_RETENTION(aff)	(aff >= PLAT_MAX_RET_STATE)
+
+#define IS_PLAT_SUSPEND2IDLE_ID(stateid)\
+	(stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)
+
-#define IS_PLAT_SUSPEND_ID(stateid)				\
-		((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
-		|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+#define IS_PLAT_SUSPEND_ID(stateid)			\
+	((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
+	|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
 
 #endif /* PLAT_PM_H */
diff --git a/plat/mediatek/mt8186/include/plat_uart.h b/plat/mediatek/mt8186/include/plat_uart.h
new file mode 100644
index 0000000..f0fb442
--- /dev/null
+++ b/plat/mediatek/mt8186/include/plat_uart.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_UART_H__
+#define __PLAT_UART_H__
+
+/* UART error code */
+#define UART_DONE	U(0)
+#define UART_PM_ERROR	U(1)
+
+/* UART HW information */
+#ifndef HW_SUPPORT_UART_PORTS
+#define HW_SUPPORT_UART_PORTS	(2U)	/* the UART PORTs current HW have */
+#endif
+#define MTK_UART_SEND_SLEEP_REQ	(1U)	/* Request uart to sleep */
+#define MTK_UART_SLEEP_ACK_IDLE	(1U)	/* uart in idle state */
+#define MTK_UART_WAIT_ACK_TIMES	(50U)
+
+#define UART_BASE0	(0x11002000)
+#define UART_BASE1	(0x11003000)
+
+#endif /* __PLAT_UART_H__ */
diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index 479a8d4..90096e9 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +8,7 @@
 #ifndef PLATFORM_DEF_H
 #define PLATFORM_DEF_H
 
-#define PLAT_PRIMARY_CPU	0x0
+#define PLAT_PRIMARY_CPU	(0x0)
 
 #define MT_GIC_BASE		(0x0C000000)
 #define MCUCFG_BASE		(0x0C530000)
@@ -15,34 +16,52 @@
 
 /* Aggregate of all devices for MMU mapping */
 #define MTK_DEV_RNG0_BASE	IO_PHYS
-#define MTK_DEV_RNG0_SIZE	0x10000000
+#define MTK_DEV_RNG0_SIZE	(0x10000000)
 #define MTK_DEV_RNG2_BASE	MT_GIC_BASE
-#define MTK_DEV_RNG2_SIZE	0x600000
+#define MTK_DEV_RNG2_SIZE	(0x600000)
+#define MTK_MCDI_SRAM_BASE	(0x11B000)
+#define MTK_MCDI_SRAM_MAP_SIZE  (0x1000)
 
+#define TOPCKGEN_BASE           (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE        (IO_PHYS + 0x00001000)
 #define SPM_BASE		(IO_PHYS + 0x00006000)
+#define APMIXEDSYS              (IO_PHYS + 0x0000C000)
+#define SSPM_MBOX_BASE          (IO_PHYS + 0x00480000)
+#define PERICFG_AO_BASE         (IO_PHYS + 0x01003000)
+#define VPPSYS0_BASE            (IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE            (IO_PHYS + 0x04f00000)
+#define VDOSYS0_BASE            (IO_PHYS + 0x0C01A000)
+#define VDOSYS1_BASE            (IO_PHYS + 0x0C100000)
 
 /*******************************************************************************
  * GPIO related constants
  ******************************************************************************/
+#define TOPCKGEN_BASE		(IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE	(IO_PHYS + 0x00001000)
 #define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define SPM_BASE		(IO_PHYS + 0x00006000)
 #define IOCFG_LT_BASE		(IO_PHYS + 0x00002000)
 #define IOCFG_LM_BASE		(IO_PHYS + 0x00002200)
 #define IOCFG_LB_BASE		(IO_PHYS + 0x00002400)
 #define IOCFG_BL_BASE		(IO_PHYS + 0x00002600)
 #define IOCFG_RB_BASE		(IO_PHYS + 0x00002A00)
 #define IOCFG_RT_BASE		(IO_PHYS + 0x00002C00)
+#define APMIXEDSYS		(IO_PHYS + 0x0000C000)
+#define MMSYS_BASE		(IO_PHYS + 0x04000000)
+#define MDPSYS_BASE		(IO_PHYS + 0x0B000000)
 
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
-#define UART0_BASE			(IO_PHYS + 0x01002000)
+#define UART0_BASE		(IO_PHYS + 0x01002000)
+#define UART1_BASE		(IO_PHYS + 0x01003000)
 
-#define UART_BAUDRATE			115200
+#define UART_BAUDRATE		(115200)
 
 /*******************************************************************************
  * PWRAP related constants
  ******************************************************************************/
-#define PMIC_WRAP_BASE			(IO_PHYS + 0x0000D000)
+#define PMIC_WRAP_BASE		(IO_PHYS + 0x0000D000)
 
 /*******************************************************************************
  * EMI MPU related constants
@@ -53,19 +72,19 @@
  * GIC-600 & interrupt handling related constants
  ******************************************************************************/
 /* Base MTK_platform compatible GIC memory map */
-#define BASE_GICD_BASE			MT_GIC_BASE
-#define MT_GIC_RDIST_BASE		(MT_GIC_BASE + 0x40000)
+#define BASE_GICD_BASE		MT_GIC_BASE
+#define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
 
-#define SYS_CIRQ_BASE			(IO_PHYS + 0x204000)
-#define CIRQ_REG_NUM			11
-#define CIRQ_IRQ_NUM			326
-#define CIRQ_SPI_START			64
-#define MD_WDT_IRQ_BIT_ID		107
+#define SYS_CIRQ_BASE		(IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM		(11)
+#define CIRQ_IRQ_NUM		(326)
+#define CIRQ_SPI_START		(64)
+#define MD_WDT_IRQ_BIT_ID	(107)
 /*******************************************************************************
  * System counter frequency related constants
  ******************************************************************************/
-#define SYS_COUNTER_FREQ_IN_TICKS	13000000
-#define SYS_COUNTER_FREQ_IN_MHZ		13
+#define SYS_COUNTER_FREQ_IN_TICKS	(13000000)
+#define SYS_COUNTER_FREQ_IN_MHZ		(13)
 
 /*******************************************************************************
  * Platform binary types for linking
@@ -98,8 +117,8 @@
 /*******************************************************************************
  * Platform memory map related constants
  ******************************************************************************/
-#define TZRAM_BASE			0x54600000
-#define TZRAM_SIZE			0x00030000
+#define TZRAM_BASE			(0x54600000)
+#define TZRAM_SIZE			(0x00030000)
 
 /*******************************************************************************
  * BL31 specific defines.
@@ -117,8 +136,8 @@
  ******************************************************************************/
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#define MAX_XLAT_TABLES			16
-#define MAX_MMAP_REGIONS		16
+#define MAX_XLAT_TABLES			(16)
+#define MAX_MMAP_REGIONS		(16)
 
 /*******************************************************************************
  * Declarations and constants to access the mailboxes safely. Each mailbox is
@@ -129,6 +148,6 @@
  * get written while being protected by different locks causing corruption of
  * a valid mailbox address.
  ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT		6
-#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+#define CACHE_WRITEBACK_SHIFT		(6)
+#define CACHE_WRITEBACK_GRANULE		BIT(CACHE_WRITEBACK_SHIFT)
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8186/include/sspm_reg.h b/plat/mediatek/mt8186/include/sspm_reg.h
new file mode 100644
index 0000000..3e8c3e2
--- /dev/null
+++ b/plat/mediatek/mt8186/include/sspm_reg.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SSPM_REG_H__
+#define __SSPM_REG_H__
+
+#include "platform_def.h"
+
+#define SSPM_CFGREG_BASE	(IO_PHYS + 0x440000)     /* SSPM view: 0x30040000 */
+#define SSPM_CFGREG_ADDR(ofs)	(SSPM_CFGREG_BASE + (ofs))
+
+#define SSPM_MCDI_SHARE_SRAM	(IO_PHYS + 0x420000)
+#define SSPM_MBOX_3_BASE	(IO_PHYS + 0x480000)
+
+#define SSPM_HW_SEM		SSPM_CFGREG_ADDR(0x0048)
+#define SSPM_ACAO_INT_SET	SSPM_CFGREG_ADDR(0x00D8)
+#define SSPM_ACAO_INT_CLR	SSPM_CFGREG_ADDR(0x00DC)
+
+#define STANDBYWFI_EN(n)	(1 << (n + 8))
+#define GIC_IRQOUT_EN(n)	(1 << (n + 0))
+
+#endif /* __SSPM_REG_H__ */
diff --git a/plat/mediatek/mt8186/plat_pm.c b/plat/mediatek/mt8186/plat_pm.c
index e8d834d..6bc6b9d 100644
--- a/plat/mediatek/mt8186/plat_pm.c
+++ b/plat/mediatek/mt8186/plat_pm.c
@@ -4,15 +4,12 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-/* common headers */
 #include <assert.h>
-
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <drivers/gpio.h>
 #include <lib/psci/psci.h>
 
-/* platform specific headers */
 #include <mt_gic_v3.h>
 #include <mtspmc.h>
 #include <plat/common/platform.h>
diff --git a/plat/mediatek/mt8186/platform.mk b/plat/mediatek/mt8186/platform.mk
index 79c6834..6108a05 100644
--- a/plat/mediatek/mt8186/platform.mk
+++ b/plat/mediatek/mt8186/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2021, MediaTek Inc. All rights reserved.
+# Copyright (c) 2021-2022, MediaTek Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -10,7 +10,10 @@
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT}/common/drivers/gic600/             \
                  -I${MTK_PLAT}/common/drivers/gpio/             \
+                 -I${MTK_PLAT}/common/drivers/uart/               \
                  -I${MTK_PLAT}/common/drivers/timer/              \
+		 -I${MTK_PLAT}/common/lpm/                        \
+                 -I${MTK_PLAT_SOC}/drivers/spm/                   \
                  -I${MTK_PLAT_SOC}/drivers/dcm/                   \
                  -I${MTK_PLAT_SOC}/drivers/emi_mpu/               \
                  -I${MTK_PLAT_SOC}/drivers/gpio/               \
@@ -47,7 +50,9 @@
                 ${MTK_PLAT}/common/mtk_sip_svc.c                      \
                 ${MTK_PLAT}/common/params_setup.c                     \
                 ${MTK_PLAT}/common/drivers/timer/mt_timer.c           \
+                ${MTK_PLAT}/common/drivers/uart/uart.c                \
                 ${MTK_PLAT}/common/mtk_cirq.c           	      \
+		${MTK_PLAT}/common/lpm/mt_lp_rm.c                     \
                 ${MTK_PLAT_SOC}/aarch64/platform_common.c             \
                 ${MTK_PLAT_SOC}/aarch64/plat_helpers.S                \
                 ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
@@ -58,6 +63,7 @@
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c              \
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c          \
                 ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c                \
+                ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c        \
                 ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
                 ${MTK_PLAT_SOC}/drivers/rtc/rtc.c                     \
                 ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
@@ -65,6 +71,9 @@
                 ${MTK_PLAT_SOC}/plat_sip_calls.c                      \
                 ${MTK_PLAT_SOC}/plat_topology.c
 
+# Build SPM drivers
+include ${MTK_PLAT_SOC}/drivers/spm/build.mk
+
 # Configs for A76 and A55
 HW_ASSISTED_COHERENCY := 1
 USE_COHERENT_MEM := 0