diff --git a/plat/mediatek/mt8186/include/mt_spm_resource_req.h b/plat/mediatek/mt8186/include/mt_spm_resource_req.h
new file mode 100644
index 0000000..9761e79
--- /dev/null
+++ b/plat/mediatek/mt8186/include/mt_spm_resource_req.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM	(0U)
+#define MT_SPM_BIT_26M		(1U)
+#define MT_SPM_BIT_INFRA	(2U)
+#define MT_SPM_BIT_SYSPLL	(3U)
+#define MT_SPM_BIT_DRAM_S0	(4U)
+#define MT_SPM_BIT_DRAM_S1	(5U)
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM	BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M	BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA	BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL	BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0	BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1	BIT(MT_SPM_BIT_DRAM_S1)
+
+char spm_resource_req(unsigned int user, unsigned int req_mask);
+
+#define IS_PLAT_SUSPEND_ID(stateid)\
+	((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)\
+	 || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8186/include/plat_mtk_lpm.h b/plat/mediatek/mt8186/include/plat_mtk_lpm.h
index 347f358..12ea9d7 100644
--- a/plat/mediatek/mt8186/include/plat_mtk_lpm.h
+++ b/plat/mediatek/mt8186/include/plat_mtk_lpm.h
@@ -44,5 +44,6 @@
 };
 
 const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
+int plat_mt_pm_register(struct mt_lpm_tz *mt_pm);
 
 #endif /* PLAT_MTK_LPM_H */
diff --git a/plat/mediatek/mt8186/include/plat_pm.h b/plat/mediatek/mt8186/include/plat_pm.h
index 436db34..ec70e4b 100644
--- a/plat/mediatek/mt8186/include/plat_pm.h
+++ b/plat/mediatek/mt8186/include/plat_pm.h
@@ -9,6 +9,10 @@
 
 #include <lib/utils_def.h>
 
+#ifndef __ASSEMBLY__
+extern uintptr_t mtk_suspend_footprint_addr;
+extern uintptr_t mtk_suspend_timestamp_addr;
+
 #define MT_PLAT_PWR_STATE_CPU			U(1)
 #define MT_PLAT_PWR_STATE_CLUSTER		U(2)
 #define MT_PLAT_PWR_STATE_MCUSYS		U(3)
@@ -24,6 +28,12 @@
 #define MTK_AFFLVL_MCUSYS			U(2)
 #define MTK_AFFLVL_SYSTEM			U(3)
 
+void mtk_suspend_footprint_log(int idx);
+void mtk_suspend_timestamp_log(int idx);
+
+int mt_cluster_ops(int cputop_mpx, int mode, int state);
+int mt_core_ops(int cpux, int state);
+
 #define IS_CLUSTER_OFF_STATE(s)					\
 		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
 #define IS_MCUSYS_OFF_STATE(s)					\
@@ -31,8 +41,88 @@
 #define IS_SYSTEM_SUSPEND_STATE(s)				\
 		is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
 
+/* SMC secure magic number */
+#define SPM_LP_SMC_MAGIC	(0xDAF10000)
+
+#define IS_SPM_LP_SMC(_type, _id)	(_id == (SPM_LP_SMC_MAGIC | _type))
+
+enum mtk_suspend_mode {
+	MTK_MCDI_MODE		= 1U,
+	MTK_IDLEDRAM_MODE	= 2U,
+	MTK_IDLESYSPLL_MODE	= 3U,
+	MTK_IDLEBUS26M_MODE	= 4U,
+	MTK_SUSPEND_MODE	= 5U,
+};
+#endif
+
+enum mt8169_idle_model {
+	IDLE_MODEL_START		= 0U,
+	IDLE_MODEL_RESOURCE_HEAD	= IDLE_MODEL_START,
+	IDLE_MODEL_BUS26M		= IDLE_MODEL_RESOURCE_HEAD,
+	IDLE_MODEL_SYSPLL		= 1U,
+	IDLE_MODEL_DRAM			= 2U,
+	IDLE_MODEL_NUM			= 3U,
+};
+
+#define footprint_addr(cpu)		(mtk_suspend_footprint_addr + (cpu << 2))
+#define timestamp_addr(cpu, idx)	(mtk_suspend_timestamp_addr +	\
+					 ((cpu * MTK_SUSPEND_TIMESTAMP_MAX + idx) << 3))
+
+#define MTK_SUSPEND_FOOTPRINT_ENTER_CPUIDLE		(0U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_ATF		(1U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_ATF			(2U)
+#define MTK_SUSPEND_FOOTPRINT_RESERVE_P1		(3U)
+#define MTK_SUSPEND_FOOTPRINT_RESERVE_P2		(4U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND		(5U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND		(6U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_WFI		(7U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_WFI			(8U)
+#define MTK_SUSPEND_FOOTPRINT_BEFORE_MMU		(9U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_MMU			(10U)
+#define MTK_SUSPEND_FOOTPRINT_ENTER_SPM_SUSPEND_FINISH	(11U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_SPM_SUSPEND_FINISH	(12U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_ATF			(13U)
+#define MTK_SUSPEND_FOOTPRINT_AFTER_ATF			(14U)
+#define MTK_SUSPEND_FOOTPRINT_LEAVE_CPUIDLE		(15U)
+
+#define MTK_SUSPEND_TIMESTAMP_ENTER_CPUIDLE		(0U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_ATF		(1U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_ATF			(2U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_L2_FLUSH		(3U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_L2_FLUSH		(4U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND		(5U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND		(6U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P1			(7U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P2			(8U)
+#define MTK_SUSPEND_TIMESTAMP_BEFORE_WFI		(9U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_WFI			(10U)
+#define MTK_SUSPEND_TIMESTAMP_RESERVE_P1		(11U)
+#define MTK_SUSPEND_TIMESTAMP_RESERVE_P2		(12U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P3			(13U)
+#define MTK_SUSPEND_TIMESTAMP_GIC_P4			(14U)
+#define MTK_SUSPEND_TIMESTAMP_ENTER_SPM_SUSPEND_FINISH	(15U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_SPM_SUSPEND_FINISH	(16U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_ATF			(17U)
+#define MTK_SUSPEND_TIMESTAMP_AFTER_ATF			(18U)
+#define MTK_SUSPEND_TIMESTAMP_LEAVE_CPUIDLE		(19U)
+#define MTK_SUSPEND_TIMESTAMP_MAX			(20U)
+
+/*
+ * definition platform power state menas.
+ * PLAT_MT_SYSTEM_SUSPEND	- system suspend pwr level
+ * PLAT_MT_CPU_SUSPEND_CLUSTER	- cluster off pwr level
+ */
+#define PLAT_MT_SYSTEM_SUSPEND		PLAT_MAX_OFF_STATE
+#define PLAT_MT_CPU_SUSPEND_CLUSTER	PLAT_MAX_RET_STATE
+
+#define IS_PLAT_SYSTEM_SUSPEND(aff)	(aff == PLAT_MT_SYSTEM_SUSPEND)
+#define IS_PLAT_SYSTEM_RETENTION(aff)	(aff >= PLAT_MAX_RET_STATE)
+
+#define IS_PLAT_SUSPEND2IDLE_ID(stateid)\
+	(stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)
+
-#define IS_PLAT_SUSPEND_ID(stateid)				\
-		((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
-		|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+#define IS_PLAT_SUSPEND_ID(stateid)			\
+	((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE)	\
+	|| (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
 
 #endif /* PLAT_PM_H */
diff --git a/plat/mediatek/mt8186/include/plat_uart.h b/plat/mediatek/mt8186/include/plat_uart.h
new file mode 100644
index 0000000..f0fb442
--- /dev/null
+++ b/plat/mediatek/mt8186/include/plat_uart.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_UART_H__
+#define __PLAT_UART_H__
+
+/* UART error code */
+#define UART_DONE	U(0)
+#define UART_PM_ERROR	U(1)
+
+/* UART HW information */
+#ifndef HW_SUPPORT_UART_PORTS
+#define HW_SUPPORT_UART_PORTS	(2U)	/* the UART PORTs current HW have */
+#endif
+#define MTK_UART_SEND_SLEEP_REQ	(1U)	/* Request uart to sleep */
+#define MTK_UART_SLEEP_ACK_IDLE	(1U)	/* uart in idle state */
+#define MTK_UART_WAIT_ACK_TIMES	(50U)
+
+#define UART_BASE0	(0x11002000)
+#define UART_BASE1	(0x11003000)
+
+#endif /* __PLAT_UART_H__ */
diff --git a/plat/mediatek/mt8186/include/platform_def.h b/plat/mediatek/mt8186/include/platform_def.h
index 479a8d4..90096e9 100644
--- a/plat/mediatek/mt8186/include/platform_def.h
+++ b/plat/mediatek/mt8186/include/platform_def.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +8,7 @@
 #ifndef PLATFORM_DEF_H
 #define PLATFORM_DEF_H
 
-#define PLAT_PRIMARY_CPU	0x0
+#define PLAT_PRIMARY_CPU	(0x0)
 
 #define MT_GIC_BASE		(0x0C000000)
 #define MCUCFG_BASE		(0x0C530000)
@@ -15,34 +16,52 @@
 
 /* Aggregate of all devices for MMU mapping */
 #define MTK_DEV_RNG0_BASE	IO_PHYS
-#define MTK_DEV_RNG0_SIZE	0x10000000
+#define MTK_DEV_RNG0_SIZE	(0x10000000)
 #define MTK_DEV_RNG2_BASE	MT_GIC_BASE
-#define MTK_DEV_RNG2_SIZE	0x600000
+#define MTK_DEV_RNG2_SIZE	(0x600000)
+#define MTK_MCDI_SRAM_BASE	(0x11B000)
+#define MTK_MCDI_SRAM_MAP_SIZE  (0x1000)
 
+#define TOPCKGEN_BASE           (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE        (IO_PHYS + 0x00001000)
 #define SPM_BASE		(IO_PHYS + 0x00006000)
+#define APMIXEDSYS              (IO_PHYS + 0x0000C000)
+#define SSPM_MBOX_BASE          (IO_PHYS + 0x00480000)
+#define PERICFG_AO_BASE         (IO_PHYS + 0x01003000)
+#define VPPSYS0_BASE            (IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE            (IO_PHYS + 0x04f00000)
+#define VDOSYS0_BASE            (IO_PHYS + 0x0C01A000)
+#define VDOSYS1_BASE            (IO_PHYS + 0x0C100000)
 
 /*******************************************************************************
  * GPIO related constants
  ******************************************************************************/
+#define TOPCKGEN_BASE		(IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE	(IO_PHYS + 0x00001000)
 #define GPIO_BASE		(IO_PHYS + 0x00005000)
+#define SPM_BASE		(IO_PHYS + 0x00006000)
 #define IOCFG_LT_BASE		(IO_PHYS + 0x00002000)
 #define IOCFG_LM_BASE		(IO_PHYS + 0x00002200)
 #define IOCFG_LB_BASE		(IO_PHYS + 0x00002400)
 #define IOCFG_BL_BASE		(IO_PHYS + 0x00002600)
 #define IOCFG_RB_BASE		(IO_PHYS + 0x00002A00)
 #define IOCFG_RT_BASE		(IO_PHYS + 0x00002C00)
+#define APMIXEDSYS		(IO_PHYS + 0x0000C000)
+#define MMSYS_BASE		(IO_PHYS + 0x04000000)
+#define MDPSYS_BASE		(IO_PHYS + 0x0B000000)
 
 /*******************************************************************************
  * UART related constants
  ******************************************************************************/
-#define UART0_BASE			(IO_PHYS + 0x01002000)
+#define UART0_BASE		(IO_PHYS + 0x01002000)
+#define UART1_BASE		(IO_PHYS + 0x01003000)
 
-#define UART_BAUDRATE			115200
+#define UART_BAUDRATE		(115200)
 
 /*******************************************************************************
  * PWRAP related constants
  ******************************************************************************/
-#define PMIC_WRAP_BASE			(IO_PHYS + 0x0000D000)
+#define PMIC_WRAP_BASE		(IO_PHYS + 0x0000D000)
 
 /*******************************************************************************
  * EMI MPU related constants
@@ -53,19 +72,19 @@
  * GIC-600 & interrupt handling related constants
  ******************************************************************************/
 /* Base MTK_platform compatible GIC memory map */
-#define BASE_GICD_BASE			MT_GIC_BASE
-#define MT_GIC_RDIST_BASE		(MT_GIC_BASE + 0x40000)
+#define BASE_GICD_BASE		MT_GIC_BASE
+#define MT_GIC_RDIST_BASE	(MT_GIC_BASE + 0x40000)
 
-#define SYS_CIRQ_BASE			(IO_PHYS + 0x204000)
-#define CIRQ_REG_NUM			11
-#define CIRQ_IRQ_NUM			326
-#define CIRQ_SPI_START			64
-#define MD_WDT_IRQ_BIT_ID		107
+#define SYS_CIRQ_BASE		(IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM		(11)
+#define CIRQ_IRQ_NUM		(326)
+#define CIRQ_SPI_START		(64)
+#define MD_WDT_IRQ_BIT_ID	(107)
 /*******************************************************************************
  * System counter frequency related constants
  ******************************************************************************/
-#define SYS_COUNTER_FREQ_IN_TICKS	13000000
-#define SYS_COUNTER_FREQ_IN_MHZ		13
+#define SYS_COUNTER_FREQ_IN_TICKS	(13000000)
+#define SYS_COUNTER_FREQ_IN_MHZ		(13)
 
 /*******************************************************************************
  * Platform binary types for linking
@@ -98,8 +117,8 @@
 /*******************************************************************************
  * Platform memory map related constants
  ******************************************************************************/
-#define TZRAM_BASE			0x54600000
-#define TZRAM_SIZE			0x00030000
+#define TZRAM_BASE			(0x54600000)
+#define TZRAM_SIZE			(0x00030000)
 
 /*******************************************************************************
  * BL31 specific defines.
@@ -117,8 +136,8 @@
  ******************************************************************************/
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
-#define MAX_XLAT_TABLES			16
-#define MAX_MMAP_REGIONS		16
+#define MAX_XLAT_TABLES			(16)
+#define MAX_MMAP_REGIONS		(16)
 
 /*******************************************************************************
  * Declarations and constants to access the mailboxes safely. Each mailbox is
@@ -129,6 +148,6 @@
  * get written while being protected by different locks causing corruption of
  * a valid mailbox address.
  ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT		6
-#define CACHE_WRITEBACK_GRANULE		(1 << CACHE_WRITEBACK_SHIFT)
+#define CACHE_WRITEBACK_SHIFT		(6)
+#define CACHE_WRITEBACK_GRANULE		BIT(CACHE_WRITEBACK_SHIFT)
 #endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8186/include/sspm_reg.h b/plat/mediatek/mt8186/include/sspm_reg.h
new file mode 100644
index 0000000..3e8c3e2
--- /dev/null
+++ b/plat/mediatek/mt8186/include/sspm_reg.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2022, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SSPM_REG_H__
+#define __SSPM_REG_H__
+
+#include "platform_def.h"
+
+#define SSPM_CFGREG_BASE	(IO_PHYS + 0x440000)     /* SSPM view: 0x30040000 */
+#define SSPM_CFGREG_ADDR(ofs)	(SSPM_CFGREG_BASE + (ofs))
+
+#define SSPM_MCDI_SHARE_SRAM	(IO_PHYS + 0x420000)
+#define SSPM_MBOX_3_BASE	(IO_PHYS + 0x480000)
+
+#define SSPM_HW_SEM		SSPM_CFGREG_ADDR(0x0048)
+#define SSPM_ACAO_INT_SET	SSPM_CFGREG_ADDR(0x00D8)
+#define SSPM_ACAO_INT_CLR	SSPM_CFGREG_ADDR(0x00DC)
+
+#define STANDBYWFI_EN(n)	(1 << (n + 8))
+#define GIC_IRQOUT_EN(n)	(1 << (n + 0))
+
+#endif /* __SSPM_REG_H__ */