feat(fvp): increase GPT PPS to 1TB
- Increase PPS for FVP from 64GB to 1TB.
- GPT L0 table for 1TB PPS requires 8KB memory.
- Set FVP_TRUSTED_SRAM_SIZE to 384 with ENABLE_RME=1
option.
- Add 256MB of PCIe memory region 1 and 3GB of
PCIe memory region 2 to FVP PAS regions array.
Change-Id: Icadd528576f53c55b5d461ff4dcd357429ba622a
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index a086a98..3fad566 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -137,7 +137,8 @@
---------------------
- ``FVP_TRUSTED_SRAM_SIZE``: Size (in kilobytes) of the Trusted SRAM region to
- utilize when building for the FVP platform. This option defaults to 256.
+ utilize when building for the FVP platform. This option defaults to 256 with
+ build option ENABLE_RME=0 and 384 for ENABLE_RME=1.
Arm Juno Build Options
----------------------
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index e94b32a..cc1dcde 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -67,7 +67,7 @@
#define ARM_L0_GPT_BASE (ARM_TRUSTED_SRAM_BASE + \
PLAT_ARM_TRUSTED_SRAM_SIZE - \
ARM_L0_GPT_SIZE)
-#define ARM_L0_GPT_SIZE UL(0x00001000) /* 4 KB */
+#define ARM_L0_GPT_SIZE UL(0x00002000) /* 8 KB */
#else
#define ARM_L0_GPT_SIZE UL(0)
#endif
@@ -120,7 +120,7 @@
* placed here. 3MB region is reserved if RME is enabled, 2MB otherwise.
*/
#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */
-/* 8 x 128KB L1 pages (GPCCR_PPS_64GB, GPCCR_PGS_4K) */
+/* 8 x 128KB L1 pages (L0GPTSZ = 1GB, PGS = 4KB) */
#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */
/* 32MB - ARM_EL3_RMM_SHARED_SIZE */
#define ARM_REALM_SIZE (UL(0x02000000) - \
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index be8a19c..90d9608 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,20 +33,22 @@
#ifdef ARM_PAS_GPTS
ARM_PAS_GPTS,
#endif
- ARM_PAS_KERNEL_1
+ ARM_PAS_KERNEL_1,
+ ARM_PAS_PCI_MEM_1,
+ ARM_PAS_PCI_MEM_2
};
static const arm_gpt_info_t arm_gpt_info = {
.pas_region_base = pas_regions,
.pas_region_count = (unsigned int)ARRAY_SIZE(pas_regions),
- .l0_base = (uintptr_t)ARM_L0_GPT_BASE,
- .l1_base = (uintptr_t)ARM_L1_GPT_BASE,
- .l0_size = (size_t)ARM_L0_GPT_SIZE,
- .l1_size = (size_t)ARM_L1_GPT_SIZE,
- .pps = GPCCR_PPS_64GB,
+ .l0_base = ARM_L0_GPT_BASE,
+ .l1_base = ARM_L1_GPT_BASE,
+ .l0_size = ARM_L0_GPT_SIZE,
+ .l1_size = ARM_L1_GPT_SIZE,
+ .pps = GPCCR_PPS_1TB,
.pgs = GPCCR_PGS_4K
};
-#endif
+#endif /* ENABLE_RME */
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
{
diff --git a/plat/arm/board/fvp/include/fvp_pas_def.h b/plat/arm/board/fvp/include/fvp_pas_def.h
index 928c33a..6b97286 100644
--- a/plat/arm/board/fvp/include/fvp_pas_def.h
+++ b/plat/arm/board/fvp/include/fvp_pas_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,31 +17,37 @@
* The PA space is initially mapped in the GPT as follows:
*
* ============================================================================
- * Base Addr| Size |L? GPT|PAS |Content |Comment
+ * Base Addr | Size |L? GPT|PAS |Content |Comment
* ============================================================================
- * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping
- * | | | |TSRAM (EL3 data) |
- * 00000000 | 40000000 | | |IO (incl.UARTs & GIC) |
+ * 0GB | 1GB |L0 GPT|ANY |TBROM (EL3 code) |Fixed mapping
+ * | | | |TSRAM (EL3 data) |
+ * 00000000 | 40000000 | | |IO (incl.UARTs & GIC) |
* ----------------------------------------------------------------------------
- * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping
- * 40000000 | 40000000 | | | |
+ * 1GB | 1GB |L0 GPT|ANY |IO |Fixed mapping
+ * 40000000 | 40000000 | | | |
* ----------------------------------------------------------------------------
- * 2GB | 2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
- * 80000000 | 7C000000 | | | |
+ * 1GB+256MB | 256MB |L1 GPT|NS |PCI Memory Region 1 |Use T.Descrip
+ * 50000000 | 10000000 | | | |
* ----------------------------------------------------------------------------
- * 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip
- * FC000000 | 1C00000 | | | |
+ * 2GB | 2GB-64MB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
+ * 80000000 | 7C000000 | | | |
* ----------------------------------------------------------------------------
- * 4GB-32MB | | | | |
- * -3MB-1MB | 32MB |L1 GPT|REALM |RMM |Use T.Descrip
- * FDC00000 | 2000000 | | | |
+ * 4GB-64MB |64MB-32MB-4MB|L1 GPT|SECURE|DRAM TZC |Use T.Descrip
+ * FC000000 | 1C00000 | | | |
* ----------------------------------------------------------------------------
- * 4GB-3MB | | | | |
- * -1MB | 4MB |L1 GPT|ROOT |EL3 DRAM data, L1 GPTs, |Use T.Descrip
- * FFC00000 | 400000 | | |SCP TZC |
+ * 4GB-32MB | | | | |
+ * -3MB-1MB | 32MB |L1 GPT|REALM |RMM |Use T.Descrip
+ * FDC00000 | 2000000 | | | |
* ----------------------------------------------------------------------------
- * 34GB | 2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
- * 880000000| 80000000 | | | |
+ * 4GB-3MB | | | | |
+ * -1MB | 4MB |L1 GPT|ROOT |EL3 DRAM data, L1 GPTs, |Use T.Descrip
+ * FFC00000 | 400000 | | |SCP TZC |
+ * ----------------------------------------------------------------------------
+ * 34GB | 2GB |L1 GPT|NS |DRAM (NS Kernel) |Use T.Descrip
+ * 880000000 | 80000000 | | | |
+ * ----------------------------------------------------------------------------
+ * 256GB | 3GB |L1 GPT|NS |PCI Memory Region 2 |Use T.Descrip
+ * 4000000000| C0000000 | | |(first 3GB only) |
* ============================================================================
*
* - 4KB of L0 GPT reside in TSRAM, on top of the CONFIG section.
@@ -91,6 +97,14 @@
#define ARM_PAS_KERNEL_1 GPT_MAP_REGION_GRANULE(ARM_PAS_4_BASE, \
ARM_PAS_4_SIZE, \
GPT_GPI_NS)
+
+#define ARM_PAS_PCI_MEM_1 GPT_MAP_REGION_GRANULE(PLAT_ARM_PCI_MEM_1_BASE, \
+ PLAT_ARM_PCI_MEM_1_SIZE, \
+ GPT_GPI_NS)
+
+#define ARM_PAS_PCI_MEM_2 GPT_MAP_REGION_GRANULE(PLAT_ARM_PCI_MEM_2_BASE, \
+ PLAT_ARM_PCI_MEM_2_SIZE, \
+ GPT_GPI_NS)
/*
* REALM and Shared area share the same PAS, so consider them a single
* PAS region to configure in GPT.
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index f597f4b..f5be8f2 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -56,7 +56,7 @@
#define PLAT_ARM_RMM_SIZE (RMM_LIMIT - RMM_BASE)
/* Protected physical address size */
-#define PLAT_ARM_PPS (64 * SZ_1G)
+#define PLAT_ARM_PPS (SZ_1T)
#endif /* ENABLE_RME */
/*
@@ -68,7 +68,7 @@
#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
#endif
-/* virtual address used by dynamic mem_protect for chunk_base */
+/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
/* No SCP in FVP */
@@ -402,11 +402,22 @@
#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
/* System timer related constants */
-#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
+#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
/* Mailbox base address */
#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
+/* PCIe memory region 1 (Base Platform RevC only) */
+#define PLAT_ARM_PCI_MEM_1_BASE (ULL(0x50000000))
+#define PLAT_ARM_PCI_MEM_1_SIZE (SZ_256M) /* 256MB */
+
+/*
+ * PCIe memory region 2 (Base Platform RevC only)
+ * The full size of the second PCI memory region is 256GB
+ * but for now we only allocate the L1 GPTs for the first 3GB.
+ */
+#define PLAT_ARM_PCI_MEM_2_BASE (ULL(0x4000000000))
+#define PLAT_ARM_PCI_MEM_2_SIZE (3 * SZ_1G) /* 3GB */
/* TrustZone controller related constants
*
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index ce06146..05bd913 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -29,9 +29,13 @@
endif
# fdts is wrong otherwise
-# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
-# the FVP platform. This option defaults to 256.
+# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
+# the FVP platform.
+ifeq (${ENABLE_RME},1)
+FVP_TRUSTED_SRAM_SIZE := 384
+else
FVP_TRUSTED_SRAM_SIZE := 256
+endif
# Macro to enable helpers for running SPM tests. Disabled by default.
PLAT_TEST_SPM := 0