refactor(fvp): fdts: consolidate GICv3 base FVP DT files
The GICv2 and GICv3 version of the FVP DT files are unnecessarily split,
as the common part of the peripherals is the same: it's literally just
the interrupt controller node that is different.
To facilitate a unification, refactor the DT include files to explicitly
include a snippet with just the GICv3 description, and a generic base DT
file for the rest. This generic file can then be reused by the GICv2
versions later.
Since we can only have a /memreserve/ entry *before* any DT nodes, move
that line to each file, to allow including the GIC DT file separately.
Change-Id: I9ff357d3fe0ce46e280c30131aeae97a99631512
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/fdts/fvp-base-gicv3-psci-1t.dts b/fdts/fvp-base-gicv3-psci-1t.dts
index c5e0424..829555b 100644
--- a/fdts/fvp-base-gicv3-psci-1t.dts
+++ b/fdts/fvp-base-gicv3-psci-1t.dts
@@ -6,9 +6,13 @@
/* Configuration: max 4 clusters with up to 4 CPUs with 1 thread per each */
-/dts-v1/;
-
#define AFF 00
#include "fvp-defs.dtsi"
-#include "fvp-base-gicv3-psci-common.dtsi"
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00010000;
+
+#include "fvp-base-gicv3.dtsi"
+#include "fvp-base-psci-common.dtsi"
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
index bda4b8d..9d5b979 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -13,6 +13,11 @@
#define PE_PER_CPU 2
#endif
+#include "fvp-defs-dynamiq.dtsi"
+
/dts-v1/;
-#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
+/memreserve/ 0x80000000 0x00010000;
+
+#include "fvp-base-gicv3.dtsi"
+#include "fvp-base-psci-common.dtsi"
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq.dts b/fdts/fvp-base-gicv3-psci-dynamiq.dts
index b693f75..1bf803e 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq.dts
@@ -13,6 +13,11 @@
#define PE_PER_CPU 1
#endif
+#include "fvp-defs-dynamiq.dtsi"
+
/dts-v1/;
-#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
+/memreserve/ 0x80000000 0x00010000;
+
+#include "fvp-base-gicv3.dtsi"
+#include "fvp-base-psci-common.dtsi"
diff --git a/fdts/fvp-base-gicv3-psci.dts b/fdts/fvp-base-gicv3-psci.dts
index eb99472..69db267 100644
--- a/fdts/fvp-base-gicv3-psci.dts
+++ b/fdts/fvp-base-gicv3-psci.dts
@@ -6,9 +6,13 @@
/* Configuration: max 4 clusters with up to 4 CPUs */
-/dts-v1/;
-
#define AFF
#include "fvp-defs.dtsi"
-#include "fvp-base-gicv3-psci-common.dtsi"
+
+/dts-v1/;
+
+/memreserve/ 0x80000000 0x00010000;
+
+#include "fvp-base-gicv3.dtsi"
+#include "fvp-base-psci-common.dtsi"
diff --git a/fdts/fvp-base-gicv3.dtsi b/fdts/fvp-base-gicv3.dtsi
new file mode 100644
index 0000000..fdcfa92
--- /dev/null
+++ b/fdts/fvp-base-gicv3.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* GICv3 with ITS configuration */
+
+/ {
+ gic: interrupt-controller@2f000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x2f000000 0x100000>;
+ interrupt-controller;
+ reg = <0x0 0x2f000000 0 0x10000>, // GICD
+ <0x0 0x2f100000 0 0x200000>, // GICR
+ <0x0 0x2c000000 0 0x2000>, // GICC
+ <0x0 0x2c010000 0 0x2000>, // GICH
+ <0x0 0x2c02f000 0 0x2000>; // GICV
+ interrupts = <1 9 4>;
+
+ its: msi-controller@2f020000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0x20000 0x20000>; // GITS
+ };
+ };
+};
diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-psci-common.dtsi
similarity index 91%
rename from fdts/fvp-base-gicv3-psci-common.dtsi
rename to fdts/fvp-base-psci-common.dtsi
index 805b014..69af15a 100644
--- a/fdts/fvp-base-gicv3-psci-common.dtsi
+++ b/fdts/fvp-base-psci-common.dtsi
@@ -12,14 +12,9 @@
#define SDEI_NORMAL 0x70
#define HIGHEST_SEC 0
-/memreserve/ 0x80000000 0x00010000;
-
-/ {
-};
-
/ {
model = "FVP Base";
- compatible = "arm,vfp-base", "arm,vexpress";
+ compatible = "arm,fvp-base", "arm,vexpress";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
@@ -143,28 +138,6 @@
#endif
};
- gic: interrupt-controller@2f000000 {
- compatible = "arm,gic-v3";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x2f000000 0x100000>;
- interrupt-controller;
- reg = <0x0 0x2f000000 0 0x10000>, // GICD
- <0x0 0x2f100000 0 0x200000>, // GICR
- <0x0 0x2c000000 0 0x2000>, // GICC
- <0x0 0x2c010000 0 0x2000>, // GICH
- <0x0 0x2c02f000 0 0x2000>; // GICV
- interrupts = <1 9 4>;
-
- its: its@2f020000 {
- compatible = "arm,gic-v3-its";
- msi-controller;
- #msi-cells = <1>;
- reg = <0x20000 0x20000>; // GITS
- };
- };
-
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
@@ -200,7 +173,7 @@
<0 63 4>;
};
- smb@0,0 {
+ smb@0 {
compatible = "simple-bus";
#address-cells = <2>;