Merge "fix(st-pmic): remove deadcode from STPMIC2 driver" into integration
diff --git a/include/lib/cpus/aarch64/cortex_a320.h b/include/lib/cpus/aarch64/cortex_a320.h
new file mode 100644
index 0000000..5231151
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a320.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A320_H
+#define CORTEX_A320_H
+
+#define CORTEX_A320_MIDR U(0x410FD8F0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A320_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A320_CPUECTLR_EL1_EXTLLC_BIT U(0)
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A320_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A320_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_A320_H */
diff --git a/include/lib/cpus/aarch64/cortex_arcadia.h b/include/lib/cpus/aarch64/cortex_arcadia.h
deleted file mode 100644
index 8b74de2..0000000
--- a/include/lib/cpus/aarch64/cortex_arcadia.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_ARCADIA_H
-#define CORTEX_ARCADIA_H
-
-#define CORTEX_ARCADIA_MIDR U(0x410FD8F0)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_ARCADIA_CPUECTLR_EL1 S3_0_C15_C1_4
-#define CORTEX_ARCADIA_CPUECTLR_EL1_EXTLLC_BIT U(0)
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_ARCADIA_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_ARCADIA_H */
diff --git a/lib/cpus/aarch64/cortex_a320.S b/lib/cpus/aarch64/cortex_a320.S
new file mode 100644
index 0000000..2d38b88
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a320.S
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a320.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A320 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex-A320 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_prologue cortex_a320
+
+cpu_reset_func_start cortex_a320
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ enable_mpmm
+cpu_reset_func_end cortex_a320
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_a320_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_A320_CPUPWRCTLR_EL1, CORTEX_A320_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
+ ret
+endfunc cortex_a320_core_pwr_dwn
+
+ /* ---------------------------------------------
+ * This function provides Cortex-A320 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a320_regs, "aS"
+cortex_a320_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a320_cpu_reg_dump
+ adr x6, cortex_a320_regs
+ mrs x8, CORTEX_A320_CPUECTLR_EL1
+ ret
+endfunc cortex_a320_cpu_reg_dump
+
+declare_cpu_ops cortex_a320, CORTEX_A320_MIDR, \
+ cortex_a320_reset_func, \
+ cortex_a320_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_arcadia.S b/lib/cpus/aarch64/cortex_arcadia.S
deleted file mode 100644
index 84749b6..0000000
--- a/lib/cpus/aarch64/cortex_arcadia.S
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2024-2025, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_arcadia.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex-ARCADIA must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex-ARCADIA supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-cpu_reset_prologue cortex_arcadia
-
-cpu_reset_func_start cortex_arcadia
- /* Disable speculative loads */
- msr SSBS, xzr
- enable_mpmm
-cpu_reset_func_end cortex_arcadia
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_arcadia_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- sysreg_bit_set CORTEX_ARCADIA_CPUPWRCTLR_EL1, CORTEX_ARCADIA_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- isb
- ret
-endfunc cortex_arcadia_core_pwr_dwn
-
- /* ---------------------------------------------
- * This function provides Cortex-Arcadia specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_arcadia_regs, "aS"
-cortex_arcadia_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_arcadia_cpu_reg_dump
- adr x6, cortex_arcadia_regs
- mrs x8, CORTEX_ARCADIA_CPUECTLR_EL1
- ret
-endfunc cortex_arcadia_cpu_reg_dump
-
-declare_cpu_ops cortex_arcadia, CORTEX_ARCADIA_MIDR, \
- cortex_arcadia_reset_func, \
- cortex_arcadia_core_pwr_dwn
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 7bd3e74..1dd0b49 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -225,7 +225,8 @@
#Include all CPUs to build to support all-errata build.
ifeq (${ENABLE_ERRATA_ALL},1)
BUILD_CPUS_WITH_NO_FVP_MODEL = 1
- FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
+ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \
+ lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a520.S \
lib/cpus/aarch64/cortex_a725.S \
lib/cpus/aarch64/cortex_x1.S \
@@ -241,11 +242,9 @@
# travis/gelas need these
FEAT_PABANDON := 1
ERRATA_SME_POWER_DOWN := 1
- FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \
- lib/cpus/aarch64/cortex_gelas.S \
+ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_gelas.S \
lib/cpus/aarch64/nevis.S \
lib/cpus/aarch64/travis.S \
- lib/cpus/aarch64/cortex_arcadia.S \
lib/cpus/aarch64/cortex_alto.S
endif