diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 4a41901..a1ffd5a 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -33,8 +33,95 @@
 
 static struct console_stm32 console;
 
-void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
-				  u_register_t arg2, u_register_t arg3)
+static void print_reset_reason(void)
+{
+	uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
+
+	if (rstsr == 0U) {
+		WARN("Reset reason unknown\n");
+		return;
+	}
+
+	INFO("Reset reason (0x%x):\n", rstsr);
+
+	if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
+		if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
+			INFO("System exits from STANDBY\n");
+			return;
+		}
+
+		if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
+			INFO("MPU exits from CSTANDBY\n");
+			return;
+		}
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
+		INFO("  Power-on Reset (rst_por)\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
+		INFO("  Brownout Reset (rst_bor)\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
+		if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
+			INFO("  System reset generated by MCU (MCSYSRST)\n");
+		} else {
+			INFO("  Local reset generated by MCU (MCSYSRST)\n");
+		}
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
+		INFO("  System reset generated by MPU (MPSYSRST)\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
+		INFO("  Reset due to a clock failure on HSE\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
+		INFO("  IWDG1 Reset (rst_iwdg1)\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
+		INFO("  IWDG2 Reset (rst_iwdg2)\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
+		INFO("  MPU Processor 0 Reset\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
+		INFO("  MPU Processor 1 Reset\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
+		INFO("  Pad Reset from NRST\n");
+		return;
+	}
+
+	if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
+		INFO("  Reset due to a failure of VDD_CORE\n");
+		return;
+	}
+
+	ERROR("  Unidentified reset reason\n");
+}
+
+void bl2_el3_early_platform_setup(u_register_t arg0,
+				  u_register_t arg1 __unused,
+				  u_register_t arg2 __unused,
+				  u_register_t arg3 __unused)
 {
 	stm32mp1_save_boot_ctx_address(arg0);
 }
@@ -59,12 +146,38 @@
 void bl2_el3_plat_arch_setup(void)
 {
 	int32_t result;
-	struct dt_node_info dt_dev_info;
+	struct dt_node_info dt_uart_info;
 	const char *board_model;
 	boot_api_context_t *boot_context =
 		(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
 	uint32_t clk_rate;
 
+	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
+			BL_CODE_END - BL_CODE_BASE,
+			MT_CODE | MT_SECURE);
+
+	/* Prevent corruption of preloaded BL32 */
+	mmap_add_region(BL32_BASE, BL32_BASE,
+			BL32_LIMIT - BL32_BASE,
+			MT_MEMORY | MT_RO | MT_SECURE);
+
+	/* Map non secure DDR for BL33 load and DDR training area restore */
+	mmap_add_region(STM32MP1_DDR_BASE,
+			STM32MP1_DDR_BASE,
+			STM32MP1_DDR_MAX_SIZE,
+			MT_MEMORY | MT_RW | MT_NS);
+
+	/* Prevent corruption of preloaded Device Tree */
+	mmap_add_region(DTB_BASE, DTB_BASE,
+			DTB_LIMIT - DTB_BASE,
+			MT_MEMORY | MT_RO | MT_SECURE);
+
+	configure_mmu();
+
+	if (dt_open_and_check() < 0) {
+		panic();
+	}
+
 	/*
 	 * Disable the backup domain write protection.
 	 * The protection is enable at each reset by hardware
@@ -88,28 +201,8 @@
 		mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
 	}
 
-	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
-			BL_CODE_END - BL_CODE_BASE,
-			MT_CODE | MT_SECURE);
-
-	/* Prevent corruption of preloaded BL32 */
-	mmap_add_region(BL32_BASE, BL32_BASE,
-			BL32_LIMIT - BL32_BASE,
-			MT_MEMORY | MT_RO | MT_SECURE);
-
-	/* Prevent corruption of preloaded Device Tree */
-	mmap_add_region(DTB_BASE, DTB_BASE,
-			DTB_LIMIT - DTB_BASE,
-			MT_MEMORY | MT_RO | MT_SECURE);
-
-	configure_mmu();
-
 	generic_delay_timer_init();
 
-	if (dt_open_and_check() < 0) {
-		panic();
-	}
-
 	if (stm32mp1_clk_probe() < 0) {
 		panic();
 	}
@@ -118,12 +211,12 @@
 		panic();
 	}
 
-	result = dt_get_stdout_uart_info(&dt_dev_info);
+	result = dt_get_stdout_uart_info(&dt_uart_info);
 
 	if ((result <= 0) ||
-	    (dt_dev_info.status == 0U) ||
-	    (dt_dev_info.clock < 0) ||
-	    (dt_dev_info.reset < 0)) {
+	    (dt_uart_info.status == 0U) ||
+	    (dt_uart_info.clock < 0) ||
+	    (dt_uart_info.reset < 0)) {
 		goto skip_console_init;
 	}
 
@@ -131,25 +224,25 @@
 		goto skip_console_init;
 	}
 
-	if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) {
+	if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
 		goto skip_console_init;
 	}
 
-	stm32mp1_reset_assert((uint32_t)dt_dev_info.reset);
+	stm32mp1_reset_assert((uint32_t)dt_uart_info.reset);
 	udelay(2);
-	stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset);
+	stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset);
 	mdelay(1);
 
-	clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock);
+	clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock);
 
-	if (console_stm32_register(dt_dev_info.base, clk_rate,
+	if (console_stm32_register(dt_uart_info.base, clk_rate,
 				   STM32MP1_UART_BAUDRATE, &console) == 0) {
 		panic();
 	}
 
 	board_model = dt_get_board_model();
 	if (board_model != NULL) {
-		NOTICE("%s\n", board_model);
+		NOTICE("Model: %s\n", board_model);
 	}
 
 skip_console_init:
@@ -162,5 +255,7 @@
 
 	stm32mp1_arch_security_setup();
 
+	print_reset_reason();
+
 	stm32mp1_io_setup();
 }