Merge pull request #319 from vwadekar/tegra-video-mem-aperture-v3
Reserve a Video Memory aperture in DRAM memory
diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md
index 242e8db..e4f9a05 100644
--- a/docs/plat/nvidia-tegra.md
+++ b/docs/plat/nvidia-tegra.md
@@ -15,7 +15,16 @@
* plat/nvidia/tegra/common - Common code for all Tegra SoCs
* plat/nvidia/tegra/soc/txxx - Chip specific code
+Trusted OS dispatcher
+=====================
+Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of
+them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd'
+on the command line while preparing a bl31 image. This allows other Trusted OS
+vendors to use the upstream code and include their dispatchers in the image
+without changing any makefiles.
+
Preparing the BL31 image to run on Tegra SoCs
===================================================
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
-TARGET_SOC=<target-soc e.g. t210> all
+TARGET_SOC=<target-soc e.g. t210> BL32=<path-to-trusted-os-binary> \
+SPD=<dispatcher e.g. tlkd> all
diff --git a/docs/optee-dispatcher.md b/docs/spd/optee-dispatcher.md
similarity index 100%
rename from docs/optee-dispatcher.md
rename to docs/spd/optee-dispatcher.md
diff --git a/docs/tlk-dispatcher.md b/docs/spd/tlk-dispatcher.md
similarity index 93%
rename from docs/tlk-dispatcher.md
rename to docs/spd/tlk-dispatcher.md
index a2212b5..890b35e 100644
--- a/docs/tlk-dispatcher.md
+++ b/docs/spd/tlk-dispatcher.md
@@ -10,10 +10,11 @@
just needs to compile, any BL32 image would do. To use TLK as the BL32, please
refer to the "Build TLK" section.
-Once a BL32 is ready, TLKD can be compiled using the following command:
+Once a BL32 is ready, TLKD can be included in the image using the following
+command:
CROSS_COMPILE=<path_to_linaro_chain>/bin/aarch64-none-elf- make NEED_BL1=0
-NEED_BL2=0 BL32=<path_to_BL32_image> PLAT=<platform> all
+NEED_BL2=0 BL32=<path_to_BL32_image> PLAT=<platform> SPD=tlkd all
_
Trusted Little Kernel (TLK)
===========================
diff --git a/docs/user-guide.md b/docs/user-guide.md
index c1cadbb..9a9334f 100644
--- a/docs/user-guide.md
+++ b/docs/user-guide.md
@@ -322,7 +322,7 @@
#### ARM development platform specific build options
-* `ARM_TSP_RAM_LOCATION_ID`: location of the TSP binary. Options:
+* `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options:
- `tsram` : Trusted SRAM (default option)
- `tdram` : Trusted DRAM (if available)
- `dram` : Secure region in DRAM (configured by the TrustZone controller)
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index 056c00d..268438f 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -37,11 +37,9 @@
/*************************************************************************
* Definitions common to all ARM Compute SubSystems (CSS)
*************************************************************************/
-#define MHU_SECURE_BASE ARM_SHARED_RAM_BASE
-#define MHU_SECURE_SIZE ARM_SHARED_RAM_SIZE
#define MHU_PAYLOAD_CACHED 0
-#define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE
+#define TRUSTED_MAILBOXES_BASE ARM_TRUSTED_SRAM_BASE
#define TRUSTED_MAILBOX_SHIFT 4
#define NSROM_BASE 0x1f000000
@@ -66,11 +64,29 @@
#define CSS_IRQ_TZC 80
#define CSS_IRQ_TZ_WDOG 86
-/* SCP <=> AP boot configuration */
-#define SCP_BOOT_CFG_ADDR 0x04000080
+/*
+ * SCP <=> AP boot configuration
+ *
+ * The SCP/AP boot configuration is a 32-bit word located at a known offset from
+ * the start of the Trusted SRAM. Part of this configuration is which CPU is the
+ * primary, according to the shift and mask definitions below.
+ *
+ * Note that the value stored at this address is only valid at boot time, before
+ * the BL3-0 image is transferred to SCP.
+ */
+#define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80)
#define PRIMARY_CPU_SHIFT 8
#define PRIMARY_CPU_BIT_WIDTH 4
+/*
+ * Base address of the first memory region used for communication between AP
+ * and SCP. Used by the BOM and SCPI protocols.
+ *
+ * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which
+ * means the SCP/AP configuration data gets overwritten when the AP initiates
+ * communication with the SCP.
+ */
+#define SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80)
#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
CSS_DEVICE_BASE, \
diff --git a/plat/arm/css/common/css_scp_bootloader.c b/plat/arm/css/common/css_scp_bootloader.c
index 6cf1667..acc7351 100644
--- a/plat/arm/css/common/css_scp_bootloader.c
+++ b/plat/arm/css/common/css_scp_bootloader.c
@@ -60,7 +60,7 @@
* Unlike the SCPI protocol, the boot protocol uses the same memory region
* for both AP -> SCP and SCP -> AP transfers; define the address of this...
*/
-#define BOM_SHARED_MEM (MHU_SECURE_BASE + 0x0080)
+#define BOM_SHARED_MEM SCP_COM_SHARED_MEM_BASE
#define BOM_CMD_HEADER ((bom_cmd_t *) BOM_SHARED_MEM)
#define BOM_CMD_PAYLOAD ((void *) (BOM_SHARED_MEM + sizeof(bom_cmd_t)))
@@ -181,7 +181,7 @@
BOM_CMD_HEADER->id = BOOT_CMD_DATA;
cmd_data_payload = BOM_CMD_PAYLOAD;
- cmd_data_payload->offset = (uintptr_t) image - MHU_SECURE_BASE;
+ cmd_data_payload->offset = (uintptr_t) image - ARM_TRUSTED_SRAM_BASE;
cmd_data_payload->block_size = image_size;
scp_boot_message_send(sizeof(*cmd_data_payload));
diff --git a/plat/arm/css/common/css_scpi.c b/plat/arm/css/common/css_scpi.c
index 9127259..0a4eafe 100644
--- a/plat/arm/css/common/css_scpi.c
+++ b/plat/arm/css/common/css_scpi.c
@@ -37,8 +37,8 @@
#include "css_mhu.h"
#include "css_scpi.h"
-#define SCPI_SHARED_MEM_SCP_TO_AP (MHU_SECURE_BASE + 0x0080)
-#define SCPI_SHARED_MEM_AP_TO_SCP (MHU_SECURE_BASE + 0x0180)
+#define SCPI_SHARED_MEM_SCP_TO_AP SCP_COM_SHARED_MEM_BASE
+#define SCPI_SHARED_MEM_AP_TO_SCP (SCP_COM_SHARED_MEM_BASE + 0x100)
#define SCPI_CMD_HEADER_AP_TO_SCP \
((scpi_cmd_t *) SCPI_SHARED_MEM_AP_TO_SCP)
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index d126501..dea8457 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -83,7 +83,7 @@
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
-static entry_point_info_t bl33_image_ep_info;
+static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
(uint64_t)TZDRAM_SIZE, (uintptr_t)NULL
};
@@ -103,6 +103,9 @@
if (type == NON_SECURE)
return &bl33_image_ep_info;
+ if (type == SECURE)
+ return &bl32_image_ep_info;
+
return NULL;
}
@@ -135,10 +138,11 @@
plat_crash_console_init();
/*
- * Copy BL3-3 entry point information.
+ * Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
bl33_image_ep_info = *from_bl2->bl33_ep_info;
+ bl32_image_ep_info = *from_bl2->bl32_ep_info;
/*
* Parse platform specific parameters - TZDRAM aperture size and
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index 6be777e..d4b0ce2 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -69,8 +69,11 @@
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
+#define BL31_SIZE 0x20000
#define BL31_BASE TZDRAM_BASE
-#define BL31_LIMIT (TZDRAM_BASE + 0x11FFF)
+#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
+#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
+#define BL32_LIMIT TZDRAM_END
/*******************************************************************************
* Platform specific page table and MMU setup constants