Set processor endianness immediately after RESET
SCTLR_EL3.EE is being configured too late in bl1_arch_setup() and
bl31_arch_setup() after data accesses have already occured on
the cold and warm boot paths.
This control bit must be configured immediately on CPU reset to
match the endian state of the firmware (little endian).
Fixes ARM-software/tf-issues#145
Change-Id: Ie12e46fbbed6baf024c30beb50751591bb8c8655
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c
index 758b8e8..1b14246 100644
--- a/bl1/aarch64/bl1_arch_setup.c
+++ b/bl1/aarch64/bl1_arch_setup.c
@@ -39,10 +39,9 @@
{
unsigned long tmp_reg = 0;
- /* Enable alignment checks and set the exception endianess to LE */
+ /* Enable alignment checks */
tmp_reg = read_sctlr_el3();
tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
- tmp_reg &= ~SCTLR_EE_BIT;
write_sctlr_el3(tmp_reg);
/*