Merge "fix(s32g274a): avoid overwriting const fields" into integration
diff --git a/Makefile b/Makefile
index 2ba4fa7..d73fc87 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 2
-VERSION_MINOR := 10
+VERSION_MINOR := 11
# VERSION_PATCH is only used for LTS releases
VERSION_PATCH := 0
VERSION := ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
@@ -35,6 +35,17 @@
# Configure the toolchains used to build TF-A and its tools
################################################################################
+#
+# The clean and check targets do not behave correctly if the user's environment
+# does not appropriately configure a toolchain. While we try to find a permanent
+# solution to this, do not try to detect any toolchains if we are building
+# exclusively with targets which do not use any toolchain tools.
+#
+
+ifeq ($(filter-out check% %clean doc %tool,$(or $(MAKECMDGOALS),all)),)
+ toolchains :=
+endif
+
include ${MAKE_HELPERS_DIRECTORY}toolchain.mk
# Assertions enabled for DEBUG builds by default
@@ -299,7 +310,7 @@
-fsanitize-undefined-trap-on-error
endif #(${SANITIZE_UB},trap)
-GCC_V_OUTPUT := $(shell $($(ARCH)-cc) -v 2>&1)
+GCC_V_OUTPUT := $(if $($(ARCH)-cc),$(shell $($(ARCH)-cc) -v 2>&1))
TF_LDFLAGS += -z noexecstack
@@ -1331,6 +1342,8 @@
PSCI_EXTENDED_STATE_ID \
PSCI_OS_INIT_MODE \
RESET_TO_BL31 \
+ RME_GPT_BITLOCK_BLOCK \
+ RME_GPT_MAX_BLOCK \
SEPARATE_CODE_AND_RODATA \
SEPARATE_BL2_NOLOAD_REGION \
SEPARATE_NOBITS_REGION \
diff --git a/changelog.yaml b/changelog.yaml
index ad9c9b5..6f2458e 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -152,11 +152,15 @@
- title: Self-hosted Trace Extensions (FEAT_TRF)
scope: trf
+ - title: DynamIQ Shared Unit (DSU)
+ scope: dsu
+
- title: Platforms
scope: platforms
deprecated:
- plat/common
+ - plat
subsections:
- title: Allwinner
@@ -222,6 +226,9 @@
- title: SGI-575
scope: sgi575
+ - title: RD-E1-Edge
+ scope: rde1edge
+
- title: RD-N1-Edge
scope: rdn1edge
@@ -237,6 +244,9 @@
deprecated:
- board/rdn2
+ deprecated:
+ - neoverse
+
- title: TC
scope: tc
@@ -651,12 +661,11 @@
- plat/xilinx/versal
- plat/versal
- subsections:
- - title: Versal NET
- scope: versal-net
+ - title: Versal NET
+ scope: versal-net
- deprecated:
- - versal_net
+ deprecated:
+ - versal_net
- title: ZynqMP
scope: zynqmp
@@ -752,6 +761,9 @@
deprecated:
- errata_abi
+ - title: ChromeOS
+ scope: cros
+
- title: Libraries
scope: lib
@@ -834,6 +846,9 @@
- title: Firmware Handoff
scope: handoff
+ - title: Exception Handling Framework (EHF)
+ scope: ehf
+
- title: Drivers
subsections:
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 1f68927..85cc612 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -63,8 +63,8 @@
:|G|: `bipinravi-arm`_
:|M|: Joanna Farley <joanna.farley@arm.com>
:|G|: `joannafarley-arm`_
-:|M|: Okash Khawaja <okash@google.com>
-:|G|: `bytefire`_
+:|M|: Jidong Sun <jidong@google.com>
+:|G|: `jidongsun`_
:|M|: Varun Wadekar <vwadekar@nvidia.com>
:|G|: `vwadekar`_
:|M|: Yann Gautier <yann.gautier@st.com>
@@ -114,6 +114,8 @@
:|M|: Marc Bonnici <marc.bonnici@arm.com>
:|G|: `marcbonnici`_
:|F|: services/std_svc/spm/el3_spmc/\*
+:|F|: include/services/el3_spmc\_\*
+:|F|: include/services/spmc_svc.h
Secure Partition Manager Dispatcher (SPMD)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -121,7 +123,13 @@
:|G|: `odeprez`_
:|M|: Joao Alves <Joao.Alves@arm.com>
:|G|: `J-Alves`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
:|F|: services/std_svc/spmd/\*
+:|F|: plat/common/plat_spmd_manifest.c
+:|F|: include/services/ffa_svc.h
+:|F|: include/services/el3_spmd_logical_sp.h
+:|F|: include/services/spmd_svc.h
Exception Handling Framework (EHF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -131,6 +139,16 @@
:|G|: `manish-pandey-arm`_
:|F|: bl31/ehf.c
+Runtime Exceptions and Interrupt Management
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: bl31/aarch64/
+:|F|: bl31/interrupt_mgmt.c
+:|F|: include/bl31/interrupt_mgmt.h
+
Realm Management Monitor Dispatcher (RMMD)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
@@ -216,12 +234,14 @@
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
:|F|: lib/psci/
+:|F|: include/lib/psci/
DebugFS
^^^^^^^
:|M|: Olivier Deprez <olivier.deprez@arm.com>
:|G|: `odeprez`_
:|F|: lib/debugfs/
+:|F|: include/lib/debugfs.h
Firmware Configuration Framework (FCONF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -232,6 +252,10 @@
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
:|F|: lib/fconf/
+:|F|: plat/arm/common/fconf/
+:|F|: include/lib/fconf/
+:|F|: include/plat/arm/common/arm_fconf\_\*
+:|F|: include/plat/arm/common/fconf\_\*
Performance Measurement Framework (PMF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -253,6 +277,7 @@
:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
:|G|: `laurenw-arm`_
:|F|: lib/cpus/
+:|F|: include/lib/cpus/
Reliability Availability Serviceabilty (RAS) framework
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -380,6 +405,8 @@
:|M|: Manish Pandey <manish.pandey2@arm.com>
:|G|: `manish-pandey-arm`_
:|F|: services/std_svc/drtm
+:|F|: include/plat/common/plat_drtm.h
+:|F|: include/services/drtm_svc.h
PSA Firmware Update
^^^^^^^^^^^^^^^^^^^
@@ -433,6 +460,32 @@
:|F|: lib/transfer_list
:|F|: include/lib/transfer_list.h
+Context Management
+^^^^^^^^^^^^^^^^^^
+:|M|: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
+:|G|: `jayanthchidanand-arm`_
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: bl1/aarch32/bl1_context_mgmt.c
+:|F|: bl1/aarch64/bl1_context_mgmt.c
+:|F|: bl31/bl31_context_mgmt.c
+:|F|: lib/el3_runtime/
+:|F|: include/lib/el3_runtime/
+
+Runtime Services
+^^^^^^^^^^^^^^^^
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: services/std_svc/std_svc_setup.c
+:|F|: common/runtime_svc.c
+:|F|: include/common/runtime_svc.h
+:|F|: include/services/arm_arch_svc.h
+:|F|: include/services/std_svc.h
+
Platform Ports
~~~~~~~~~~~~~~
@@ -604,7 +657,6 @@
:|M|: Avi Fishman <avi.fishman@nuvoton.com>
:|G|: `avifishman`_
:|F|: docs/plat/npcm845x.rst
-:|F|: drivers/nuvoton/
:|F|: include/drivers/nuvoton/
:|F|: include/plat/nuvoton/
:|F|: plat/nuvoton/
@@ -983,7 +1035,7 @@
.. _bijucdas: https://github.com/bijucdas
.. _bipinravi-arm: https://github.com/bipinravi-arm
.. _bryanodonoghue: https://github.com/bryanodonoghue
-.. _bytefire: https://github.com/bytefire
+.. _jidongsun: https://github.com/jidongsun
.. _carlocaione: https://github.com/carlocaione
.. _chandnich: https://github.com/chandnich
.. _ChiaweiW: https://github.com/chiaweiw
@@ -1061,3 +1113,7 @@
.. _vwadekar: https://github.com/vwadekar
.. _xueliang-zhong-arm: https://github.com/xueliang-zhong-arm
.. _Yann-lms: https://github.com/Yann-lms
+
+--------------
+
+*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/change-log.md b/docs/change-log.md
index cfc8c56..1e6647f 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,6 +3,924 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+## [2.11.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.10.0..refs/tags/v2.11.0) (2024-05-17)
+
+### ⚠ BREAKING CHANGES
+
+- **Architecture**
+
+ - **Memory Tagging Extension2**
+
+ - Any platform or downstream code trying to use
+ SCR_EL3.ATA bit(26) will see failures as this is now moved to be
+ used only with FEAT_MTE2 with
+ commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2
+
+ **See:** remove mte, mte_perm ([c282384](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c282384dbb45b6185b4aba14efebbad110d18e49))
+
+- **Services**
+
+ - **SPM**
+
+ - **SPMD**
+
+ - Given the optimizations made in TF-A SPMD to simplify NS EL1 context
+ management, platform integrators must use SPMC binaries built by
+ picking commits after 2fc6dcfa97e05159f95859fcf68db3031586f8c7 from
+ hafnium repository.
+
+ **See:** skip NS EL1 context save & restore operations ([2d960a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d960a11601be6e7f24c38d84b2a4fdbb52efb9b))
+
+- **Drivers**
+
+ - **Arm**
+
+ - **RSE**
+
+ - remove PLAT_RSS_NOT_SUPPORTED build option
+
+ **See:** remove PLAT_RSS_NOT_SUPPORTED build option ([878354a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/878354a845cbc51c198b879d3d92ed472e21889c))
+
+ - **FWU**
+
+ - add a config flag for including image info in the FWU metadata ([11d05a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/11d05a77295885f27530cf07029ebc2b36f49918))
+ - add a function to obtain an alternate FWU bank to boot ([26aab79](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/26aab79560a2281c4207b01102495459c2bddefc))
+ - add some sanity checks for the FWU metadata ([d2566cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2566cfb896672ea07c31c37e7acd9ef77abc4fb))
+ - document the config flag for including image info in the FWU metadata ([7ae1619](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ae16196cc73a580f298734bb98f2ccb210e3ba9))
+ - migrate FWU metadata structure to version 2 ([a89d58b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a89d58bb204c00db260225859bce0b55aa5e2385))
+
+### New Features
+
+- **Architecture**
+
+ - **CPU feature / ID register handling in general**
+
+ - add cortex-a35 l2 extended control register ([a727d59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a727d59d9c1ef5ecf2f221ce289506da2011dda1))
+ - add feature detection for FEAT_CSV2_3 ([30019d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30019d8698b219d4a642dc59e7178006f59654ff))
+ - added few helper functions ([30f05b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30f05b4f5db605ddc1a3ca0ae0cbd13ed0e728b6))
+
+ - **DynamIQ Shared Unit (DSU)**
+
+ - save/restore DSU PMU register ([f99a69c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f99a69c386ce5448edfc47eaf146d1a20ac8216e))
+
+ - **Memory Tagging Extension2**
+
+ - add mte2 feat ([8e39788](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e3978899a481484d8c60bf276be503aebd43afb))
+
+- **Platforms**
+
+ - update SZ_* macros ([6d511a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d511a8c31f0d792695566ae75c8f7b08b3b7236))
+
+ - **Arm**
+
+ - add COT_DESC_IN_DTB option for CCA CoT ([b76a43c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b76a43c9382e85969cac896cd4d5d6774d0d1553))
+ - add trusty_sp_fw_config build option ([0686a01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0686a01b0cacb9aab840a5c334409b5739a95a97))
+ - move GPT setup to common BL source ([341df6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/341df6af6eb911ffd175e129f61fc59efcf9fcea))
+ - retrieve GPT related data from platform ([86e4859](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86e4859a05614b40ff3cf38f8bd4efc856c546fe))
+ - support FW handoff b/w BL1 & BL2 ([9c11ed7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c11ed7e3e5536ad1fcb9190560e0368da9c5ab5))
+ - support FW handoff b/w BL2 & BL31 ([a5566f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5566f65fd1be689ca5c63baa1f5b61b40960c8d))
+ - add platform API that gets cluster ID ([e6ae019](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6ae019a84c4d2ad2d2825b32fbcbe304752e3ae))
+
+ - **CSS**
+
+ - initialise generic timer early in the boot ([3447ba1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3447ba1f0405a8590ec31e4b79737efe151c3d5b))
+
+ - **FVP**
+
+ - add CCA CoT in DTB support ([4c79b86](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4c79b86ed6a36b572cf9e96f0269eb5dd0b46d5f))
+ - add stdout-path ([8c30a0c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c30a0c7fe0162de0618b26fb34cc91ea582e5f7))
+ - add support for virto-net, virtio-9p and virtio-rng ([51b8b9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/51b8b9c3c46cec87ebb7b484727c80ff29d73057))
+ - added calls to unprotect/protect memory ([6873088](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6873088c2cd6983025b6777d4c3bde912eade571))
+ - delegate FFH RAS handling to SP ([d07d4d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d07d4d63374b0d155b9281f9fcaf6b44f18117c8))
+ - remove left-over RSS usage ([a1726fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1726fa7ffecdcc8f8f4d09bd0bdc97ef3b72f11))
+
+ - **Neoverse-RD**
+
+ - add scope for RD-V1 ([86a4949](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/86a4949fd012a9912c8bf909d14e20657bba2240))
+ - add scope for RD-V1-MC ([6fb16da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fb16dac6e6672040ec80f85f2f337f52cf3f3d3))
+ - add scope for SGI-575 ([18b5070](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18b50707f7732a8b3deb46d8d011566199711c0b))
+ - disable SPMD_SPM_AT_SEL2 for A75/V1/N1 platforms ([b9c3273](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9c32730e5b7efe5170ed3c0dda7ab9db397c478))
+ - disable SPMD_SPM_AT_SEL2 for N2/V2 platforms ([301c017](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/301c01748ea717d0f2cf3ba1f0a2fe389b6fb155))
+ - enable AMU if supported by the platform ([fed9368](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fed9368529e5bc2c9111ac5a743688166661fd8f))
+ - remove unused SGI_PLAT build-option ([2d32517](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d32517ce64886f154c6d509f80d0fcde05dc498))
+
+ - **SGI-575**
+
+ - remove SGI-575 from deprecated list ([f104eec](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f104eecdea209af87de43c62811a0a9456f2838c))
+
+ - **RD-E1-Edge**
+
+ - remove support for RD-E1-Edge ([c69253c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c69253cc3ad3063380c8f905125fe85f6d942d09))
+
+ - **RD-N1-Edge**
+
+ - remove RD-N1-Edge from deprecated list ([78b7939](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/78b793956f3a86a3dd62394c858ae9ee41379b8b))
+
+ - **RD-N2**
+
+ - enable NEOVERSE_Nx_EXTERNAL_LLC flag ([ab2b363](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab2b3632171dd5488952ba3f68693e490857e9dc))
+ - add dts for secure partition ([49df726](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49df7261be44d5199a930c95667edb6b878355d1))
+ - enable AMU if present on the platform ([2cfedfa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2cfedfad9c2c59316adf17d4f0ee561b50a041b6))
+ - enable MTE2 if present on the platform ([3a5b375](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3a5b3753033561cb5d7cd7aace634cc66eab0fa7))
+ - update power message value to 0 ([08f6398](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/08f6398b2b9566812cd110498e3135dfc2e3e494))
+
+ - **TC**
+
+ - add arm_ffa node in dts ([4fc4e9c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fc4e9c969930d83f1144441199301d3b4b34a5a))
+ - add DPE backend to the measured boot framework ([e7f1181](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7f1181f8a7729acb07ebac86944e36932bcd09e))
+ - add DPE context handle node to device tree ([1f47a71](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f47a7133f7fe7fb038aca97fc93533964b2b429))
+ - add dummy TRNG support to be able to boot pVMs ([7be391d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7be391d1ce5683c717fcf2be584f3d294ebc2bf3))
+ - add firmware update secure partition ([d062872](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0628728a627ee11c97839640d404221a74c3a65))
+ - add memory node in the device tree ([5ee4deb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ee4deb8e69175f57fa51519ef37e3674aa6b9a0))
+ - add PMU entry ([553b06b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/553b06b5d4f7ec8e49796e0ffdf081bf5cf30d53))
+ - add RSS SDS region right after SCMI payload ([6f503e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6f503e0eea23a2663ed5cbfe9b925e1e0d65c236))
+ - add save/restore DSU PMU register support ([b87d7ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b87d7ab13f4b03f872c3c4a3dd7c755baf3a38d3))
+ - add SCMI power domain and IOMMU toggles ([a658b46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a658b46dc74ceaa51d119bd7bd9eccdefb0cc455))
+ - add spmc manifest with trusty sp ([ba197f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba197f5f708fe8e033971c6f4d5b25f6783aaa45))
+ - add TC3 platform definitions ([62320dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62320dc4fd2c13d9f4b227fe73cad2a79bdba42c))
+ - allow booting from DRAM ([18f754a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/18f754a275083ea66823b1c9f39e234cf430140e))
+ - choose the DPU address and irq based on the target ([8e94163](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8e94163ec041f2d7df41c2dfd8625c06655ba08e))
+ - enable gpu/dpu scmi power domain and also gpu perf domain ([127eabe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/127eabeddfc4fb596a1b499fe68ee6f7e5b5b6d5))
+ - factor in FVP/FPGA differences ([1b8ed09](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b8ed0993fc5c04f76d949df7e2851e67040bbf9))
+ - get the parent component provided DPE context_handle ([467bdf2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/467bdf26b64a38cfbfb3bf8ab915eb97eb6b3037))
+ - group components into certificates ([6df8d76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6df8d7647dad5c347d363554d25e590d24eb05e5))
+ - interrupt numbers for `smmu_700` ([2c406dd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2c406ddaf700e0f1c80535e309a2245b9e0bee92))
+ - introduce an FPGA subvariant and TC3 CPUs ([a02bb36](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a02bb36caa521259ae57a904dedb7fd4e6a51340))
+ - pass the DTB address to BL33 in R0 ([638e4a9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/638e4a92d80346b4d46ef2cc5fbb7941d1b7fd31))
+ - provide a mock mbedtls-random generation function ([a877818](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8778185d2fd2b80cee8af7879ecb92be1aa3898))
+ - share DPE context handle with child component ([03d388d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/03d388d8e3eb5c6cce65afba060a16fae83d4d12))
+
+ - **Intel**
+
+ - add in QSPI ECC for Linux ([4d122e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4d122e5f199ad1531650ae11de5121057cfc0855))
+ - enable query of fip offset on RSU ([6cbe2c5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cbe2c5d19c4af0ba6bbba049962bf55454da8bb))
+ - enable SDMMC frontdoor load for ATF->Linux ([32a87d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32a87d440087e0a71765a61ec341af7cfcfbda97))
+ - increase bl2 size limit ([2d46b2e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d46b2e46189120b6779cd27ec6bd6ec9901f72c))
+ - restructure watchdog ([47ca43b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47ca43bcb4565a992bf527f68e1ff60fc036fd12))
+ - support QSPI ECC Linux for Agilex ([d6ae69c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6ae69c8c69016d05d64752538aad53f319b88a2))
+ - support QSPI ECC Linux for N5X ([6cf16b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cf16b36821b9f2a60ed9abbaa593ef62b8b9f2b))
+ - support QSPI ECC Linux for Stratix10 ([8be16e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8be16e44cf0143e8651090d80bd14194aa78b1f2))
+ - support query of fip offset using RSU ([62be2a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62be2a1ae3efcba0bb8b7ec8ef73b2a0f5a437e3))
+ - support SDM mailbox safe inject seu error for Linux ([fffcb25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fffcb25c3c2171624c582d92173154f570708a9a))
+ - support wipe DDR after calibration ([68bb3e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68bb3e836e93b271f9f1c05787025dd3f04dd788))
+
+ - **MediaTek**
+
+ - remove bl32 flag for mtk_bl ([9c41cc1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c41cc182dd7acf541565ab3df7a4261fb7eaf1b))
+
+ - **MT8188**
+
+ - add secure iommu support ([5fb5ff5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5fb5ff5694c1bcf0ddfc972600b69d7494ca6645))
+ - remove apusys kernel handler usage constraints ([0c77651](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c77651fb47c7ffd4b1b37a74aea77373179ab5d))
+
+ - **NXP**
+
+ - **i.MX**
+
+ - **i.MX 8M**
+
+ - add 3600 MTps DDR PLL rate ([f1bb459](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f1bb459c3192eb6b3fc6b9b77658d82227eae2d5))
+ - add defines for csu_sa access security ([81de503](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81de50372c9192098118fc8bddaf086a620add87))
+ - add imx csu_sa enum type defines for imx8m ([2ac4909](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2ac4909a5ec0a50a75cab9bb587fb1b8e592794d))
+ - make bl33 start configurable via PRELOADED_BL33_BASE ([9260a8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9260a8c818aadbf513b2744cad978c18d0f65a8e))
+ - obtain boot image set for imx8mn/mp ([6d2c502](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d2c502afb845e7af94c610ab5a375b868c885ba))
+
+ - **i.MX 8M Mini**
+
+ - restrict peripheral access to secure world ([1156c76](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1156c76361c170c83c6b9a9dd7c22aa401a4ce2e))
+ - set and lock almost all peripherals as non-secure ([f4b11e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4b11e59b81af3e485e6992b10b50b362902eee1))
+
+ - **i.MX 8M Plus**
+
+ - restrict peripheral access to secure world ([0324081](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0324081af0105af536992c8ced2caa5a1928010f))
+ - set and lock almost all peripherals as non-secure ([cba7daa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cba7daa10576684670e06d05ff02888a5b4f16bf))
+
+ - **i.MX 8Q**
+
+ - detect console base address during runtime ([52ee817](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/52ee8173041c46aafcfa43f004029dddbfa9f9b5))
+
+ - **i.MX 8ULP**
+
+ - add a flag check for the ddr status ([4fafccb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fafccb9a8f7b35406b08743f6d9c9b519b01c61))
+ - add APD power down mode(PD) support in system suspend ([478af8d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/478af8d3c34576793a820733ddba6449c2cf2fac))
+ - add i.MX8ULP basic support ([fcd41e8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fcd41e8692ce8e8fc98d069bc131820cbf83c55c))
+ - add memory region policy ([5fd0642](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5fd06421f8bf9f5b67e73828281534f14f302630))
+ - add OPTEE support ([e7b82a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e7b82a7d2fa1fc3f32724e6836b8f6078d20c103))
+ - add some delay before cmc1 access ([c514d3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c514d3cfa7640313c4d78674df9d7cbe9227420b))
+ - add system power off support ([891c547](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/891c547e9658c1827559d8da5e3b87de5a2e9f6a))
+ - add the basic support for idle & system suspned ([daa4478](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/daa4478a3cb2f86501c37e5a301cd4d6a6e60ee6))
+ - add the initial XRDC support ([ac5d69b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ac5d69b628736f66f72e99532656105fdc07a3fe))
+ - add trusty support ([e853041](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e853041920b15b77839027ab802d0cd9a08c7c35))
+ - adjust the dram mapped region ([8d50c91](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8d50c91b476474cc403c30eb6de6af28cb246e5a))
+ - adjust the voltage when sys dvfs enabled ([416c443](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/416c4433f0047a86165e450e60f93020c561151b))
+ - allocated caam did for the non secure world ([7c5eedc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7c5eedca4c7f176448e6b92eb5c22ee2ea45e70a))
+ - allow RTD to reset APD through MU ([ea1f7a2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ea1f7a2e109181f19f5bdeb71533e7dfda753df7))
+ - ddrc switch auto low power and software interface ([ee25e6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ee25e6a51bf20c92471e737ccba98af4a74d1383))
+ - enable 512KB cache after resume on imx8ulp ([bcca70b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcca70b9688c5effa0731f39e2b209071f54be2c))
+ - enable the DDR frequency scaling support ([caee273](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/caee2733ba4e7a09ea656b0be85f150a275cc57c))
+ - give HIFI4 DSP access to more resources ([351976b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/351976bb063cca7866e214a6bda9302f9ab018b3))
+ - not power off LPAV PD when LPAV owner is RTD ([ab787db](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ab787dba7726bdf58c15626e5cc9a3525aade8a3))
+ - protect TEE region for secure access only ([ff5e179](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ff5e1793b95ed4297deae72cdb665178e6e72e44))
+ - update the upower config for power optimization ([36af80c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/36af80c2b420cb32ff57273eda0d7d0e93b49153))
+ - update XRDC for ELE to access DDR with CA35 DID ([d159c00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d159c00532afe50686dd92215de9b420d60502f6))
+
+ - **S32G274A**
+
+ - add S32G274ARDB2 board support ([8b81a39](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b81a39e28a087e1123271a42c04a7ce3b496a58))
+ - enable BL31 stage ([e73c3c3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e73c3c3a6cbc1e81de4c9d73a5d713e6b37ae3b2))
+
+ - **QEMU**
+
+ - allow ARM_ARCH_MAJOR/MINOR override ([e769f83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e769f830d3116f49ed82769d9d731c4dca8f6188))
+ - enable FEAT_ECV when present ([1b694c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1b694c77c497cb8272c97417ef1fa4f5f9c869c1))
+ - enable transfer list to BL31/32 ([305825b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/305825b490a77e5b0ee816ea29c53bc6444a1d63))
+ - load and run RMM image ([8ffe0b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8ffe0b2edea6b00c9fe7d9ecaeca43c734d3764d))
+ - setup Granule Protection Table ([6cd113f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6cd113fe06fdaa67a8457391eb6bcffd295f87fd))
+ - setup memory map for RME ([cd75693](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cd75693f5ed303c1366fdff9b392d766848b6b67))
+ - support TRP for RME ([ebe82a3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ebe82a392f06aa0adddf9cc5caa7af8f561b2fb4))
+ - update mapping types for RME ([a5ab1ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5ab1ef7febb2dc931cd8f7fcd76caac04d628cd))
+ - update to manifest v0.3 ([762a1c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/762a1c44b985b71495a90bc3484b576d28c8511a))
+ - use mock attestation functions for RME ([c69e95e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c69e95eed0491b481971b48f5df855402ed5392a))
+
+ - **SBSA**
+
+ - handle CPU information ([42925c1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42925c15bee09162c6dfc8c2204843ffac6201c1))
+ - handle memory information ([8b7dd83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8b7dd8397dd017b61ecda8447e8956a1d9d6d5d3))
+ - mpidr needs to be present ([4fc54c9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4fc54c99d08926c2d42173902c8aaf3862722c84))
+
+ - **Raspberry Pi**
+
+ - add Raspberry Pi 5 support ([f834b64](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f834b64f889c1c4e03e590d44a6a52e3ac79cf42))
+
+ - **Renesas**
+
+ - **R-Car**
+
+ - **R-Car 3**
+
+ - add cache operations to boot process ([7e06b06](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7e06b06753b12d567b6f48b6e60d6d0a56cf72e5))
+ - change CAM setting to improve bus latency of R-Car Gen3 ([e366f8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e366f8cf3349189daafb7ac2ab74d98931757a60))
+ - change MMU configurations ([5e8c2d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e8c2d8e23ca0760bca7e5b692ee95dd2871ec89))
+ - enable the stack protection ([cfa466a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cfa466ab733ff021771b94b4a98d22bfdd246139))
+ - update IPL and Secure Monitor Rev.4.0.0 ([516a98e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/516a98ef277626aa1858d9a4018d13ab2aeb39e7))
+
+ - **ST**
+
+ - add a function to clear the FWU trial state counter ([6e99fee](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6e99fee43efa256bdac3b38864206c94bd9ae3c8))
+ - add logic to boot the platform from an alternate bank ([6166051](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6166051426638087b5433eff1739d26478313dff))
+ - do not directly call BSEC functions in common code ([3007c72](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3007c72844c72e0911721e499dbab37b3eca1cdc))
+ - get the state of the active bank directly ([588b01b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/588b01b5e4726cd4a6d235e9f566a546ef17f631))
+ - use stm32_get_otp_value_from_idx() in BL31 ([189db94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/189db9486ddd949f279faa970bfc1dd9cc0e3623))
+
+ - **STM32MP1**
+
+ - only fuse monotonic counter on closed devices ([d6bb94f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6bb94f3a14ddbcf44c667134ed302eff054954c))
+
+ - **STM32MP2**
+
+ - add BSEC and OTP support ([197ac78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/197ac780d73c3421c4643e0bc02d112ceffd248f))
+ - add ddr-fw parameter for fiptool ([e494afc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e494afc05f8562455e09b4f131f2699990a744f8))
+ - add plat_my_core_pos ([d1c85da](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d1c85da8ef23a99387823272b03399a07e3a00da))
+ - add STM32MP_USB_PROGRAMMER compilation ([2e905c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2e905c0682b4e6d2cfdbd42e41f6097b16967ff5))
+ - put back core 1 in wfi after debugger's halt ([2331a34](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2331a34f783b29a9a1fe86f5142d0a359cacb259))
+ - use early traces ([47ea303](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47ea303389f6d0ac81617366973ece9d93dc49c9))
+
+ - **Xilinx**
+
+ - add handler for power down req sgi irq ([ade92a6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ade92a64e4d2fbb5f246e6ad891465d10e0d9b26))
+ - add new state to identify cpu power down ([5949701](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5949701600c7f3c3a6589d0efd743615156c34b6))
+ - add wrapper to handle cpu power down req ([3dd118c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3dd118cf9d60e1eab97af505eb63a2cdc044d747))
+ - power down all cores on receiving cpu pwrdwn req ([c3280df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c3280df1bb95ed09b5d5f91f8977bbe99c6a923b))
+ - request cpu power down from reset ([88ee081](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88ee0816a7429689890659f69b895ac84e48f141))
+ - send SGI to mailbox driver ([9a7f892](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9a7f892e29ea81c67f6f6b1342a367234e125b63))
+
+ - **Versal**
+
+ - enable errata management feature ([d766f99](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d766f994d2bd00c538f66e95686fc47b45ccbdb9))
+ - extend platform address space sizes ([663f024](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/663f024f207bddb7b80167e661c094d77955e292))
+
+ - **Versal NET**
+
+ - add bufferless IPI Support ([511e4a4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/511e4a48ccd5e74af338041be238f5df12fffe3e))
+
+ - **ZynqMP**
+
+ - remove unused pm_get_proc_by_node() ([b03ba48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b03ba4801d39da1d5acc7a58d9c7736e57efc099))
+
+- **Bootloader Images**
+
+ - **BL32**
+
+ - create an sp_min_setup function ([a1255c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1255c758593f9f6fb85b70165fad21de7491e1e))
+
+- **Services**
+
+ - **FF-A**
+
+ - update FF-A version to v1.2 ([e830e4c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e830e4cdee3d2238314326ef8c259b35d1c4f167))
+
+ - **RME**
+
+ - build TF-A with ENABLE_RME for Armv9.2 ([7d5fc98](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7d5fc98f5483efb942f7cbe4c04bf546a9a8598c))
+ - pass console info via RMM-EL3 ifc ([3290447](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/32904472cc55a4bc9d8181a389ce3419033e0101))
+
+ - **SPM**
+
+ - **EL3 SPMC**
+
+ - add support for FFA_CONSOLE_LOG ([638a6f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/638a6f8e04c543649369374492524f2952f8d6b6))
+ - add support for FFA_MEM_PERM_GET and SET ABIs ([1f6b2b2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f6b2b26535d5254d998239f232d997972d0475b))
+ - add support to handle power mgmt calls for s-el0 sp ([5917379](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59173793f47e27a66c871a0e8237e0f0d462080d))
+ - add support to map S-EL0 SP device regions ([727ab1c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/727ab1c4ab1e5ce1559fa6efec510114ce51fdf8))
+ - add support to map S-EL0 SP memory regions ([83c3da7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83c3da7711a246e04f4d0a64593fc0ab46f08bad))
+ - add support to setup S-EL0 context ([48db2b0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/48db2b0120d1726208ff38a0edf6962f55a988bf))
+ - synchronize access to the s-el0 sp context ([5ed8e25](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5ed8e255096bd34d12bc6621e48cf9139bf414b2))
+
+ - **SPMD**
+
+ - add FFA_MSG_SEND_DIR_REQ2 ([cc6047b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc6047b3de52e412988f321723f67077a409e27d))
+ - add FFA_MSG_SEND_DIR_RESP2 ([0651b7b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0651b7beb7e08a01c6e28be61026b053d53308fa))
+ - initialize SCR_EL3.EEL2 bit at RESET ([8815cda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8815cdaf57806901cfd388b8ee8c7979a8a2fe15))
+ - pass SMCCCv1.3 SVE hint to lower EL ([c925867](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c925867ec1be039abb72a7d65bff1b6a85b3d67a))
+
+ - **DRTM**
+
+ - add ACPI table region size to the DLME header ([5dde96b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5dde96b02490829d023b37931737c2ba2a6ed431))
+ - add additional return codes ([89f5c75](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/89f5c753af8e5b8091543e8b1cae4d37e345ed7f))
+ - for TPM features fw hash algorithm should be 16-bits ([c86cfa3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c86cfa35975542d25d2192b81908074195aafe96))
+ - update DRTM version to 1.0 ([9c36b90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9c36b900f904642f41e201024df584c0eaef9fc5))
+ - update references to DRTM beta0 ([b94d590](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b94d59099f0addb32389952dc6ecf35136a23859))
+ - update return code if secondary PE is not off ([bc9064a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc9064ae5c983aaca56102c2c0d3513ed022fd46))
+
+ - **ChromeOS**
+
+ - add ChromeOS widevine SMC handler ([b22e689](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b22e6898e1493eb00d0f0de6d48655d744264cb6))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - add support for Poseidon V CPU ([b77f55d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b77f55d6c7e51025d6c7ada1b4aa9506a046cf0f))
+ - support to update External LLC presence in Neoverse N3 ([6fbc98b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6fbc98b15d92d881c4fbb74fd1344f0ef3f128ad))
+ - support to update External LLC presence in Neoverse V2 ([6aa5d1b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6aa5d1b3ab7b29c85ffe05942f2991da869e7fed))
+
+ - **EL3 Runtime**
+
+ - introduce UNDEF injection to lower EL ([3c789bf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3c789bfccca548ebcbdafbc7ecb07461d9368bea))
+
+ - **FCONF**
+
+ - support signing-key in root cert node ([04ac0b3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04ac0b3c2711a4cb2f35983e91ff0ee842b52bbd))
+
+ - **OP-TEE**
+
+ - enable transfer list in opteed ([0e8def9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0e8def996e73673d3e2c3d755a84e2b759ab3052))
+
+ - **PSCI**
+
+ - add psci_do_manage_extensions API ([160e843](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/160e8434baa48cc19d69913b00d2a643c788caec))
+
+ - **GPT**
+
+ - validate CRC of GPT partition entries ([7a9e9f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7a9e9f6e96a93617abd33ef48734b65ad792ec13))
+
+ - **SMCCC**
+
+ - add vendor specific el3 id ([be5b1e2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/be5b1e22346c6d8ce4b0c56604c99f7a9d3676cc))
+ - add vendor-specific el3 service ([de6b79d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/de6b79d8b5e15262b328051095e15ad4c67518eb))
+ - add version FID for PMF ([42cbefc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/42cbefc72721a9cbf68a70d81cbcb141a2d085f1))
+
+ - **C Standard Library**
+
+ - add printf support for space padding ([0926d2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0926d2df7a5606c2b7c341d51f04a396084c39f2))
+
+ - **Locks**
+
+ - add bitlock ([222f885](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/222f885df38c3abd34ee239a721654155609631b))
+
+ - **DICE Protection Environment (Experimental)**
+
+ - add cert_id argument to dpe_derive_context() ([6a415bd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a415bd1e71ac944c0ac67507b01f251e63361c3))
+ - add client API for DICE Protection Environment ([b03fe8c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b03fe8c025f1c8025e70e7289339ecbc6cf83aae))
+ - add DPE driver to measured boot ([0ae9c63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ae9c631eaa32a30df3ff10cb4f0abafccb6c409))
+ - add QCBOR library as a dependency of DPE ([c19977b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c19977be0c3654e12accd51d4aef7059411106a6))
+ - add typedefs from the Open DICE repo ([584052c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/584052c7f80b406666b9597447eeccef4d6deca4))
+
+ - **Context Management**
+
+ - report context memory usage ([bfef8b9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bfef8b908e3a3cc29656c1d30a6b53490c79539b))
+ - add documentation for context management library ([4efd219](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4efd2193621ab7b933f4edfa28888379f3e03cbd))
+
+ - **Firmware Handoff**
+
+ - add additional TE tags ([a312bfb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a312bfb34487774a0e3244266ee45f63af86e2e8))
+ - add support for RESET_TO_BL2 ([f019c80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f019c8013e9c5efeb85eec7792fe901543a5832c))
+ - add TE's for BL1 handoff interface ([0646c9b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0646c9b293a2d8cdfd4626d15395385b5c1c2a6c))
+ - add TL source files to BL1 ([469b1d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/469b1d8412a748819f8c1bf51f695f2cb9f20489))
+ - enhance transfer list library ([40fd755](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/40fd755bad9411d1e9e55984107186dde4137635))
+
+- **Drivers**
+
+ - **Authentication**
+
+ - add explicit entries for key OIDs ([2b53106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2b53106a0e91e0865bf855935de04b24ef1cfa02))
+
+ - **mbedTLS**
+
+ - update config for 3.6.0 ([55aed7d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/55aed7d798f3d48d6aa08d58eb46c4cda318bcfb))
+
+ - **Console**
+
+ - introduce EARLY_CONSOLE ([ae770fe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae770fedf459d5643125d29f48659e3e936ebd2d))
+
+ - **FWU**
+
+ - modify the check for getting the FWU bank's state ([56724d0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56724d09c2c55ee2b8486b7c706f5fb9d980df88))
+ - update the URL links for the FWU specification ([e106a78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e106a78ef00df4c70a1594a89520af07b939cd92))
+
+ - **SCMI**
+
+ - add scmi sensor support ([e63819f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e63819f2bc307e7a42d43151242009f91ceeb06b))
+
+ - **Arm**
+
+ - **SMMU**
+
+ - fix to perform INV_ALL before enabling GPC ([70d849c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70d849c14de99e7320cc381b441af8bfe2a38375))
+ - separate out smmuv3_security_init from smmuv3_init ([a23710b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a23710b4b943a15a418a5d41236b2b57bd071de6))
+
+ - **MHU**
+
+ - add MHUv3 doorbell driver ([bc17476](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc174764f0daa82128bf60163653fc20db9a7e87))
+ - add MHUv3 wrapper APIs for RSS comm driver ([4b4f850](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4b4f8505e7c58ba80a00c47a11f5feaf6d6f44f2))
+ - use compile flag to choose mhu version ([996b3af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/996b3af84cc6aeca90bc0dd3559abffd8bdc0ed7))
+
+ - **RSE**
+
+ - add defines for 'type' range and use them in psa_call() ([002b106](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/002b10604ba0b90ac6e85d445ce2184cab52e39b))
+ - adjust parameter packing to match TF-M changes ([5abcc83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5abcc83991770a2fdbcb57dfc01000c6354da915))
+
+ - **NXP**
+
+ - add Linflex driver ([306946b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/306946b01490cfe0675300412cf738840bd099ef))
+
+ - **ST**
+
+ - **BSEC**
+
+ - add driver for the new IP version BSEC3 ([ae6542f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae6542f6c7ac9224843448424d3a539733bd651b))
+ - use early traces ([cf237f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cf237f8d55255da1aad4f8dccb3110bab6060eba))
+
+ - **Clock**
+
+ - add function to control MCU subsystem ([77b4ca0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/77b4ca0b2fd2c35e3bcb516078e1d9e3573172b3))
+
+ - **SDMMC2**
+
+ - set FIFO size to 1024 on STM32MP25 ([d5b4d5d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d5b4d5d2e62e57acdcb2dbbcd4fe208bde92dc4c))
+
+- **Miscellaneous**
+
+ - **AArch64**
+
+ - add functions for TLBI RPALOS ([8754cc5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8754cc5d1c1b33d645b321f465bcfe61bc3915d6))
+
+ - **DT Bindings**
+
+ - introduce CCA CoT, rename TBBR ([c4b35ce](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c4b35cebffb0d034aa7bdba7cfdb65ba93939e35))
+
+ - **FDTs**
+
+ - **STM32MP2**
+
+ - add board ID OTP in STM32MP257F-EV1 ([88528f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/88528f55771fdc0a94b2ddd7f49f495a83044a24))
+ - add OTP nodes in STM32MP251 SoC DT file ([c238a46](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c238a46a76660cbfa9ed40da4b1d0e5d477c3dd7))
+
+ - **Security**
+
+ - add support for SLS mitigation ([538516f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/538516f5d3db6e2c30dfa9f0b82859389f529e78))
+
+- **Documentation**
+
+ - update maintainer list for neoverse_rd ([2d7902d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d7902d9bf0bafceee9f571225862c476de0cdce))
+
+- **Build System**
+
+ - check that .text section starts at page boundary ([3d6edc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3d6edc325c52082ab63ffd003c55a4ed875a52c5))
+ - redirect stdin to nul during toolchain detection ([b9014f8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b9014f858d1fd963a466228ec15572b0892a8490))
+
+- **Tools**
+
+ - **Memory Mapping Tool**
+
+ - add RELA section display ([a6462e0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a6462e05cf1cd55da44002cdede04053a928cf0a))
+
+### Resolved Issues
+
+- **Architecture**
+
+ - **Memory Tagging Extension2**
+
+ - remove CTX_INCLUDE_MTE_REGS usage ([30788a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/30788a8455779b70aebd38d53afc8aa19d776c6c))
+ - use ATA bit with FEAT_MTE2 ([ef0d0e5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef0d0e5478a3f19cbe70a378b9b184036db38fe2))
+
+ - **Performance Monitors Extension (FEAT_PMUv3)**
+
+ - fix breakage on ARMv7 CPUs with SP_min as BL32 ([e6f8fc7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e6f8fc7437f6b9483ea0463315809d7ff6d5c0ec))
+
+ - **Statistical profiling Extension (FEAT_SPE)**
+
+ - invoke spe_disable during power domain off/suspend ([777f1f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/777f1f6897b57fe98c70d17c0d318aab3b86e119))
+
+- **Platforms**
+
+ - **Arm**
+
+ - move console flush/switch in common function ([6bdc856](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6bdc856bc9135db420196683501b4f201b30ae3a))
+ - only expose `arm_bl2_dyn_cfg_init` to BL2 ([3b48ca1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b48ca17f350d8b0999e89e8d9215993701e16a0))
+
+ - **FVP**
+
+ - added ranges for linux ([b7491c7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b7491c77d7ad2991b8c7c01f0311ebb3b0eca397))
+ - don't check MPIDRs with the power controller in BL1 ([6d8546f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6d8546f9fc49a03a817b15b20a9d62fadda74b9c))
+ - permit enabling SME for SPD=spmd ([0b0fd0b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0b0fd0b47616b706e2f07c6da548cdc913fecd17))
+
+ - **FPGA**
+
+ - halve number of PEs per core ([70b9204](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/70b9204e6f98f1ec4f0529e8c1c88e8ece490d22))
+
+ - **Neoverse-RD**
+
+ - **SGI**
+
+ - align to misra rule for braces ([cacee06](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cacee0605684a75bbe8783c74fddba97b9abcffa))
+ - apply workarounds for N2 CPU erratum ([7934b68](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7934b68af6b446783823a114f25c3be06244c0e4))
+ - increase BL31 carveout size ([0737bd3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0737bd33faba5c9e6a0e98969e015430e2782332))
+ - reduce cper buffer carveout size ([f10d3e4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f10d3e4953741eb3be1f9e4c09e7420554a0f050))
+ - update spi_id max for sgi multichip platforms ([89d8577](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/89d857780c50bddf94db26f158c008b4cc846edf))
+
+ - **RD-N1-Edge**
+
+ - update RD-N1-Edge's changelog title ([d239ede](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d239edea5644657ac72458cc13e3ce6bb5754ff8))
+
+ - **RD-N2**
+
+ - populate TOS_CONFIG only when SPMC_AT_EL3 is enabled ([10dcffe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10dcffedb36a658cf8a3389fbdeb499d4e7e4446))
+
+ - **TC**
+
+ - correct interrupts ([d2e44e7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2e44e7d71863e3b302b5e72c8262bb0f3964fe6))
+ - do not enable MPMM and Aux AMU counters always ([fc42f84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fc42f84560d33c53b248e14913bbd6a69a8d310a))
+ - do not use r0 for HW_CONFIG ([a5a966b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a5a966b12d9fe51a337db3204e7463ad95ba99c6))
+ - enable FEAT_MTE2 ([154eb0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/154eb0a22fa0a88d1f46e3674e3979626a83e063))
+ - guard PSA crypto headers under TF-M test-suite define ([d2ce6aa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2ce6aa066ce1539908726de0d94a59c16634c4a))
+ - increase BL2 maximum size limit ([19258a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/19258a5839cae9a81fb7256fbea34ff118220161))
+ - increase stack size when TRUSTED_BOARD_BOOT=0 ([44ddee6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/44ddee6f0a993ed5b3409e6626c0c70b7ed7d7a2))
+ - missing device regions in spmc manifest ([5e47112](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5e4711208db622ff6150e69c87962b506742a544))
+ - remove timer interrupt from G1S ([9bf31a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9bf31a59d187f6537066f05677972d9767e96c82))
+
+ - **Intel**
+
+ - add HPS remapper to remap base address for SDM ([b727664](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b727664e0dcf62be39552521c451ecde02091917))
+ - bl31 overwrite OCRAM configuration ([cfbac59](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cfbac59590056e6b639aed56a1da480cd46f6f3e))
+ - fix hardcoded mpu frequency ticks ([150d2be](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/150d2be0d2d440011c91c9bf8013a1ab602b464c))
+ - read QSPI bank buffer data in bytes ([2f17ac0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2f17ac01adf28edb90a5ec8f446be1be76971b5c))
+ - revert back to use L4 clock ([d0e400b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d0e400b3c626be647b9a20bc4f4869e20cc15dde))
+ - revert sys counter to 400MHz ([460692a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/460692afb5b934720b69c410e3b02c540a3b1ddf))
+ - temporarily workaround for Zephyr SMP ([68820f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68820f642191cef67df38516ef1c2ed1411c579f))
+ - update DDR range checking for Agilex5 ([f4aaa9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f4aaa9fd6e6b4edd03976680b94e1c24aa582a68))
+ - update fcs crypto init code to check for mode ([b0f4478](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0f447897d3e2ddd72b291cb450165f4d220663e))
+ - update fcs functions to check ddr range ([e8a3454](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e8a3454cb74a9b55c0cb678d47a8553ece660439))
+ - update from INFO to VERBOSE when print debug message ([56c8d02](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/56c8d022b00ba212f3e21dcfab20c14f3a44eec4))
+ - update HPS bridges for Agilex5 SoC FPGA ([2973054](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2973054d9b4ba4fbcad7e04303ce8e0838b2f2b3))
+ - update individual return result for hps and fpga bridges ([82752c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/82752c412362607549068d1c10cf7688f309d249))
+ - update nand driver to match GHRD design ([a773f41](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a773f4121b3064fba24631e980c6226f23378e06))
+ - update stream id to non-secure for SDM ([8fbd307](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8fbd3073cacfc7a23efdfda4eecfaf6607515306))
+ - update system counter back to 400MHz ([a72f86a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a72f86ac4208e2aae5da83229cdd9ac97f651e36))
+
+ - **NXP**
+
+ - **i.MX**
+
+ - **i.MX 8M**
+
+ - align 3200 MTps rate with U-Boot ([060fe63](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/060fe63337097c6cadea76ef5d2d383f0d90ef01))
+ - fix CSU_SA_REG to work with all sa registers ([c13016b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c13016bac6a6960acbbfb3e0176e1894a7e9fa3a))
+ - handle 3734 in addition to 3733 and 3732 MTps rates ([cb60a87](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb60a876efc156c87afcd5ec53b9cf356f30211d))
+
+ - **i.MX 8M Plus**
+
+ - uncondtionally enable only the USB power domain ([ae6ce19](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae6ce196df5b932f38c543cd8c6d8d86ee600009))
+
+ - **i.MX 8ULP**
+
+ - add sw workaround for csi/hotplug test hang ([e1d5c3c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e1d5c3c8f435424394367e2ff19240b1b8a3073c))
+ - fix suspend/resume issue when DBD owner is s400 only ([68f132b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68f132b88bb24277ee34d5c3c94d16c26d7d4545))
+ - increase the mmap region num ([047d7d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/047d7d1ba2fc84d8377156f7f45d2d69c3cb5f84))
+
+ - **QEMU**
+
+ - disable FEAT_SB ([59bdb42](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59bdb426d300a6350334523a8dbc3fa6ae9f3bfc))
+ - increase max FIP size ([f465ac2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f465ac221001f82bed907be356917675645d92eb))
+
+ - **Raspberry Pi**
+
+ - consider MT when calculating core index from MPIDR ([6744d07](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6744d07d9475adb49352fa57aa72fce17a95d757))
+
+ - **Renesas**
+
+ - **R-Car**
+
+ - fix implicit rule invocations in tools ([e068a7c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e068a7ca860f35a171f608d55fb8a2a00ebd7561))
+
+ - **R-Car 3**
+
+ - change RAM protection configurations ([e9afde1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e9afde1a2e311df0197a8e9102ef535382aef228))
+ - fix load address range check ([4f7e0fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4f7e0fa38fdb6a25b07afafff492985bcc4e63a0))
+
+ - **Rockchip**
+
+ - add support for building with LTO enabled ([e5e9ccd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e5e9ccdb0c070d3066e7d778e5e2b563acd7ba98))
+ - fix documentation in how build bl31 in AARCH64 ([6611e81](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6611e81e14ed4aa16844e3865fd8a9f6fa99a074))
+
+ - **RK3328**
+
+ - apply ERRATA_A53_1530924 erratum ([dd2c888](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dd2c888606dcdd638354c6345e08d4415d9d09fd))
+
+ - **ST**
+
+ - **STM32MP2**
+
+ - add missing include ([cb0d6b5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cb0d6b5b5f7530335eac3c387bbb82d86608b0ea))
+ - correct early/crash console init ([4da462d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4da462dcdc2e435c8b732f3ceff4c94ca28b4c43))
+
+ - **Texas Instruments**
+
+ - do not stop non-secure timer on world switch ([d2e1f6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d2e1f6a8811e52505556f7b91156499d82488751))
+
+ - **K3**
+
+ - increment while reading trail bytes ([0bdaf5c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0bdaf5c804f852fe21f6172e436524157c9f6919))
+
+ - **Xilinx**
+
+ - add console_flush() before shutdown ([7ec53af](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ec53afaade308b35f546480990dbc9304e06e7d))
+ - add FIT image check in DT console ([e2d9dfe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e2d9dfe2bffe4fde28f2714058c8c882ea90102a))
+ - add FIT image check in prepare_dtb ([046e130](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/046e1304721e8bbf3d304dac22aa290bcbb0d10c))
+ - check proc variable before use ([652c1ab](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/652c1ab1526877d3505218f87ea96e6a9b2ccc11))
+ - deprecate SiP service count query ([6a80c20](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a80c20eff74054c28273b42f3fe8e1a8fc5add4))
+ - fix sending sgi to linux ([427e46d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/427e46ddea1e528d4c57b1d8215482055bd79c3e))
+ - follow MISRA-C standards for condition check ([655e62a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/655e62aa5bede7ace8f8c6df571707aca9d6e14f))
+ - rename macros to align with ARM ([7995319](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/79953190bc856ac3f47281029a80e5129bb4437d))
+ - update correct return types ([8eb6a1d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8eb6a1da1229b8f0bff33293cbb86ce20d09259d))
+
+ - **Versal**
+
+ - initialize cntfrq_el0 register ([f000744](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f000744e0f501c89fb2240b47e91c261e3082249))
+
+ - **Versal NET**
+
+ - setup counter frequency ([07625d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/07625d9dd42d81c0e15f101fc0b6efa1c784b6f4))
+ - use arm common GIC handlers ([b225926](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b2259261815961042d2a994401929bc76a0d3ee9))
+
+ - **ZynqMP**
+
+ - resolve null pointer dereferencing ([20fa9fc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/20fa9fc82334c67834eb22e20a3f4a07bcbe069d))
+
+ - **Nuvoton**
+
+ - gfx frame buffer memory corruption during secondary boot ([ae2b4a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae2b4a5494f9b4985fc2434e543ab0921e3b5a34))
+ - prevent changing clock frequency ([fe8cc55](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fe8cc55a0cb5e47a0c0e28b147ee3e8dfdae07b2))
+
+- **Bootloader Images**
+
+ - **BL1**
+
+ - add missing `__RW_{START,END}__` symbols ([d701b48](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d701b48eef4bb4b4b13ce5ef4091a37047e49a0b))
+ - add missing spinlock dependency ([e40b563](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e40b563e87fd4ff58474a289909a1827c8d2bca7))
+
+ - **BL2**
+
+ - make BL2 SRAM footprint flexible ([e0e03a8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e0e03a8d8b7eac45606812d1f2a9685b51e44515))
+
+- **Services**
+
+ - **FF-A**
+
+ - add NS memory node to fvp_spmc_optee_sp manifest ([92bba3e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/92bba3e711a21f2d31842bee64a1bd87e4b65414))
+
+ - **RME**
+
+ - **RMMD**
+
+ - avoid TRP when external RMM is defined ([57bc3c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57bc3c40560285e6029742b7360f8a0d0ac2346c))
+ - fix bug, raised by coverity, when zeroing manifest struct ([83a4e8e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83a4e8e0c69c64219e4d9de6c7f51fb10e3adc5a))
+
+ - **SPM**
+
+ - add device-regions used in tf-a-tests ([45716e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/45716e377ecb30c17aa3b375ce1e232d15492b9c))
+ - not defining load-address in SP config ([04e7f80](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04e7f80823e8a083138dd25963a5509bacd93257))
+ - reduce verbosity on passing tf-a-tests ([29872eb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/29872eb330201334fcb8e418b7dc7ae8ff0dc192))
+ - silence warning in sp_mk_generator ([6a3225e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a3225e2277df18e5c3aceb6173579cccefece51))
+
+ - **EL3 SPMC**
+
+ - add datastore linker script markers ([ba33528](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ba33528a00bb83f5562918131cb37574fc287193))
+ - fix dangling pointer in FFA_CONSOLE_LOG ([83129bc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/83129bcd8e75f1ffbfc9a3bae3d60749b1d22fe3))
+
+ - **SPMD**
+
+ - register group0 handler only if supported ([fca5f0e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fca5f0ebe5c2b5cf1c9d5096db6001a60ff7e089))
+ - skip NS EL1 context save & restore operations ([2d960a1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/2d960a11601be6e7f24c38d84b2a4fdbb52efb9b))
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - workaround for Cortex-A520 erratum 2630792 ([f03bfc3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f03bfc304599540d859c4a07ac85d1bd9ae2c4f0))
+ - workaround for Cortex-A520 erratum 2858100 ([34db353](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/34db3531ba085f111274b3b8e18476c4a392c245))
+ - workaround for Cortex-A710 erratum 2778471 ([c9508d6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c9508d6a1062ec3de4baaa3bd79ceed13eb972ad))
+ - workaround for Cortex-A715 erratum 2331818 ([53b3cd2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/53b3cd2532dbdb794ddfedcc8a3985d2404eb6f7))
+ - workaround for Cortex-A715 erratum 2344187 ([33c665a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/33c665ae955fe5f5ae255f56ef6cdf073a9f601f))
+ - workaround for Cortex-A715 erratum 2413290 ([15a0461](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/15a04615bb6834d93ab0077b89726dc17e3ba8b0))
+ - workaround for Cortex-A715 erratum 2420947 ([1f73247](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/1f732471320cee7b4f355ecff7dcfab7018e48ae))
+ - workaround for Cortex-A715 erratum 2429384 ([262dc9f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/262dc9f76086970dab3dc43815890bed0ea29c79))
+ - workaround for Cortex-A715 erratum 2561034 ([6a6b282](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a6b282378340dc61cf088ff5a06770cf68f44d8))
+ - workaround for Cortex-A715 erratum 2728106 ([10134e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/10134e3556ca61e670017e681eb637889b1bd4f8))
+ - workaround for Cortex-A720 erratum 2926083 ([152f4cf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/152f4cfa16bc3d2786f598390450af38f4b2d0be))
+ - workaround for Cortex-A720 erratum 2940794 ([7385213](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7385213e602465d27530015a9b28ebc36a77b1c1))
+ - workaround for Cortex-A78C erratum 2683027 ([68cac6a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/68cac6a0f273dbe4f44563b467c996fafef07016))
+ - workaround for Cortex-A78C erratum 2743232 ([81d4094](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81d4094d637871ff34ddd7c2e2b3e842915f30f5))
+ - workaround for Cortex-X2 erratum 2778471 ([b01a93d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b01a93d7789a794ef0635e0a7b0e7e53cc8519e5))
+ - workaround for Cortex-X3 erratum 2266875 ([a65c5ba](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a65c5ba351178e6119299fa935a3576453cf900b))
+ - workaround for Cortex-X3 erratum 2302506 ([3f9df2c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3f9df2c6ad053172c5dab74cd12d82a5b2c93c34))
+ - workaround for Cortex-X3 erratum 2372204 ([7f69a40](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f69a40697c3cc64e3fc553f6b50c72b97238dc9))
+ - workaround for Cortex X3 erratum 2641945 ([c1aa3fa](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c1aa3fa5555250dfbcae99fb6944ad24c4ee6a0b))
+ - workaround for Cortex X3 erratum 2743088 ([f43e9f5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f43e9f57dc37a806bcd5e25a46b9f9bb1f365a64))
+ - workaround for Cortex-X3 erratum 2779509 ([355ce0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/355ce0a43abc1559b072b9cd9905f5194a6f0b86))
+ - workaround for Cortex-X4 erratum 2701112 ([cc41b56](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/cc41b56f41af14b00ce9f5c802e2f883786cef38))
+ - workaround for Cortex-X4 erratum 2740089 ([c833ca6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c833ca66a6fecbc54e038164e466be677559ec4e))
+ - workaround for Cortex-X4 erratum 2763018 ([4731211](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/47312115dea140dd7ba26cf0512856a41f3e3067))
+ - workaround for Neoverse V1 erratum 2348377 ([71ed917](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/71ed91733140c82a392161c81869fcadb445c01a))
+ - workaround for Neoverse V2 erratum 2618597 ([c0f8ce5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0f8ce5379a77e61e89d91e225784801e5bbd3e0))
+ - workaround for Neoverse V2 erratum 2662553 ([912c409](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/912c4090fff207b445dde4bff72cc9b6e057e8b7))
+ - workaround for Neoverse V2 erratum 3099206 ([8815cda](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8815cdaf57806901cfd388b8ee8c7979a8a2fe15))
+ - add Cortex-A520 definitions ([ae19093](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae19093f2aa6dd95cc7819accb0d05c0ebe4eeb3))
+ - workaround for Cortex-A715 erratum 2413290 re-factored with ENABLE_SPE_FOR_NS=1 ([bd2f7d3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd2f7d325826f75acd729d4ee2719fd6130a7c5e))
+ - fix a defect in Cortex-A715 erratum 2561034 ([57ab6d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/57ab6d897656f71d229268d80e41b26e62179400))
+ - add erratum 2701951 to Cortex-X3's list ([106c428](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/106c4283a564e4f37976ebc7dd8bc7d35f6592e4))
+ - update status of Cortex-X3 erratum 2615812 ([f589a2a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f589a2a5f1b032ff3a09a419e49db0b97ccd8595))
+ - fix incorrect AMU trap settings for N2 CPU ([54b86d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/54b86d47eb05f09330df57519b7d04b9968890e5))
+ - correct variant name for default Poseidon CPU ([61a2968](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/61a29682c66d0437806f81fb8ab0e3ff321dfe04))
+ - check for SCU before accessing DSU ([5b5562b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5b5562b2e5855f949f1fc0579d7aff15e6b274ef))
+
+ - **EL3 Runtime**
+
+ - **Context Management**
+
+ - add more feature registers to EL1 context mgmt ([d6c76e6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6c76e6c65429326e7572e10f521dd9108a3a1e3))
+ - add more system registers to EL1 context mgmt ([ed9bb82](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ed9bb824e4a3815e60acaa69ed66796279f4afbf))
+ - hide `cm_init_context_by_index` from BL1 ([a6b3643](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a6b3643c2a1a95146e93c8b6f07c2e491a1230d6))
+ - remove ENABLE_FEAT_MTE usage ([a796d5a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a796d5aa11b25622841cd2283630ff9348eed699))
+ - save guarded control stack registers ([6aae3ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6aae3acfd0d48e49e2367e6cd883dda7dca974c8))
+ - update gic el2 sysregs save/restore mechanism ([937d6fd](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/937d6fdb70cd24602fd2638a5dbd5c46d32559c1))
+ - couple el2 registers with dependent feature flags ([d6af234](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d6af23443179f6d2239c7f5f190f0d8828bd68cf))
+ - move EL1 save/restore routines into C ([59f8882](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/59f8882b44845ab865e354eeda8ce653f5d5fcf3))
+
+ - **FCONF**
+
+ - boot fails using ARM_ARCH_MINOR=8 ([0c86a84](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0c86a846d9149ee5af7e1ee4bb185c532ed9d0f8))
+
+ - **OP-TEE**
+
+ - set interrupt handler before kernel boot ([0ec69a5](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0ec69a5bfbfcdf4566db8e96adaf29ad847d3d58))
+
+ - **PSCI**
+
+ - fix parent_idx in psci_validate_state_coordination ([412d92f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/412d92fdfd28d2f850a48e5f0aee95faa894a556))
+ - mask the Last in Level nibble in StateId ([0a9c244](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0a9c244b05ef2d2d4b946ba81bb9b9584b479b48))
+
+ - **GPT**
+
+ - declare gpt_tlbi_by_pa_ll() ([832e4ed](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/832e4ed520d5ed7e64249fe98c1ffb4550db5eca))
+ - unify logging messages ([b99926e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b99926ef7b287738c4b4a87ee7ab4eaed1e4038f))
+ - use DC CIGDPAPA when MTE2 is implemented ([62d6465](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62d64652134ca1d3ea68da65ea9e4ae136f6c44e))
+
+ - **C Standard Library**
+
+ - add memcpy_s source file to libc_asm mk ([99db13b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/99db13bfaa5b11345730937c2e0e56cb670c01a5))
+ - memset inclusion to libc makefiles ([84eb3ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/84eb3ef6c9f596e968b4f9b83a3a01deda2a8a9d))
+
+ - **PSA**
+
+ - fix static check failure ([bc0ff02](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bc0ff02cbb046388eff1a95efd0043757d6ac317))
+
+ - **Context Management**
+
+ - align the memory address of EL2 context registers ([8c56a78](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8c56a78894ddc69167bc093fe19f173feced720c))
+
+ - **Firmware Handoff**
+
+ - correct representation of tag_id ([d594ace](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/d594ace68d4fa62cf2f1d5d13503b737b85924e5))
+
+ - **Exception Handling Framework (EHF)**
+
+ - restrict secure world FIQ routing model to SPM_MM ([7671008](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7671008fcfc826dbc3166ff1bdbb9cd7fbc7f68b))
+
+ - **SMCCC**
+
+ - correctly find pmf version ([62865b4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/62865b4ee455806e37a9c5bd52255b8c09cf1a1a))
+
+- **Drivers**
+
+ - **Measured Boot**
+
+ - add missing image identifier string ([a8a09e3](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a8a09e3141354b159e7699d7c9c325bdd817b1f5))
+
+ - **SCMI**
+
+ - induce a delay in monitoring SCMI channel status ([af1ac2d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/af1ac2d7db47717bc69afd69b56f398aa34b2fb6))
+
+ - **Arm**
+
+ - **GIC**
+
+ - **GICv3**
+
+ - **GIC-600**
+
+ - workaround for Part 1 of GIC600 erratum 2384374 ([24a4a0a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/24a4a0a5ec25e179f2e567a6e13a9b5c87db1b81))
+
+ - **GICv2**
+
+ - fix SGIR_NSATT bitshift ([eef240c](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/eef240cfdedcc59f09dd5cd942448c5dcecc75d6))
+
+ - **MHU**
+
+ - use MHUv2 if PLAT_MHU_VERSION undefined ([c34dd06](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c34dd06a843d71cdba2fa1c3c9067f6f130a0c73))
+ - provide only the usable size of memory ([5cd1084](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5cd10848be4f6ac19daa66803c3d512e3eea4266))
+
+ - **RSE**
+
+ - fix bound check during protocol selection ([f754bd4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f754bd466749a9338561f991bfb85140dd034e03))
+
+ - **Renesas**
+
+ - **R-Car3**
+
+ - add integer overflow check ([ef38fb1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ef38fb1f5a5f2bdb897158e4244a1eddd2396eeb))
+ - add integer overflow check ([93b8952](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/93b8952eefa14141c142070a71fc017736c8910c))
+ - check "rcar_image_number" variable before use ([b469880](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b469880e3b6b26849c3d43d3fe88a755a25249bc))
+ - check for length underflow ([9778b27](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9778b270e29bac3e16f57f9557098c45858c05de))
+ - check loaded NS image area ([ae4860b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/ae4860b0f5c283aeca4def1449f0293ef22ff508))
+
+ - **USB**
+
+ - add missing include ([f84f21f](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f84f21fa8d17662dcdc6b0b8b0caca4a45cd9ccd))
+
+- **Miscellaneous**
+
+ - **TBBR**
+
+ - move rotpk definitions out of arm_def.h ([0f0fd49](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/0f0fd499dedd799e19279f0aa1f4f686085a944a))
+
+ - code coverage optimization fix ([152ad11](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/152ad112d73402523302f3cb252aee0efc145736))
+ - fix MISRA defects ([c42d0d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c42d0d8754ae8818a7e7a63e873ca7699a7f102b))
+ - static checks on spmc dts ([c35299d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c35299d6b4e8b2757e47dc4c5a3b2e0836f89a7d))
+
+- **Documentation**
+
+ - revise the description of REGISTER_CRYPTO_LIB ([5710229](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5710229f9e837f28e4bafee6b51e828f901bf3f1))
+ - typo in the romlib design ([3b57ae2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/3b57ae23e0891e44d5b648575b80cbad4fc10405))
+
+- **Build System**
+
+ - add forgotten BL_LDFLAGS to lto command line ([49ba1df](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49ba1df52204e721f06a6da76ef0f8692ce1b2f8))
+ - don't generate build-id ([304ad94](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/304ad94b34c2117823169a199558e7484139caa1))
+ - don't rely on that gcc-ar is in the same directory as gcc ([7ef0b83](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7ef0b8377fa7fb3697dda5adfa44dafd7e14150f))
+ - enforce single partition for LTO build ([31f80ef](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/31f80efeefaee2c59db50a46cabe2b5fdf20e4ae))
+ - march handling with arch-features ([7275ac2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7275ac2af86277e2442ef4b0fee6c35cbe830056))
+ - move comment for VERSION_PATCH ([c25d1cc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c25d1ccf1e205b2781ecd0de91e91d35e57b79bc))
+ - mute sp_mk_generator from build log ([fbd32ac](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/fbd32ac081c421929728f454427b7839235d2075))
+ - properly manage versions in .versionrc.js ([7f74030](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/7f74030b89136a1673e2a949564403709bc48f5d))
+ - wrap toolchain paths in double quotes ([4731c00](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/4731c00bb60915c0d4b29c082a752e9925a244b4))
+
+- **Tools**
+
+ - **Certificate Creation Tool**
+
+ - add guardrails around brainpool usage ([c0c280d](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/c0c280dfda7322dcaebb5c6341c0880bdf524e13))
+ - use a salt length equal to digest length for RSA-PSS ([e639ad2](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/e639ad23c8c7a1b320af9ebd519420ae7d431531))
+
+ - **Memory Mapping Tool**
+
+ - fix footprint free space calculation ([9e72d01](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/9e72d01ed29c350dfc0567c59bc482901211634b))
+ - fix memory map dump when SEPARATE_CODE_AND_RODATA=0 ([6dc8ee6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6dc8ee61ffeee8ea5aafdbef3121fa4e82b57932))
+
+ - **Marvell Tools**
+
+ - include mbedtls/version.h before use ([8eb4efe](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/8eb4efe70bd5b03917e2063ab8ff5646de88922a))
+
## [2.10.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.9.0..refs/tags/v2.10.0) (2023-11-21)
### ⚠ BREAKING CHANGES
@@ -2667,11 +3585,11 @@
- route GIC IPI interrupts during setup ([04cc91b](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/04cc91b43c1d10fcba563e18f06336987e6e3a24))
- use only one space for indentation ([dee5885](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/dee588591328b96d9b9ef908869c8b42bd2632f2))
- - **Versal NET**
+ - **Versal NET**
- - Enable a78 errata workarounds ([bcc6e4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcc6e4a02a88056b9c45ff28f405e09444433528))
- - add default values for silicon ([faa22d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/faa22d48d9929d57975b84ab76cb595afdcf57f4))
- - use api_id directly without FUNCID_MASK ([b0eb6d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0eb6d124b1764264778d17b1519bfe62b7b9337))
+ - Enable a78 errata workarounds ([bcc6e4a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bcc6e4a02a88056b9c45ff28f405e09444433528))
+ - add default values for silicon ([faa22d4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/faa22d48d9929d57975b84ab76cb595afdcf57f4))
+ - use api_id directly without FUNCID_MASK ([b0eb6d1](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/b0eb6d124b1764264778d17b1519bfe62b7b9337))
- **ZynqMP**
@@ -8839,7 +9757,7 @@
______________________________________________________________________
-*Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
[mbed tls releases]: https://tls.mbed.org/tech-updates/releases
[pr#1002]: https://github.com/ARM-software/arm-trusted-firmware/pull/1002#issuecomment-312650193
diff --git a/docs/conf.py b/docs/conf.py
index d4e5423..3f9655b 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -14,8 +14,8 @@
project = "Trusted Firmware-A"
author = "Trusted Firmware-A contributors"
-version = "2.10.0"
-release = "2.10.0"
+version = "2.11.0"
+release = "2.11.0"
# -- General configuration ---------------------------------------------------
diff --git a/docs/design_documents/cmake_framework.rst b/docs/design_documents/cmake_framework.rst
index d88942e..f946b2e 100644
--- a/docs/design_documents/cmake_framework.rst
+++ b/docs/design_documents/cmake_framework.rst
@@ -11,11 +11,7 @@
Abstract
--------
This document presents a proposal for a new buildsystem for TF-A using CMake,
-and as part of this a reusable CMake framework for embedded projects. For a
-summary about the proposal, please see the `Phabricator wiki page
-<https://developer.trustedfirmware.org/w/tf_a/cmake-buildsystem-proposal/>`_. As
-mentioned there, the proposal consists of two phases. The subject of this
-document is the first phase only.
+and as part of this a reusable CMake framework for embedded projects.
Introduction
------------
@@ -162,4 +158,4 @@
--------------
-*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 6ab95f9..52a9317 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -701,13 +701,6 @@
This option defaults to 0.
-- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot
- backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When
- set to ``1`` then measurements and additional metadata collected during the
- measured boot process are sent to the DICE Protection Environment for storage
- and processing. A certificate chain, which represents the boot state of the
- device, can be queried from the DPE.
-
- ``MARCH_DIRECTIVE``: used to pass a -march option from the platform build
options to the compiler. An example usage:
@@ -812,6 +805,21 @@
instead of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1
entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default value is 0.
+- ``RME_GPT_BITLOCK_BLOCK``: This defines the block size (in number of 512MB
+- blocks) covered by a single bit of the bitlock structure during RME GPT
+- operations. The lower the block size, the better opportunity for
+- parallelising GPT operations but at the cost of more bits being needed
+- for the bitlock structure. This numeric parameter can take the values
+- from 0 to 512 and must be a power of 2. The value of 0 is special and
+- and it chooses a single spinlock for all GPT L1 table entries. Default
+- value is 1 which corresponds to block size of 512MB per bit of bitlock
+- structure.
+
+- ``RME_GPT_MAX_BLOCK``: Numeric value in MB to define the maximum size of
+ supported contiguous blocks in GPT Library. This parameter can take the
+ values 0, 2, 32 and 512. Setting this value to 0 disables use of Contigious
+ descriptors. Default value is 2.
+
- ``ROT_KEY``: This option is used when ``GENERATE_COT=1``. It specifies a
file that contains the ROT private key in PEM format or a PKCS11 URI and
enforces public key hash generation. If ``SAVE_KEYS=1``, only a file is
@@ -1257,6 +1265,13 @@
Common build options
~~~~~~~~~~~~~~~~~~~~
+- ``DICE_PROTECTION_ENVIRONMENT``: Boolean flag to specify the measured boot
+ backend when ``MEASURED_BOOT`` is enabled. The default value is ``0``. When
+ set to ``1`` then measurements and additional metadata collected during the
+ measured boot process are sent to the DICE Protection Environment for storage
+ and processing. A certificate chain, which represents the boot state of the
+ device, can be queried from the DPE.
+
- ``DRTM_SUPPORT``: Boolean flag to enable support for Dynamic Root of Trust
for Measurement (DRTM). This feature has trust dependency on BL31 for taking
the measurements and recording them as per `PSA DRTM specification`_. For
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 0d4331f..6a0241f 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -31,7 +31,7 @@
Clang/LLVM 11.0.0
Device Tree Compiler 1.4.7
GNU make 3.81
-mbed TLS\ [#f1]_ 3.4.1
+mbed TLS\ [#f1]_ 3.6.0
Node.js [#f2]_ 16
OpenSSL 1.0.0
Poetry [#f2]_ 1.3.2
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index bab1086..43a7d59 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -31,8 +31,8 @@
The following source trees and binaries were used:
-- TF-A [`v2.9-rc0`_]
-- TFTF [`v2.9-rc0`_]
+- `TF-A v2.11-rc0`_
+- `TFTF v2.11-rc0`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
<Runtime Instrumentation Methodology>`
@@ -73,23 +73,23 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- parallel (v2.9)
+ parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 104.58 | 241.20 | 5.26 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 384.24 | 22.50 | 138.76 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 244.56 | 22.18 | 5.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 670.56 | 18.58 | 4.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 809.36 | 269.28 | 4.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 984.96 | 219.70 | 79.62 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-------------------+--------------------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-------------------+--------------------+-------------+
+ | 0 | 0 | 112.98 (-53.44%) | 26.16 (-89.33%) | 5.48 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 0 | 1 | 411.18 | 438.88 (+1572.56%) | 138.54 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 0 | 261.82 (+150.88%) | 474.06 (+1649.30%) | 5.6 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 1 | 714.76 (+86.84%) | 26.44 | 4.48 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 2 | 862.66 | 149.34 (-45.00%) | 4.38 |
+ +---------+------+-------------------+--------------------+-------------+
+ | 1 | 3 | 1045.12 | 98.12 (-55.76%) | 79.74 |
+ +---------+------+-------------------+--------------------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
parallel (v2.10)
@@ -111,22 +111,22 @@
+---------+------+-------------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- serial (v2.9)
+ serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 236.56 | 23.24 | 138.18 |
+ | 0 | 0 | 244.42 | 27.42 | 138.12 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 236.86 | 23.28 | 138.10 |
+ | 0 | 1 | 245.02 | 27.34 | 138.08 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 281.04 | 22.80 | 77.24 |
+ | 1 | 0 | 297.66 | 26.2 | 77.68 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 100.28 | 18.52 | 4.54 |
+ | 1 | 1 | 108.02 | 21.94 | 4.52 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 100.12 | 18.78 | 4.50 |
+ | 1 | 2 | 107.48 | 21.88 | 4.46 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 100.36 | 18.94 | 4.44 |
+ | 1 | 3 | 107.52 | 21.86 | 4.46 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
@@ -152,23 +152,23 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
- parallel (v2.9)
+ parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 662.34 | 15.22 | 8.08 |
- +---------+------+-----------+--------+-------------+
- | 0 | 1 | 802.00 | 15.50 | 8.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 385.22 | 15.74 | 7.88 |
- +---------+------+-----------+--------+-------------+
- | 1 | 1 | 106.16 | 16.06 | 7.44 |
- +---------+------+-----------+--------+-------------+
- | 1 | 2 | 524.38 | 15.64 | 7.34 |
- +---------+------+-----------+--------+-------------+
- | 1 | 3 | 246.00 | 15.78 | 7.72 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-------------------+--------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-------------------+--------+-------------+
+ | 0 | 0 | 704.46 | 19.28 | 7.86 |
+ +---------+------+-------------------+--------+-------------+
+ | 0 | 1 | 853.66 | 18.78 | 7.82 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 0 | 556.52 (+425.51%) | 19.06 | 7.82 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 1 | 113.28 (-70.47%) | 19.28 | 7.48 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 2 | 260.62 (-50.22%) | 19.8 | 7.26 |
+ +---------+------+-------------------+--------+-------------+
+ | 1 | 3 | 408.16 (+66.94%) | 19.82 | 7.38 |
+ +---------+------+-------------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
parallel (v2.10)
@@ -189,22 +189,22 @@
| 1 | 3 | 244.5 | 20.16 | 7.56 |
+---------+------+-------------------+--------+-------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 99.80 | 15.94 | 5.42 |
+ | 0 | 0 | 106.78 | 19.2 | 5.32 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 99.76 | 15.80 | 5.24 |
+ | 0 | 1 | 107.44 | 19.64 | 5.44 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 278.26 | 16.16 | 4.58 |
+ | 1 | 0 | 295.82 | 19.14 | 4.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 96.88 | 16.00 | 4.52 |
+ | 1 | 1 | 104.34 | 19.18 | 4.28 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 96.80 | 16.12 | 4.54 |
+ | 1 | 2 | 103.96 | 19.34 | 4.4 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 96.88 | 16.12 | 4.54 |
+ | 1 | 3 | 104.32 | 19.18 | 4.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
@@ -231,22 +231,22 @@
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9)
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 235.76 | 26.14 | 137.80 |
+ | 0 | 0 | 243.62 | 29.84 | 137.66 |
+---------+------+-----------+--------+-------------+
- | 0 | 1 | 235.40 | 25.72 | 137.62 |
+ | 0 | 1 | 243.88 | 29.54 | 137.8 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 174.70 | 22.40 | 77.26 |
+ | 1 | 0 | 183.26 | 26.22 | 77.76 |
+---------+------+-----------+--------+-------------+
- | 1 | 1 | 100.92 | 24.04 | 4.52 |
+ | 1 | 1 | 107.64 | 26.74 | 4.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 2 | 100.68 | 22.44 | 4.36 |
+ | 1 | 2 | 107.52 | 25.9 | 4.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 3 | 101.36 | 22.70 | 4.52 |
+ | 1 | 3 | 107.74 | 25.8 | 4.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10)
@@ -272,23 +272,23 @@
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.9)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.11)
- +-------------+--------+-------------+
- | Cluster | Core | Latency |
- +-------------+--------+-------------+
- | 0 | 0 | 1.48 |
- +-------------+--------+-------------+
- | 0 | 1 | 1.04 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.56 |
- +-------------+--------+-------------+
- | 1 | 1 | 0.92 |
- +-------------+--------+-------------+
- | 1 | 2 | 0.96 |
- +-------------+--------+-------------+
- | 1 | 3 | 0.96 |
- +-------------+--------+-------------+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +-------------+--------+--------------+
+ | 0 | 0 | 1.26 |
+ +-------------+--------+--------------+
+ | 0 | 1 | 0.96 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.54 |
+ +-------------+--------+--------------+
+ | 1 | 1 | 0.94 |
+ +-------------+--------+--------------+
+ | 1 | 2 | 0.92 |
+ +-------------+--------+--------------+
+ | 1 | 3 | 1.02 |
+ +-------------+--------+--------------+
.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (2.10)
@@ -526,8 +526,9 @@
--------------
-*Copyright (c) 2019-2023, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.*
.. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
-.. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0
+.. _TF-A v2.11-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.11-rc0
+.. _TFTF v2.11-rc0: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/?h=v2.11-rc0
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index fd3c9c9..c1c4dd6 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -6,8 +6,8 @@
The following source trees and binaries were used:
-- TF-A [`v2.9-rc0-16-g666aec401`_]
-- TFTF [`v2.9-rc0`_]
+- `TF-A v2.11-rc0`_
+- `TFTF v2.11-rc0`_
- SCP/MCP `Prebuilt Images`_
Please see the Runtime Instrumentation :ref:`Testing Methodology
@@ -92,20 +92,19 @@
``CPU_SUSPEND`` to deepest power level
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- parallel (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in parallel (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.80 | 10.08 | 0.80 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 4.14 | 15.92 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 3.68 | 12.96 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 3.36 | 18.58 | 0.18 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+----------------+--------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+--------+----------------+
+ | 0 | 0 | 3.0 (+41.51%) | 23.14 | 1.2 (+185.71%) |
+ +---------+------+----------------+--------+----------------+
+ | 0 | 0 | 4.6 | 35.86 | 0.3 |
+ +---------+------+----------------+--------+----------------+
+ | 1 | 0 | 3.68 (+33.33%) | 33.36 | 0.3 |
+ +---------+------+----------------+--------+----------------+
+ | 1 | 0 | 3.7 (+40.15%) | 38.1 | 0.28 |
+ +---------+------+----------------+--------+----------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
parallel (v2.10)
@@ -122,19 +121,18 @@
| 1 | 0 | 2.64 | 44.56 (+139.83%) | 0.36 (+100.00%) |
+---------+------+----------------+------------------+-----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
- serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in serial (v2.11)
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.86 | 9.92 | 0.32 |
+ | 0 | 0 | 1.7 | 22.46 | 0.3 |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.70 | 10.48 | 0.36 |
+ | 0 | 0 | 2.28 | 22.5 | 0.3 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.78 | 9.72 | 0.16 |
+ | 1 | 0 | 2.14 | 21.5 | 0.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.94 | 10.44 | 0.16 |
+ | 1 | 0 | 2.24 | 22.66 | 0.3 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
@@ -155,22 +153,19 @@
``CPU_SUSPEND`` to power level 0
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
- parallel (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in parallel (v2.11)
- +---------------------------------------------------+
- | test_rt_instr_cpu_susp_parallel |
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 0.88 | 12.32 | 0.26 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 2.12 | 14.62 | 0.26 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.86 | 14.14 | 0.16 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.92 | 9.44 | 0.18 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+----------------+--------+-------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+----------------+--------+-------------+
+ | 0 | 0 | 0.94 (-37.33%) | 30.36 | 0.3 |
+ +---------+------+----------------+--------+-------------+
+ | 0 | 0 | 2.12 | 33.12 | 0.28 |
+ +---------+------+----------------+--------+-------------+
+ | 1 | 0 | 2.08 | 32.56 | 0.3 |
+ +---------+------+----------------+--------+-------------+
+ | 1 | 0 | 2.14 | 21.92 | 0.28 |
+ +---------+------+----------------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
parallel (v2.10)
@@ -187,20 +182,18 @@
| 1 | 0 | 2.04 | 23.1 (+144.70%) | 0.24 |
+---------+------+---------------+------------------+----------------+
-.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.9)
+.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.11)
- +---------------------------------------------------+
- | test_rt_instr_cpu_susp_serial |
+---------+------+-----------+--------+-------------+
| Cluster | Core | Powerdown | Wakeup | Cache Flush |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.52 | 9.40 | 0.30 |
+ | 0 | 0 | 1.64 | 21.88 | 0.34 |
+---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.92 | 9.80 | 0.18 |
+ | 0 | 0 | 2.42 | 21.76 | 0.34 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 2.20 | 9.60 | 0.14 |
+ | 1 | 0 | 2.02 | 21.14 | 0.32 |
+---------+------+-----------+--------+-------------+
- | 1 | 0 | 1.82 | 9.78 | 0.18 |
+ | 1 | 0 | 2.18 | 22.3 | 0.34 |
+---------+------+-----------+--------+-------------+
.. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.10)
@@ -223,19 +216,19 @@
``CPU_OFF`` on all non-lead CPUs in sequence then, ``CPU_SUSPEND`` on the lead
core to the deepest power level.
-.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.9)
+.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.11)
- +---------+------+-----------+--------+-------------+
- | Cluster | Core | Powerdown | Wakeup | Cache Flush |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 1.84 | 9.94 | 0.32 |
- +---------+------+-----------+--------+-------------+
- | 0 | 0 | 14.20 | 13.10 | 0.50 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 13.88 | 12.36 | 0.42 |
- +---------+------+-----------+--------+-------------+
- | 1 | 0 | 14.40 | 13.26 | 0.52 |
- +---------+------+-----------+--------+-------------+
+ +---------+------+-----------+--------+----------------+
+ | Cluster | Core | Powerdown | Wakeup | Cache Flush |
+ +---------+------+-----------+--------+----------------+
+ | 0 | 0 | 1.96 | 22.44 | 0.38 |
+ +---------+------+-----------+--------+----------------+
+ | 0 | 0 | 13.76 | 30.34 | 0.26 |
+ +---------+------+-----------+--------+----------------+
+ | 1 | 0 | 13.46 | 28.28 | 0.24 |
+ +---------+------+-----------+--------+----------------+
+ | 1 | 0 | 13.84 | 30.06 | 0.28 (-60.00%) |
+ +---------+------+-----------+--------+----------------+
.. table:: ``CPU_OFF`` latencies (µs) on all non-lead CPUs (v2.10)
@@ -254,21 +247,19 @@
``CPU_VERSION`` in parallel
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.9)
+.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.11)
- +------------------------------------+
- | test_rt_instr_psci_version_parallel|
- +-------------+--------+-------------+
- | Cluster | Core | Latency |
- +-------------+--------+-------------+
- | 0 | 0 | 0.08 |
- +-------------+--------+-------------+
- | 0 | 0 | 0.26 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.20 |
- +-------------+--------+-------------+
- | 1 | 0 | 0.26 |
- +-------------+--------+-------------+
+ +-------------+--------+--------------+
+ | Cluster | Core | Latency |
+ +-------------+--------+--------------+
+ | 0 | 0 | 0.12 |
+ +-------------+--------+--------------+
+ | 0 | 0 | 0.24 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.2 |
+ +-------------+--------+--------------+
+ | 1 | 0 | 0.26 |
+ +-------------+--------+--------------+
.. table:: ``CPU_VERSION`` latency (µs) in parallel on all cores (v2.10)
@@ -288,10 +279,10 @@
--------------
-*Copyright (c) 2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2023-2024, Arm Limited. All rights reserved.*
-.. _v2.9-rc0-16-g666aec401: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/heads/v2.9-rc0-16-g666aec401
-.. _v2.9-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.9-rc0
+.. _TF-A v2.11-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.11-rc0
+.. _TFTF v2.11-rc0: https://review.trustedfirmware.org/plugins/gitiles/TF-A/tf-a-tests/+/refs/tags/v2.11-rc0
.. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
.. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/
.. _N1SDP: https://developer.arm.com/documentation/101489/latest
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index 33b3533..11bec7e 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -4,8 +4,8 @@
Getting Started
===============
-- Make sure you have a Github account and you are logged on both
- `developer.trustedfirmware.org`_ and `review.trustedfirmware.org`_.
+- Make sure you have a Github account and you are logged on to
+ `review.trustedfirmware.org`_.
Also make sure that you have registered your full name and email address in
your `review.trustedfirmware.org`_ profile. Otherwise, the Gerrit server
@@ -334,7 +334,6 @@
*Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.*
-.. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
.. _review.trustedfirmware.org: https://review.trustedfirmware.org
.. _Git guidelines: http://git-scm.com/book/ch5-2.html
.. _Gerrit Uploading Changes documentation: https://review.trustedfirmware.org/Documentation/user-upload.html
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 59adc7c..1e2f84b 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -807,15 +807,6 @@
TLBIRPALOS(addr, TLBI_SZ_512M);
}
-/*
- * Invalidate TLBs of GPT entries by Physical address, last level.
- *
- * @pa: the starting address for the range
- * of invalidation
- * @size: size of the range of invalidation
- */
-void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
-
/* Previously defined accessor functions with incomplete register names */
#define read_current_el() read_CurrentEl()
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index f9c4baf..93771df 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,6 @@
.globl zero_normalmem
.globl zeromem
.globl memcpy16
- .globl gpt_tlbi_by_pa_ll
.globl disable_mmu_el1
.globl disable_mmu_el3
@@ -594,20 +593,3 @@
b.lo 1b
ret
endfunc fixup_gdt_reloc
-
-/*
- * TODO: Currently only supports size of 4KB,
- * support other sizes as well.
- */
-func gpt_tlbi_by_pa_ll
-#if ENABLE_ASSERTIONS
- cmp x1, #PAGE_SIZE_4KB
- ASM_ASSERT(eq)
- tst x0, #(PAGE_SIZE_MASK)
- ASM_ASSERT(eq)
-#endif
- lsr x0, x0, #FOUR_KB_SHIFT /* 4KB size encoding is zero */
- sys #6, c8, c4, #7, x0 /* TLBI RPALOS, <Xt> */
- dsb sy
- ret
-endfunc gpt_tlbi_by_pa_ll
diff --git a/lib/gpt_rme/gpt_rme.c b/lib/gpt_rme/gpt_rme.c
index 72e905e..4d80373 100644
--- a/lib/gpt_rme/gpt_rme.c
+++ b/lib/gpt_rme/gpt_rme.c
@@ -57,6 +57,13 @@
*/
static const gpt_p_val_e gpt_p_lookup[] = {PGS_4KB_P, PGS_64KB_P, PGS_16KB_P};
+static void shatter_2mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+static void shatter_32mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+static void shatter_512mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+
/*
* This structure contains GPT configuration data
*/
@@ -70,11 +77,188 @@
static gpt_config_t gpt_config;
+/*
+ * Number of L1 entries in 2MB, depending on GPCCR_EL3.PGS:
+ * +-------+------------+
+ * | PGS | L1 entries |
+ * +-------+------------+
+ * | 4KB | 32 |
+ * +-------+------------+
+ * | 16KB | 8 |
+ * +-------+------------+
+ * | 64KB | 2 |
+ * +-------+------------+
+ */
+static unsigned int gpt_l1_cnt_2mb;
+
+/*
+ * Mask for the L1 index field, depending on
+ * GPCCR_EL3.L0GPTSZ and GPCCR_EL3.PGS:
+ * +---------+-------------------------------+
+ * | | PGS |
+ * +---------+----------+----------+---------+
+ * | L0GPTSZ | 4KB | 16KB | 64KB |
+ * +---------+----------+----------+---------+
+ * | 1GB | 0x3FFF | 0xFFF | 0x3FF |
+ * +---------+----------+----------+---------+
+ * | 16GB | 0x3FFFF | 0xFFFF | 0x3FFF |
+ * +---------+----------+----------+---------+
+ * | 64GB | 0xFFFFF | 0x3FFFF | 0xFFFF |
+ * +---------+----------+----------+---------+
+ * | 512GB | 0x7FFFFF | 0x1FFFFF | 0x7FFFF |
+ * +---------+----------+----------+---------+
+ */
+static uint64_t gpt_l1_index_mask;
+
+/* Number of 128-bit L1 entries in 2MB, 32MB and 512MB */
+#define L1_QWORDS_2MB (gpt_l1_cnt_2mb / 2U)
+#define L1_QWORDS_32MB (L1_QWORDS_2MB * 16U)
+#define L1_QWORDS_512MB (L1_QWORDS_32MB * 16U)
+
+/* Size in bytes of L1 entries in 2MB, 32MB */
+#define L1_BYTES_2MB (gpt_l1_cnt_2mb * sizeof(uint64_t))
+#define L1_BYTES_32MB (L1_BYTES_2MB * 16U)
+
+/* Get the index into the L1 table from a physical address */
+#define GPT_L1_INDEX(_pa) \
+ (((_pa) >> (unsigned int)GPT_L1_IDX_SHIFT(gpt_config.p)) & gpt_l1_index_mask)
+
/* These variables are used during initialization of the L1 tables */
-static unsigned int gpt_next_l1_tbl_idx;
static uintptr_t gpt_l1_tbl;
+/* These variable is used during runtime */
+#if (RME_GPT_BITLOCK_BLOCK == 0)
+/*
+ * The GPTs are protected by a global spinlock to ensure
+ * that multiple CPUs do not attempt to change the descriptors at once.
+ */
+static spinlock_t gpt_lock;
+#else
+
+/* Bitlocks base address */
+static bitlock_t *gpt_bitlock_base;
+#endif
+
+/* Lock/unlock macros for GPT entries */
+#if (RME_GPT_BITLOCK_BLOCK == 0)
+/*
+ * Access to GPT is controlled by a global lock to ensure
+ * that no more than one CPU is allowed to make changes at any
+ * given time.
+ */
+#define GPT_LOCK spin_lock(&gpt_lock)
+#define GPT_UNLOCK spin_unlock(&gpt_lock)
+#else
+/*
+ * Access to a block of memory is controlled by a bitlock.
+ * Size of block = RME_GPT_BITLOCK_BLOCK * 512MB.
+ */
+#define GPT_LOCK bit_lock(gpi_info.lock, gpi_info.mask)
+#define GPT_UNLOCK bit_unlock(gpi_info.lock, gpi_info.mask)
+#endif
+
+static void tlbi_page_dsbosh(uintptr_t base)
+{
+ /* Look-up table for invalidation TLBs for 4KB, 16KB and 64KB pages */
+ static const gpt_tlbi_lookup_t tlbi_page_lookup[] = {
+ { tlbirpalos_4k, ~(SZ_4K - 1UL) },
+ { tlbirpalos_64k, ~(SZ_64K - 1UL) },
+ { tlbirpalos_16k, ~(SZ_16K - 1UL) }
+ };
+
+ tlbi_page_lookup[gpt_config.pgs].function(
+ base & tlbi_page_lookup[gpt_config.pgs].mask);
+ dsbosh();
+}
+
/*
+ * Helper function to fill out GPI entries in a single L1 table
+ * with Granules or Contiguous descriptor.
+ *
+ * Parameters
+ * l1 Pointer to 2MB, 32MB or 512MB aligned L1 table entry to fill out
+ * l1_desc GPT Granules or Contiguous descriptor set this range to
+ * cnt Number of double 128-bit L1 entries to fill
+ *
+ */
+static void fill_desc(uint64_t *l1, uint64_t l1_desc, unsigned int cnt)
+{
+ uint128_t *l1_quad = (uint128_t *)l1;
+ uint128_t l1_quad_desc = (uint128_t)l1_desc | ((uint128_t)l1_desc << 64);
+
+ VERBOSE("GPT: %s(%p 0x%"PRIx64" %u)\n", __func__, l1, l1_desc, cnt);
+
+ for (unsigned int i = 0U; i < cnt; i++) {
+ *l1_quad++ = l1_quad_desc;
+ }
+}
+
+static void shatter_2mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ unsigned long idx = GPT_L1_INDEX(ALIGN_2MB(base));
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n",
+ __func__, base, l1_desc);
+
+ /* Convert 2MB Contiguous block to Granules */
+ fill_desc(&gpi_info->gpt_l1_addr[idx], l1_desc, L1_QWORDS_2MB);
+}
+
+static void shatter_32mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ unsigned long idx = GPT_L1_INDEX(ALIGN_2MB(base));
+ const uint64_t *l1_gran = &gpi_info->gpt_l1_addr[idx];
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB);
+ uint64_t *l1;
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n",
+ __func__, base, l1_desc);
+
+ /* Get index corresponding to 32MB aligned address */
+ idx = GPT_L1_INDEX(ALIGN_32MB(base));
+ l1 = &gpi_info->gpt_l1_addr[idx];
+
+ /* 16 x 2MB blocks in 32MB */
+ for (unsigned int i = 0U; i < 16U; i++) {
+ /* Fill with Granules or Contiguous descriptors */
+ fill_desc(l1, (l1 == l1_gran) ? l1_desc : l1_cont_desc,
+ L1_QWORDS_2MB);
+ l1 = (uint64_t *)((uintptr_t)l1 + L1_BYTES_2MB);
+ }
+}
+
+static void shatter_512mb(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ unsigned long idx = GPT_L1_INDEX(ALIGN_32MB(base));
+ const uint64_t *l1_32mb = &gpi_info->gpt_l1_addr[idx];
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB);
+ uint64_t *l1;
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n",
+ __func__, base, l1_desc);
+
+ /* Get index corresponding to 512MB aligned address */
+ idx = GPT_L1_INDEX(ALIGN_512MB(base));
+ l1 = &gpi_info->gpt_l1_addr[idx];
+
+ /* 16 x 32MB blocks in 512MB */
+ for (unsigned int i = 0U; i < 16U; i++) {
+ if (l1 == l1_32mb) {
+ /* Shatter this 32MB block */
+ shatter_32mb(base, gpi_info, l1_desc);
+ } else {
+ /* Fill 32MB with Contiguous descriptors */
+ fill_desc(l1, l1_cont_desc, L1_QWORDS_32MB);
+ }
+
+ l1 = (uint64_t *)((uintptr_t)l1 + L1_BYTES_32MB);
+ }
+}
+
+/*
* This function checks to see if a GPI value is valid.
*
* These are valid GPI values.
@@ -213,10 +397,11 @@
* to see if this PAS would fall into one that has already been
* initialized.
*/
- for (unsigned int i = GPT_L0_IDX(pas_regions[idx].base_pa);
- i <= GPT_L0_IDX(pas_regions[idx].base_pa +
- pas_regions[idx].size - 1UL);
- i++) {
+ for (unsigned int i =
+ (unsigned int)GPT_L0_IDX(pas_regions[idx].base_pa);
+ i <= GPT_L0_IDX(pas_regions[idx].base_pa +
+ pas_regions[idx].size - 1UL);
+ i++) {
if ((GPT_L0_TYPE(l0_desc[i]) == GPT_L0_TYPE_BLK_DESC) &&
(GPT_L0_BLKD_GPI(l0_desc[i]) == GPT_GPI_ANY)) {
/* This descriptor is unused so continue */
@@ -227,7 +412,7 @@
* This descriptor has been initialized in a previous
* call to this function so cannot be initialized again.
*/
- ERROR("GPT: PAS[%u] overlaps with previous L0[%d]!\n",
+ ERROR("GPT: PAS[%u] overlaps with previous L0[%u]!\n",
idx, i);
return -EFAULT;
}
@@ -318,7 +503,7 @@
static int validate_l0_params(gpccr_pps_e pps, uintptr_t l0_mem_base,
size_t l0_mem_size)
{
- size_t l0_alignment;
+ size_t l0_alignment, locks_size = 0;
/*
* Make sure PPS is valid and then store it since macros need this value
@@ -344,12 +529,28 @@
return -EFAULT;
}
- /* Check size */
- if (l0_mem_size < GPT_L0_TABLE_SIZE(gpt_config.t)) {
- ERROR("%sL0%s\n", "GPT: Inadequate ", " memory\n");
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /*
+ * Size of bitlocks in bytes for the protected address space
+ * with RME_GPT_BITLOCK_BLOCK * 512MB per bitlock.
+ */
+ locks_size = GPT_PPS_ACTUAL_SIZE(gpt_config.t) /
+ (RME_GPT_BITLOCK_BLOCK * SZ_512M * 8U);
+
+ /*
+ * If protected space size is less than the size covered
+ * by 'bitlock' structure, check for a single bitlock.
+ */
+ if (locks_size < LOCK_SIZE) {
+ locks_size = LOCK_SIZE;
+ }
+#endif
+ /* Check size for L0 tables and bitlocks */
+ if (l0_mem_size < (GPT_L0_TABLE_SIZE(gpt_config.t) + locks_size)) {
+ ERROR("GPT: Inadequate L0 memory\n");
ERROR(" Expected 0x%lx bytes, got 0x%lx bytes\n",
- GPT_L0_TABLE_SIZE(gpt_config.t),
- l0_mem_size);
+ GPT_L0_TABLE_SIZE(gpt_config.t) + locks_size,
+ l0_mem_size);
return -ENOMEM;
}
@@ -397,9 +598,10 @@
/* Make sure enough space was supplied */
if (l1_mem_size < l1_gpt_mem_sz) {
- ERROR("%sL1 GPTs%s", "GPT: Inadequate ", " memory\n");
+ ERROR("%sL1 GPTs%s", (const char *)"GPT: Inadequate ",
+ (const char *)" memory\n");
ERROR(" Expected 0x%lx bytes, got 0x%lx bytes\n",
- l1_gpt_mem_sz, l1_mem_size);
+ l1_gpt_mem_sz, l1_mem_size);
return -ENOMEM;
}
@@ -418,8 +620,7 @@
static void generate_l0_blk_desc(pas_region_t *pas)
{
uint64_t gpt_desc;
- unsigned int end_idx;
- unsigned int idx;
+ unsigned long idx, end_idx;
uint64_t *l0_gpt_arr;
assert(gpt_config.plat_gpt_l0_base != 0U);
@@ -448,7 +649,7 @@
/* Generate the needed block descriptors */
for (; idx < end_idx; idx++) {
l0_gpt_arr[idx] = gpt_desc;
- VERBOSE("GPT: L0 entry (BLOCK) index %u [%p]: GPI = 0x%"PRIx64" (0x%"PRIx64")\n",
+ VERBOSE("GPT: L0 entry (BLOCK) index %lu [%p]: GPI = 0x%"PRIx64" (0x%"PRIx64")\n",
idx, &l0_gpt_arr[idx],
(gpt_desc >> GPT_L0_BLK_DESC_GPI_SHIFT) &
GPT_L0_BLK_DESC_GPI_MASK, l0_gpt_arr[idx]);
@@ -482,54 +683,202 @@
return end_pa;
}
- return (cur_idx + 1U) << GPT_L0_IDX_SHIFT;
+ return (cur_idx + 1UL) << GPT_L0_IDX_SHIFT;
}
/*
- * Helper function to fill out GPI entries in a single L1 table. This function
- * fills out entire L1 descriptors at a time to save memory writes.
+ * Helper function to fill out GPI entries from 'first' granule address of
+ * the specified 'length' in a single L1 table with 'l1_desc' Contiguous
+ * descriptor.
*
* Parameters
- * gpi GPI to set this range to
* l1 Pointer to L1 table to fill out
- * first Address of first granule in range.
- * last Address of last granule in range (inclusive).
+ * first Address of first granule in range
+ * length Length of the range in bytes
+ * gpi GPI set this range to
+ *
+ * Return
+ * Address of next granule in range.
*/
-static void fill_l1_tbl(uint64_t gpi, uint64_t *l1, uintptr_t first,
- uintptr_t last)
+static uintptr_t fill_l1_cont_desc(uint64_t *l1, uintptr_t first,
+ size_t length, unsigned int gpi)
{
- uint64_t gpi_field = GPT_BUILD_L1_DESC(gpi);
- uint64_t gpi_mask = ULONG_MAX;
+ /*
+ * Look up table for contiguous blocks and descriptors.
+ * Entries should be defined in descending block sizes:
+ * 512MB, 32MB and 2MB.
+ */
+ static const gpt_fill_lookup_t gpt_fill_lookup[] = {
+#if (RME_GPT_MAX_BLOCK == 512)
+ { SZ_512M, GPT_L1_CONT_DESC_512MB },
+#endif
+#if (RME_GPT_MAX_BLOCK >= 32)
+ { SZ_32M, GPT_L1_CONT_DESC_32MB },
+#endif
+#if (RME_GPT_MAX_BLOCK != 0)
+ { SZ_2M, GPT_L1_CONT_DESC_2MB }
+#endif
+ };
- assert(first <= last);
- assert((first & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) == 0U);
- assert((last & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1)) == 0U);
- assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
- assert(l1 != NULL);
+ /*
+ * Iterate through all block sizes (512MB, 32MB and 2MB)
+ * starting with maximum supported.
+ */
+ for (unsigned long i = 0UL; i < ARRAY_SIZE(gpt_fill_lookup); i++) {
+ /* Calculate index */
+ unsigned long idx = GPT_L1_INDEX(first);
+
+ /* Contiguous block size */
+ size_t cont_size = gpt_fill_lookup[i].size;
+
+ if (GPT_REGION_IS_CONT(length, first, cont_size)) {
+
+ /* Generate Contiguous descriptor */
+ uint64_t l1_desc = GPT_L1_GPI_CONT_DESC(gpi,
+ gpt_fill_lookup[i].desc);
+
+ /* Number of 128-bit L1 entries in block */
+ unsigned int cnt;
+
+ switch (cont_size) {
+ case SZ_512M:
+ cnt = L1_QWORDS_512MB;
+ break;
+ case SZ_32M:
+ cnt = L1_QWORDS_32MB;
+ break;
+ default: /* SZ_2MB */
+ cnt = L1_QWORDS_2MB;
+ }
+
+ VERBOSE("GPT: Contiguous descriptor 0x%"PRIxPTR" %luMB\n",
+ first, cont_size / SZ_1M);
+
+ /* Fill Contiguous descriptors */
+ fill_desc(&l1[idx], l1_desc, cnt);
+ first += cont_size;
+ length -= cont_size;
+
+ if (length == 0UL) {
+ break;
+ }
+ }
+ }
+
+ return first;
+}
+
+/* Build Granules descriptor with the same 'gpi' for every GPI entry */
+static uint64_t build_l1_desc(unsigned int gpi)
+{
+ uint64_t l1_desc = (uint64_t)gpi | ((uint64_t)gpi << 4);
+
+ l1_desc |= (l1_desc << 8);
+ l1_desc |= (l1_desc << 16);
+ return (l1_desc | (l1_desc << 32));
+}
+
+/*
+ * Helper function to fill out GPI entries from 'first' to 'last' granule
+ * address in a single L1 table with 'l1_desc' Granules descriptor.
+ *
+ * Parameters
+ * l1 Pointer to L1 table to fill out
+ * first Address of first granule in range
+ * last Address of last granule in range (inclusive)
+ * gpi GPI set this range to
+ *
+ * Return
+ * Address of next granule in range.
+ */
+static uintptr_t fill_l1_gran_desc(uint64_t *l1, uintptr_t first,
+ uintptr_t last, unsigned int gpi)
+{
+ uint64_t gpi_mask;
+ unsigned long i;
+
+ /* Generate Granules descriptor */
+ uint64_t l1_desc = build_l1_desc(gpi);
/* Shift the mask if we're starting in the middle of an L1 entry */
- gpi_mask = gpi_mask << (GPT_L1_GPI_IDX(gpt_config.p, first) << 2);
+ gpi_mask = ULONG_MAX << (GPT_L1_GPI_IDX(gpt_config.p, first) << 2);
/* Fill out each L1 entry for this region */
- for (unsigned int i = GPT_L1_IDX(gpt_config.p, first);
- i <= GPT_L1_IDX(gpt_config.p, last); i++) {
+ for (i = GPT_L1_INDEX(first); i <= GPT_L1_INDEX(last); i++) {
+
/* Account for stopping in the middle of an L1 entry */
- if (i == GPT_L1_IDX(gpt_config.p, last)) {
+ if (i == GPT_L1_INDEX(last)) {
gpi_mask &= (gpi_mask >> ((15U -
GPT_L1_GPI_IDX(gpt_config.p, last)) << 2));
}
+ assert((l1[i] & gpi_mask) == (GPT_L1_ANY_DESC & gpi_mask));
+
/* Write GPI values */
- assert((l1[i] & gpi_mask) ==
- (GPT_BUILD_L1_DESC(GPT_GPI_ANY) & gpi_mask));
- l1[i] = (l1[i] & ~gpi_mask) | (gpi_mask & gpi_field);
+ l1[i] = (l1[i] & ~gpi_mask) | (l1_desc & gpi_mask);
/* Reset mask */
gpi_mask = ULONG_MAX;
}
+
+ return last + GPT_PGS_ACTUAL_SIZE(gpt_config.p);
}
/*
+ * Helper function to fill out GPI entries in a single L1 table.
+ * This function fills out an entire L1 table with either Contiguous
+ * or Granules descriptors depending on region length and alignment.
+ *
+ * Parameters
+ * l1 Pointer to L1 table to fill out
+ * first Address of first granule in range
+ * last Address of last granule in range (inclusive)
+ * gpi GPI set this range to
+ */
+static void fill_l1_tbl(uint64_t *l1, uintptr_t first, uintptr_t last,
+ unsigned int gpi)
+{
+ assert(l1 != NULL);
+ assert(first <= last);
+ assert((first & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) == 0UL);
+ assert((last & (GPT_PGS_ACTUAL_SIZE(gpt_config.p) - 1UL)) == 0UL);
+ assert(GPT_L0_IDX(first) == GPT_L0_IDX(last));
+
+ while (first < last) {
+ /* Region length */
+ size_t length = last - first + GPT_PGS_ACTUAL_SIZE(gpt_config.p);
+
+ if (length < SZ_2M) {
+ /*
+ * Fill with Granule descriptor in case of
+ * region length < 2MB.
+ */
+ first = fill_l1_gran_desc(l1, first, last, gpi);
+
+ } else if ((first & (SZ_2M - UL(1))) == UL(0)) {
+ /*
+ * For region length >= 2MB and at least 2MB aligned
+ * call to fill_l1_cont_desc will iterate through
+ * all block sizes (512MB, 32MB and 2MB) supported and
+ * fill corresponding Contiguous descriptors.
+ */
+ first = fill_l1_cont_desc(l1, first, length, gpi);
+ } else {
+ /*
+ * For not aligned region >= 2MB fill with Granules
+ * descriptors up to the next 2MB aligned address.
+ */
+ uintptr_t new_last = ALIGN_2MB(first + SZ_2M) -
+ GPT_PGS_ACTUAL_SIZE(gpt_config.p);
+
+ first = fill_l1_gran_desc(l1, first, new_last, gpi);
+ }
+ }
+
+ assert(first == (last + GPT_PGS_ACTUAL_SIZE(gpt_config.p)));
+}
+
+/*
* This function finds the next available unused L1 table and initializes all
* granules descriptor entries to GPI_ANY. This ensures that there are no chunks
* of GPI_NO_ACCESS (0b0000) memory floating around in the system in the
@@ -543,16 +892,14 @@
static uint64_t *get_new_l1_tbl(void)
{
/* Retrieve the next L1 table */
- uint64_t *l1 = (uint64_t *)((uint64_t)(gpt_l1_tbl) +
- (GPT_L1_TABLE_SIZE(gpt_config.p) *
- gpt_next_l1_tbl_idx));
+ uint64_t *l1 = (uint64_t *)gpt_l1_tbl;
- /* Increment L1 counter */
- gpt_next_l1_tbl_idx++;
+ /* Increment L1 GPT address */
+ gpt_l1_tbl += GPT_L1_TABLE_SIZE(gpt_config.p);
/* Initialize all GPIs to GPT_GPI_ANY */
for (unsigned int i = 0U; i < GPT_L1_ENTRY_COUNT(gpt_config.p); i++) {
- l1[i] = GPT_BUILD_L1_DESC(GPT_GPI_ANY);
+ l1[i] = GPT_L1_ANY_DESC;
}
return l1;
@@ -573,7 +920,7 @@
uintptr_t last_gran_pa;
uint64_t *l0_gpt_base;
uint64_t *l1_gpt_arr;
- unsigned int l0_idx;
+ unsigned int l0_idx, gpi;
assert(gpt_config.plat_gpt_l0_base != 0U);
assert(pas != NULL);
@@ -582,18 +929,19 @@
* Checking of PAS parameters has already been done in
* validate_pas_mappings so no need to check the same things again.
*/
-
end_pa = pas->base_pa + pas->size;
l0_gpt_base = (uint64_t *)gpt_config.plat_gpt_l0_base;
/* We start working from the granule at base PA */
cur_pa = pas->base_pa;
+ /* Get GPI */
+ gpi = GPT_PAS_ATTR_GPI(pas->attrs);
+
/* Iterate over each L0 region in this memory range */
- for (l0_idx = GPT_L0_IDX(pas->base_pa);
- l0_idx <= GPT_L0_IDX(end_pa - 1U);
+ for (l0_idx = (unsigned int)GPT_L0_IDX(pas->base_pa);
+ l0_idx <= (unsigned int)GPT_L0_IDX(end_pa - 1UL);
l0_idx++) {
-
/*
* See if the L0 entry is already a table descriptor or if we
* need to create one.
@@ -623,8 +971,7 @@
* function needs the addresses of the first granule and last
* granule in the range.
*/
- fill_l1_tbl(GPT_PAS_ATTR_GPI(pas->attrs), l1_gpt_arr,
- cur_pa, last_gran_pa);
+ fill_l1_tbl(l1_gpt_arr, cur_pa, last_gran_pa, gpi);
/* Advance cur_pa to first granule in next L0 region */
cur_pa = get_l1_end_pa(cur_pa, end_pa);
@@ -644,9 +991,9 @@
*/
static void flush_l0_for_pas_array(pas_region_t *pas, unsigned int pas_count)
{
- unsigned int idx;
- unsigned int start_idx;
- unsigned int end_idx;
+ unsigned long idx;
+ unsigned long start_idx;
+ unsigned long end_idx;
uint64_t *l0 = (uint64_t *)gpt_config.plat_gpt_l0_base;
assert(pas != NULL);
@@ -657,7 +1004,7 @@
end_idx = GPT_L0_IDX(pas[0].base_pa + pas[0].size - 1UL);
/* Find lowest and highest L0 indices used in this PAS array */
- for (idx = 1U; idx < pas_count; idx++) {
+ for (idx = 1UL; idx < pas_count; idx++) {
if (GPT_L0_IDX(pas[idx].base_pa) < start_idx) {
start_idx = GPT_L0_IDX(pas[idx].base_pa);
}
@@ -671,7 +1018,7 @@
* the end index value.
*/
flush_dcache_range((uintptr_t)&l0[start_idx],
- ((end_idx + 1U) - start_idx) * sizeof(uint64_t));
+ ((end_idx + 1UL) - start_idx) * sizeof(uint64_t));
}
/*
@@ -767,8 +1114,10 @@
int gpt_init_l0_tables(gpccr_pps_e pps, uintptr_t l0_mem_base,
size_t l0_mem_size)
{
- int ret;
uint64_t gpt_desc;
+ size_t locks_size = 0;
+ __unused bitlock_t *bit_locks;
+ int ret;
/* Ensure that MMU and Data caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
@@ -787,9 +1136,31 @@
((uint64_t *)l0_mem_base)[i] = gpt_desc;
}
- /* Flush updated L0 tables to memory */
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /* Initialise bitlocks at the end of L0 table */
+ bit_locks = (bitlock_t *)(l0_mem_base +
+ GPT_L0_TABLE_SIZE(gpt_config.t));
+
+ /* Size of bitlocks in bytes */
+ locks_size = GPT_PPS_ACTUAL_SIZE(gpt_config.t) /
+ (RME_GPT_BITLOCK_BLOCK * SZ_512M * 8U);
+
+ /*
+ * If protected space size is less than the size covered
+ * by 'bitlock' structure, initialise a single bitlock.
+ */
+ if (locks_size < LOCK_SIZE) {
+ locks_size = LOCK_SIZE;
+ }
+
+ for (size_t i = 0UL; i < (locks_size/LOCK_SIZE); i++) {
+ bit_locks[i].lock = 0U;
+ }
+#endif
+
+ /* Flush updated L0 tables and bitlocks to memory */
flush_dcache_range((uintptr_t)l0_mem_base,
- (size_t)GPT_L0_TABLE_SIZE(gpt_config.t));
+ GPT_L0_TABLE_SIZE(gpt_config.t) + locks_size);
/* Stash the L0 base address once initial setup is complete */
gpt_config.plat_gpt_l0_base = l0_mem_base;
@@ -806,7 +1177,7 @@
* This function can be called multiple times with different L1 memory ranges
* and PAS regions if it is desirable to place L1 tables in different locations
* in memory. (ex: you have multiple DDR banks and want to place the L1 tables
- * in the DDR bank that they control)
+ * in the DDR bank that they control).
*
* Parameters
* pgs PGS value to use for table generation.
@@ -822,8 +1193,7 @@
size_t l1_mem_size, pas_region_t *pas_regions,
unsigned int pas_count)
{
- int ret;
- int l1_gpt_cnt;
+ int l1_gpt_cnt, ret;
/* Ensure that MMU and Data caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
@@ -860,9 +1230,14 @@
/* Set up parameters for L1 table generation */
gpt_l1_tbl = l1_mem_base;
- gpt_next_l1_tbl_idx = 0U;
}
+ /* Number of L1 entries in 2MB depends on GPCCR_EL3.PGS value */
+ gpt_l1_cnt_2mb = (unsigned int)GPT_L1_ENTRY_COUNT_2MB(gpt_config.p);
+
+ /* Mask for the L1 index field */
+ gpt_l1_index_mask = GPT_L1_IDX_MASK(gpt_config.p);
+
INFO("GPT: Boot Configuration\n");
INFO(" PPS/T: 0x%x/%u\n", gpt_config.pps, gpt_config.t);
INFO(" PGS/P: 0x%x/%u\n", gpt_config.pgs, gpt_config.p);
@@ -894,7 +1269,7 @@
if (l1_gpt_cnt > 0) {
flush_dcache_range(l1_mem_base,
GPT_L1_TABLE_SIZE(gpt_config.p) *
- l1_gpt_cnt);
+ (size_t)l1_gpt_cnt);
}
/* Make sure that all the entries are written to the memory */
@@ -946,23 +1321,29 @@
gpt_config.pgs = (reg >> GPCCR_PGS_SHIFT) & GPCCR_PGS_MASK;
gpt_config.p = gpt_p_lookup[gpt_config.pgs];
+ /* Number of L1 entries in 2MB depends on GPCCR_EL3.PGS value */
+ gpt_l1_cnt_2mb = (unsigned int)GPT_L1_ENTRY_COUNT_2MB(gpt_config.p);
+
+ /* Mask for the L1 index field */
+ gpt_l1_index_mask = GPT_L1_IDX_MASK(gpt_config.p);
+
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /* Bitlocks at the end of L0 table */
+ gpt_bitlock_base = (bitlock_t *)(gpt_config.plat_gpt_l0_base +
+ GPT_L0_TABLE_SIZE(gpt_config.t));
+#endif
VERBOSE("GPT: Runtime Configuration\n");
VERBOSE(" PPS/T: 0x%x/%u\n", gpt_config.pps, gpt_config.t);
VERBOSE(" PGS/P: 0x%x/%u\n", gpt_config.pgs, gpt_config.p);
VERBOSE(" L0GPTSZ/S: 0x%x/%u\n", GPT_L0GPTSZ, GPT_S_VAL);
VERBOSE(" L0 base: 0x%"PRIxPTR"\n", gpt_config.plat_gpt_l0_base);
-
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ VERBOSE(" Bitlocks: 0x%"PRIxPTR"\n", (uintptr_t)gpt_bitlock_base);
+#endif
return 0;
}
/*
- * The L1 descriptors are protected by a spinlock to ensure that multiple
- * CPUs do not attempt to change the descriptors at once. In the future it
- * would be better to have separate spinlocks for each L1 descriptor.
- */
-static spinlock_t gpt_lock;
-
-/*
* A helper to write the value (target_pas << gpi_shift) to the index of
* the gpt_l1_addr.
*/
@@ -973,6 +1354,8 @@
*gpt_l1_desc &= ~(GPT_L1_GRAN_DESC_GPI_MASK << gpi_shift);
*gpt_l1_desc |= ((uint64_t)target_pas << gpi_shift);
gpt_l1_addr[idx] = *gpt_l1_desc;
+
+ dsboshst();
}
/*
@@ -982,6 +1365,7 @@
static int get_gpi_params(uint64_t base, gpi_info_t *gpi_info)
{
uint64_t gpt_l0_desc, *gpt_l0_base;
+ __unused unsigned int block_idx;
gpt_l0_base = (uint64_t *)gpt_config.plat_gpt_l0_base;
gpt_l0_desc = gpt_l0_base[GPT_L0_IDX(base)];
@@ -993,19 +1377,311 @@
/* Get the table index and GPI shift from PA */
gpi_info->gpt_l1_addr = GPT_L0_TBLD_ADDR(gpt_l0_desc);
- gpi_info->idx = GPT_L1_IDX(gpt_config.p, base);
+ gpi_info->idx = (unsigned int)GPT_L1_INDEX(base);
gpi_info->gpi_shift = GPT_L1_GPI_IDX(gpt_config.p, base) << 2;
- gpi_info->gpt_l1_desc = (gpi_info->gpt_l1_addr)[gpi_info->idx];
- gpi_info->gpi = (gpi_info->gpt_l1_desc >> gpi_info->gpi_shift) &
- GPT_L1_GRAN_DESC_GPI_MASK;
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ /* Block index */
+ block_idx = (unsigned int)(base / (RME_GPT_BITLOCK_BLOCK * SZ_512M));
+
+ /* Bitlock address and mask */
+ gpi_info->lock = &gpt_bitlock_base[block_idx / LOCK_BITS];
+ gpi_info->mask = 1U << (block_idx & (LOCK_BITS - 1U));
+#endif
return 0;
}
/*
+ * Helper to retrieve the gpt_l1_desc and GPI information from gpi_info.
+ * This function is called with bitlock or spinlock acquired.
+ */
+static void read_gpi(gpi_info_t *gpi_info)
+{
+ gpi_info->gpt_l1_desc = (gpi_info->gpt_l1_addr)[gpi_info->idx];
+
+ if ((gpi_info->gpt_l1_desc & GPT_L1_TYPE_CONT_DESC_MASK) ==
+ GPT_L1_TYPE_CONT_DESC) {
+ /* Read GPI from Contiguous descriptor */
+ gpi_info->gpi = (unsigned int)GPT_L1_CONT_GPI(gpi_info->gpt_l1_desc);
+ } else {
+ /* Read GPI from Granules descriptor */
+ gpi_info->gpi = (unsigned int)((gpi_info->gpt_l1_desc >> gpi_info->gpi_shift) &
+ GPT_L1_GRAN_DESC_GPI_MASK);
+ }
+}
+
+static void flush_page_to_popa(uintptr_t addr)
+{
+ size_t size = GPT_PGS_ACTUAL_SIZE(gpt_config.p);
+
+ if (is_feat_mte2_supported()) {
+ flush_dcache_to_popa_range_mte2(addr, size);
+ } else {
+ flush_dcache_to_popa_range(addr, size);
+ }
+}
+
+/*
+ * Helper function to check if all L1 entries in 2MB block have
+ * the same Granules descriptor value.
+ *
+ * Parameters
+ * base Base address of the region to be checked
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor with all entries
+ * set to the same GPI.
+ *
+ * Return
+ * true if L1 all entries have the same descriptor value, false otherwise.
+ */
+__unused static bool check_fuse_2mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* Last L1 entry index in 2MB block */
+ unsigned int long idx = GPT_L1_INDEX(ALIGN_2MB(base)) +
+ gpt_l1_cnt_2mb - 1UL;
+
+ /* Number of L1 entries in 2MB block */
+ unsigned int cnt = gpt_l1_cnt_2mb;
+
+ /*
+ * Start check from the last L1 entry and continue until the first
+ * non-matching to the passed Granules descriptor value is found.
+ */
+ while (cnt-- != 0U) {
+ if (gpi_info->gpt_l1_addr[idx--] != l1_desc) {
+ /* Non-matching L1 entry found */
+ return false;
+ }
+ }
+
+ return true;
+}
+
+__unused static void fuse_2mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* L1 entry index of the start of 2MB block */
+ unsigned long idx_2 = GPT_L1_INDEX(ALIGN_2MB(base));
+
+ /* 2MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB);
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n", __func__, base, l1_desc);
+
+ fill_desc(&gpi_info->gpt_l1_addr[idx_2], l1_cont_desc, L1_QWORDS_2MB);
+}
+
+/*
+ * Helper function to check if all 1st L1 entries of 2MB blocks
+ * in 32MB have the same 2MB Contiguous descriptor value.
+ *
+ * Parameters
+ * base Base address of the region to be checked
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor.
+ *
+ * Return
+ * true if all L1 entries have the same descriptor value, false otherwise.
+ */
+__unused static bool check_fuse_32mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* The 1st L1 entry index of the last 2MB block in 32MB */
+ unsigned long idx = GPT_L1_INDEX(ALIGN_32MB(base)) +
+ (15UL * gpt_l1_cnt_2mb);
+
+ /* 2MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 2MB);
+
+ /* Number of 2MB blocks in 32MB */
+ unsigned int cnt = 16U;
+
+ /* Set the first L1 entry to 2MB Contiguous descriptor */
+ gpi_info->gpt_l1_addr[GPT_L1_INDEX(ALIGN_2MB(base))] = l1_cont_desc;
+
+ /*
+ * Start check from the 1st L1 entry of the last 2MB block and
+ * continue until the first non-matching to 2MB Contiguous descriptor
+ * value is found.
+ */
+ while (cnt-- != 0U) {
+ if (gpi_info->gpt_l1_addr[idx] != l1_cont_desc) {
+ /* Non-matching L1 entry found */
+ return false;
+ }
+ idx -= gpt_l1_cnt_2mb;
+ }
+
+ return true;
+}
+
+__unused static void fuse_32mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* L1 entry index of the start of 32MB block */
+ unsigned long idx_32 = GPT_L1_INDEX(ALIGN_32MB(base));
+
+ /* 32MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB);
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n", __func__, base, l1_desc);
+
+ fill_desc(&gpi_info->gpt_l1_addr[idx_32], l1_cont_desc, L1_QWORDS_32MB);
+}
+
+/*
+ * Helper function to check if all 1st L1 entries of 32MB blocks
+ * in 512MB have the same 32MB Contiguous descriptor value.
+ *
+ * Parameters
+ * base Base address of the region to be checked
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor.
+ *
+ * Return
+ * true if all L1 entries have the same descriptor value, false otherwise.
+ */
+__unused static bool check_fuse_512mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* The 1st L1 entry index of the last 32MB block in 512MB */
+ unsigned long idx = GPT_L1_INDEX(ALIGN_512MB(base)) +
+ (15UL * 16UL * gpt_l1_cnt_2mb);
+
+ /* 32MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 32MB);
+
+ /* Number of 32MB blocks in 512MB */
+ unsigned int cnt = 16U;
+
+ /* Set the first L1 entry to 2MB Contiguous descriptor */
+ gpi_info->gpt_l1_addr[GPT_L1_INDEX(ALIGN_32MB(base))] = l1_cont_desc;
+
+ /*
+ * Start check from the 1st L1 entry of the last 32MB block and
+ * continue until the first non-matching to 32MB Contiguous descriptor
+ * value is found.
+ */
+ while (cnt-- != 0U) {
+ if (gpi_info->gpt_l1_addr[idx] != l1_cont_desc) {
+ /* Non-matching L1 entry found */
+ return false;
+ }
+ idx -= 16UL * gpt_l1_cnt_2mb;
+ }
+
+ return true;
+}
+
+__unused static void fuse_512mb(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* L1 entry index of the start of 512MB block */
+ unsigned long idx_512 = GPT_L1_INDEX(ALIGN_512MB(base));
+
+ /* 512MB Contiguous descriptor */
+ uint64_t l1_cont_desc = GPT_L1_CONT_DESC(l1_desc, 512MB);
+
+ VERBOSE("GPT: %s(0x%"PRIxPTR" 0x%"PRIx64")\n", __func__, base, l1_desc);
+
+ fill_desc(&gpi_info->gpt_l1_addr[idx_512], l1_cont_desc, L1_QWORDS_512MB);
+}
+
+/*
+ * Helper function to convert GPI entries in a single L1 table
+ * from Granules to Contiguous descriptor.
+ *
+ * Parameters
+ * base Base address of the region to be written
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor with all entries
+ * set to the same GPI.
+ */
+__unused static void fuse_block(uint64_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* Start with check for 2MB block */
+ if (!check_fuse_2mb(base, gpi_info, l1_desc)) {
+ /* Check for 2MB fusing failed */
+ return;
+ }
+
+#if (RME_GPT_MAX_BLOCK == 2)
+ fuse_2mb(base, gpi_info, l1_desc);
+#else
+ /* Check for 32MB block */
+ if (!check_fuse_32mb(base, gpi_info, l1_desc)) {
+ /* Check for 32MB fusing failed, fuse to 2MB */
+ fuse_2mb(base, gpi_info, l1_desc);
+ return;
+ }
+
+#if (RME_GPT_MAX_BLOCK == 32)
+ fuse_32mb(base, gpi_info, l1_desc);
+#else
+ /* Check for 512MB block */
+ if (!check_fuse_512mb(base, gpi_info, l1_desc)) {
+ /* Check for 512MB fusing failed, fuse to 32MB */
+ fuse_32mb(base, gpi_info, l1_desc);
+ return;
+ }
+
+ /* Fuse to 512MB */
+ fuse_512mb(base, gpi_info, l1_desc);
+
+#endif /* RME_GPT_MAX_BLOCK == 32 */
+#endif /* RME_GPT_MAX_BLOCK == 2 */
+}
+
+/*
+ * Helper function to convert GPI entries in a single L1 table
+ * from Contiguous to Granules descriptor. This function updates
+ * descriptor to Granules in passed 'gpt_config_t' structure as
+ * the result of shuttering.
+ *
+ * Parameters
+ * base Base address of the region to be written
+ * gpi_info Pointer to 'gpt_config_t' structure
+ * l1_desc GPT Granules descriptor set this range to.
+ */
+__unused static void shatter_block(uint64_t base, gpi_info_t *gpi_info,
+ uint64_t l1_desc)
+{
+ /* Look-up table for 2MB, 32MB and 512MB locks shattering */
+ static const gpt_shatter_func gpt_shatter_lookup[] = {
+ shatter_2mb,
+ shatter_32mb,
+ shatter_512mb
+ };
+
+ /* Look-up table for invalidation TLBs for 2MB, 32MB and 512MB blocks */
+ static const gpt_tlbi_lookup_t tlbi_lookup[] = {
+ { tlbirpalos_2m, ~(SZ_2M - 1UL) },
+ { tlbirpalos_32m, ~(SZ_32M - 1UL) },
+ { tlbirpalos_512m, ~(SZ_512M - 1UL) }
+ };
+
+ /* Get shattering level from Contig field of Contiguous descriptor */
+ unsigned long level = GPT_L1_CONT_CONTIG(gpi_info->gpt_l1_desc) - 1UL;
+
+ /* Shatter contiguous block */
+ gpt_shatter_lookup[level](base, gpi_info, l1_desc);
+
+ tlbi_lookup[level].function(base & tlbi_lookup[level].mask);
+ dsbosh();
+
+ /*
+ * Update 'gpt_config_t' structure's descriptor to Granules to reflect
+ * the shattered GPI back to caller.
+ */
+ gpi_info->gpt_l1_desc = l1_desc;
+}
+
+/*
* This function is the granule transition delegate service. When a granule
* transition request occurs it is routed to this function to have the request,
- * if valid, fulfilled following A1.1.1 Delegate of RME supplement
+ * if valid, fulfilled following A1.1.1 Delegate of RME supplement.
*
* TODO: implement support for transitioning multiple granules at once.
*
@@ -1022,9 +1698,9 @@
int gpt_delegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
{
gpi_info_t gpi_info;
- uint64_t nse;
- int res;
+ uint64_t nse, __unused l1_desc;
unsigned int target_pas;
+ int res;
/* Ensure that the tables have been set up before taking requests */
assert(gpt_config.plat_gpt_l0_base != 0UL);
@@ -1032,10 +1708,6 @@
/* Ensure that caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
- /* Delegate request can only come from REALM or SECURE */
- assert(src_sec_state == SMC_FROM_REALM ||
- src_sec_state == SMC_FROM_SECURE);
-
/* See if this is a single or a range of granule transition */
if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
return -EINVAL;
@@ -1060,70 +1732,80 @@
return -EINVAL;
}
+ /* Delegate request can only come from REALM or SECURE */
+ if ((src_sec_state != SMC_FROM_REALM) &&
+ (src_sec_state != SMC_FROM_SECURE)) {
+ VERBOSE("GPT: Invalid caller security state 0x%x\n",
+ src_sec_state);
+ return -EINVAL;
+ }
+
- target_pas = GPT_GPI_REALM;
- if (src_sec_state == SMC_FROM_SECURE) {
+ if (src_sec_state == SMC_FROM_REALM) {
+ target_pas = GPT_GPI_REALM;
+ nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
+ l1_desc = GPT_L1_REALM_DESC;
+ } else {
target_pas = GPT_GPI_SECURE;
+ nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
+ l1_desc = GPT_L1_SECURE_DESC;
}
- /*
- * Access to L1 tables is controlled by a global lock to ensure
- * that no more than one CPU is allowed to make changes at any
- * given time.
- */
- spin_lock(&gpt_lock);
res = get_gpi_params(base, &gpi_info);
if (res != 0) {
- spin_unlock(&gpt_lock);
return res;
}
+ /*
+ * Access to GPT is controlled by a lock to ensure that no more
+ * than one CPU is allowed to make changes at any given time.
+ */
+ GPT_LOCK;
+ read_gpi(&gpi_info);
+
/* Check that the current address is in NS state */
if (gpi_info.gpi != GPT_GPI_NS) {
VERBOSE("GPT: Only Granule in NS state can be delegated.\n");
VERBOSE(" Caller: %u, Current GPI: %u\n", src_sec_state,
gpi_info.gpi);
- spin_unlock(&gpt_lock);
+ GPT_UNLOCK;
return -EPERM;
}
- if (src_sec_state == SMC_FROM_SECURE) {
- nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
- } else {
- nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
+#if (RME_GPT_MAX_BLOCK != 0)
+ /* Check for Contiguous descriptor */
+ if ((gpi_info.gpt_l1_desc & GPT_L1_TYPE_CONT_DESC_MASK) ==
+ GPT_L1_TYPE_CONT_DESC) {
+ shatter_block(base, &gpi_info, GPT_L1_NS_DESC);
}
-
+#endif
/*
* In order to maintain mutual distrust between Realm and Secure
* states, remove any data speculatively fetched into the target
- * physical address space. Issue DC CIPAPA over address range.
+ * physical address space.
+ * Issue DC CIPAPA or DC_CIGDPAPA on implementations with FEAT_MTE2.
*/
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- }
+ flush_page_to_popa(base | nse);
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
gpi_info.gpi_shift, gpi_info.idx, target_pas);
- dsboshst();
- gpt_tlbi_by_pa_ll(base, GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- dsbosh();
+ /* Ensure that all agents observe the new configuration */
+ tlbi_page_dsbosh(base);
nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
+ /* Ensure that the scrubbed data have made it past the PoPA */
+ flush_page_to_popa(base | nse);
+
+#if (RME_GPT_MAX_BLOCK != 0)
+ if (gpi_info.gpt_l1_desc == l1_desc) {
+ /* Try to fuse */
+ fuse_block(base, &gpi_info, l1_desc);
}
+#endif
- /* Unlock access to the L1 tables */
- spin_unlock(&gpt_lock);
+ /* Unlock the lock to GPT */
+ GPT_UNLOCK;
/*
* The isb() will be done as part of context
@@ -1155,7 +1837,7 @@
int gpt_undelegate_pas(uint64_t base, size_t size, unsigned int src_sec_state)
{
gpi_info_t gpi_info;
- uint64_t nse;
+ uint64_t nse, __unused l1_desc;
int res;
/* Ensure that the tables have been set up before taking requests */
@@ -1164,10 +1846,6 @@
/* Ensure that MMU and caches are enabled */
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0UL);
- /* Delegate request can only come from REALM or SECURE */
- assert(src_sec_state == SMC_FROM_REALM ||
- src_sec_state == SMC_FROM_SECURE);
-
/* See if this is a single or a range of granule transition */
if (size != GPT_PGS_ACTUAL_SIZE(gpt_config.p)) {
return -EINVAL;
@@ -1192,84 +1870,80 @@
return -EINVAL;
}
- /*
- * Access to L1 tables is controlled by a global lock to ensure
- * that no more than one CPU is allowed to make changes at any
- * given time.
- */
- spin_lock(&gpt_lock);
-
res = get_gpi_params(base, &gpi_info);
if (res != 0) {
- spin_unlock(&gpt_lock);
return res;
}
+ /*
+ * Access to GPT is controlled by a lock to ensure that no more
+ * than one CPU is allowed to make changes at any given time.
+ */
+ GPT_LOCK;
+ read_gpi(&gpi_info);
+
/* Check that the current address is in the delegated state */
- if ((src_sec_state == SMC_FROM_REALM &&
- gpi_info.gpi != GPT_GPI_REALM) ||
- (src_sec_state == SMC_FROM_SECURE &&
- gpi_info.gpi != GPT_GPI_SECURE)) {
- VERBOSE("GPT: Only Granule in REALM or SECURE state can be undelegated.\n");
+ if ((src_sec_state == SMC_FROM_REALM) &&
+ (gpi_info.gpi == GPT_GPI_REALM)) {
+ l1_desc = GPT_L1_REALM_DESC;
+ nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
+ } else if ((src_sec_state == SMC_FROM_SECURE) &&
+ (gpi_info.gpi == GPT_GPI_SECURE)) {
+ l1_desc = GPT_L1_SECURE_DESC;
+ nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
+ } else {
+ VERBOSE("GPT: Only Granule in REALM or SECURE state can be undelegated\n");
VERBOSE(" Caller: %u Current GPI: %u\n", src_sec_state,
gpi_info.gpi);
- spin_unlock(&gpt_lock);
+ GPT_UNLOCK;
return -EPERM;
}
-
- /* In order to maintain mutual distrust between Realm and Secure
+#if (RME_GPT_MAX_BLOCK != 0)
+ /* Check for Contiguous descriptor */
+ if ((gpi_info.gpt_l1_desc & GPT_L1_TYPE_CONT_DESC_MASK) ==
+ GPT_L1_TYPE_CONT_DESC) {
+ shatter_block(base, &gpi_info, l1_desc);
+ }
+#endif
+ /*
+ * In order to maintain mutual distrust between Realm and Secure
* states, remove access now, in order to guarantee that writes
* to the currently-accessible physical address space will not
* later become observable.
*/
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
gpi_info.gpi_shift, gpi_info.idx, GPT_GPI_NO_ACCESS);
- dsboshst();
- gpt_tlbi_by_pa_ll(base, GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- dsbosh();
-
- if (src_sec_state == SMC_FROM_SECURE) {
- nse = (uint64_t)GPT_NSE_SECURE << GPT_NSE_SHIFT;
- } else {
- nse = (uint64_t)GPT_NSE_REALM << GPT_NSE_SHIFT;
- }
+ /* Ensure that all agents observe the new NO_ACCESS configuration */
+ tlbi_page_dsbosh(base);
- /* Ensure that the scrubbed data has made it past the PoPA */
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- }
+ /* Ensure that the scrubbed data have made it past the PoPA */
+ flush_page_to_popa(base | nse);
/*
- * Remove any data loaded speculatively
- * in NS space from before the scrubbing
+ * Remove any data loaded speculatively in NS space from before
+ * the scrubbing.
*/
nse = (uint64_t)GPT_NSE_NS << GPT_NSE_SHIFT;
- if (is_feat_mte2_supported()) {
- flush_dcache_to_popa_range_mte2(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- } else {
- flush_dcache_to_popa_range(nse | base,
- GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- }
+ flush_page_to_popa(base | nse);
- /* Clear existing GPI encoding and transition granule. */
+ /* Clear existing GPI encoding and transition granule */
write_gpt(&gpi_info.gpt_l1_desc, gpi_info.gpt_l1_addr,
gpi_info.gpi_shift, gpi_info.idx, GPT_GPI_NS);
- dsboshst();
/* Ensure that all agents observe the new NS configuration */
- gpt_tlbi_by_pa_ll(base, GPT_PGS_ACTUAL_SIZE(gpt_config.p));
- dsbosh();
+ tlbi_page_dsbosh(base);
- /* Unlock access to the L1 tables. */
- spin_unlock(&gpt_lock);
+#if (RME_GPT_MAX_BLOCK != 0)
+ if (gpi_info.gpt_l1_desc == GPT_L1_NS_DESC) {
+ /* Try to fuse */
+ fuse_block(base, &gpi_info, GPT_L1_NS_DESC);
+ }
+#endif
+ /* Unlock the lock to GPT */
+ GPT_UNLOCK;
/*
* The isb() will be done as part of context
diff --git a/lib/gpt_rme/gpt_rme.mk b/lib/gpt_rme/gpt_rme.mk
index 60176f4..7d6b61f 100644
--- a/lib/gpt_rme/gpt_rme.mk
+++ b/lib/gpt_rme/gpt_rme.mk
@@ -1,8 +1,22 @@
#
-# Copyright (c) 2021, Arm Limited. All rights reserved.
+# Copyright (c) 2021-2024, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
+# Process RME_GPT_BITLOCK_BLOCK value
+ifeq ($(filter 0 1 2 4 8 16 32 64 128 256 512, ${RME_GPT_BITLOCK_BLOCK}),)
+ $(error "Invalid value for RME_GPT_BITLOCK_BLOCK: ${RME_GPT_BITLOCK_BLOCK}")
+endif
+
+ifeq (${RME_GPT_BITLOCK_BLOCK},0)
+ $(warning "GPT library uses global spinlock")
+endif
+
+# Process RME_GPT_MAX_BLOCK value
+ifeq ($(filter 0 2 32 512, ${RME_GPT_MAX_BLOCK}),)
+ $(error "Invalid value for RME_GPT_MAX_BLOCK: ${RME_GPT_MAX_BLOCK}")
+endif
+
GPT_LIB_SRCS := $(addprefix lib/gpt_rme/, \
gpt_rme.c)
diff --git a/lib/gpt_rme/gpt_rme_private.h b/lib/gpt_rme/gpt_rme_private.h
index b2a5dae..31dad20 100644
--- a/lib/gpt_rme/gpt_rme_private.h
+++ b/lib/gpt_rme/gpt_rme_private.h
@@ -9,6 +9,7 @@
#include <arch.h>
#include <lib/gpt_rme/gpt_rme.h>
+#include <lib/spinlock.h>
#include <lib/utils_def.h>
/******************************************************************************/
@@ -19,7 +20,7 @@
#define GPT_L0_TYPE_MASK UL(0xF)
#define GPT_L0_TYPE_SHIFT U(0)
-/* For now, we don't support contiguous descriptors, only table and block */
+/* GPT level 0 table and block descriptors */
#define GPT_L0_TYPE_TBL_DESC UL(3)
#define GPT_L0_TYPE_BLK_DESC UL(1)
@@ -29,29 +30,63 @@
#define GPT_L0_BLK_DESC_GPI_MASK UL(0xF)
#define GPT_L0_BLK_DESC_GPI_SHIFT U(4)
-/* GPT level 1 descriptor bit definitions */
+/* GPT level 1 Contiguous descriptor */
+#define GPT_L1_TYPE_CONT_DESC_MASK UL(0xF)
+#define GPT_L1_TYPE_CONT_DESC UL(1)
+
+/* GPT level 1 Contiguous descriptor definitions */
+#define GPT_L1_CONTIG_2MB UL(1)
+#define GPT_L1_CONTIG_32MB UL(2)
+#define GPT_L1_CONTIG_512MB UL(3)
+
+#define GPT_L1_CONT_DESC_GPI_SHIFT U(4)
+#define GPT_L1_CONT_DESC_GPI_MASK UL(0xF)
+#define GPT_L1_CONT_DESC_CONTIG_SHIFT U(8)
+#define GPT_L1_CONT_DESC_CONTIG_MASK UL(3)
+
+/* GPT level 1 Granules descriptor bit definitions */
#define GPT_L1_GRAN_DESC_GPI_MASK UL(0xF)
+/* L1 Contiguous descriptors templates */
+#define GPT_L1_CONT_DESC_2MB \
+ (GPT_L1_TYPE_CONT_DESC | \
+ (GPT_L1_CONTIG_2MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
+#define GPT_L1_CONT_DESC_32MB \
+ (GPT_L1_TYPE_CONT_DESC | \
+ (GPT_L1_CONTIG_32MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
+#define GPT_L1_CONT_DESC_512MB \
+ (GPT_L1_TYPE_CONT_DESC | \
+ (GPT_L1_CONTIG_512MB << GPT_L1_CONT_DESC_CONTIG_SHIFT))
+
+/* Create L1 Contiguous descriptor from GPI and template */
+#define GPT_L1_GPI_CONT_DESC(_gpi, _desc) \
+ ((_desc) | ((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT))
+
+/* Create L1 Contiguous descriptor from Granules descriptor and size */
+#define GPT_L1_CONT_DESC(_desc, _size) \
+ (GPT_L1_CONT_DESC_##_size | \
+ (((_desc) & GPT_L1_GRAN_DESC_GPI_MASK) << \
+ GPT_L1_CONT_DESC_GPI_SHIFT))
+
+/* Create L1 Contiguous descriptor from GPI and size */
+#define GPT_L1_CONT_DESC_SIZE(_gpi, _size) \
+ (GPT_L1_CONT_DESC_##_size | \
+ (((uint64_t)(_gpi) << GPT_L1_CONT_DESC_GPI_SHIFT))
+
+#define GPT_L1_GPI_BYTE(_gpi) (uint64_t)((_gpi) | ((_gpi) << 4))
+#define GPT_L1_GPI_HALF(_gpi) (GPT_L1_GPI_BYTE(_gpi) | (GPT_L1_GPI_BYTE(_gpi) << 8))
+#define GPT_L1_GPI_WORD(_gpi) (GPT_L1_GPI_HALF(_gpi) | (GPT_L1_GPI_HALF(_gpi) << 16))
+
/*
- * This macro fills out every GPI entry in a granules descriptor to the same
- * value.
+ * This macro generates a Granules descriptor
+ * with the same value for every GPI entry.
*/
-#define GPT_BUILD_L1_DESC(_gpi) (((uint64_t)(_gpi) << 4*0) | \
- ((uint64_t)(_gpi) << 4*1) | \
- ((uint64_t)(_gpi) << 4*2) | \
- ((uint64_t)(_gpi) << 4*3) | \
- ((uint64_t)(_gpi) << 4*4) | \
- ((uint64_t)(_gpi) << 4*5) | \
- ((uint64_t)(_gpi) << 4*6) | \
- ((uint64_t)(_gpi) << 4*7) | \
- ((uint64_t)(_gpi) << 4*8) | \
- ((uint64_t)(_gpi) << 4*9) | \
- ((uint64_t)(_gpi) << 4*10) | \
- ((uint64_t)(_gpi) << 4*11) | \
- ((uint64_t)(_gpi) << 4*12) | \
- ((uint64_t)(_gpi) << 4*13) | \
- ((uint64_t)(_gpi) << 4*14) | \
- ((uint64_t)(_gpi) << 4*15))
+#define GPT_BUILD_L1_DESC(_gpi) (GPT_L1_GPI_WORD(_gpi) | (GPT_L1_GPI_WORD(_gpi) << 32))
+
+#define GPT_L1_SECURE_DESC GPT_BUILD_L1_DESC(GPT_GPI_SECURE)
+#define GPT_L1_NS_DESC GPT_BUILD_L1_DESC(GPT_GPI_NS)
+#define GPT_L1_REALM_DESC GPT_BUILD_L1_DESC(GPT_GPI_REALM)
+#define GPT_L1_ANY_DESC GPT_BUILD_L1_DESC(GPT_GPI_ANY)
/******************************************************************************/
/* GPT platform configuration */
@@ -106,17 +141,46 @@
PGS_64KB_P = 16U
} gpt_p_val_e;
+#define LOCK_SIZE sizeof(((bitlock_t *)NULL)->lock)
+#define LOCK_TYPE typeof(((bitlock_t *)NULL)->lock)
+#define LOCK_BITS (LOCK_SIZE * 8U)
+
/*
- * Internal structure to retrieve the values from get_gpi_info();
+ * Internal structure to retrieve the values from get_gpi_params();
*/
-typedef struct gpi_info {
+typedef struct {
uint64_t gpt_l1_desc;
uint64_t *gpt_l1_addr;
unsigned int idx;
unsigned int gpi_shift;
unsigned int gpi;
+#if (RME_GPT_BITLOCK_BLOCK != 0)
+ bitlock_t *lock;
+ LOCK_TYPE mask;
+#endif
} gpi_info_t;
+/*
+ * Look up structure for contiguous blocks and descriptors
+ */
+typedef struct {
+ size_t size;
+ unsigned int desc;
+} gpt_fill_lookup_t;
+
+typedef void (*gpt_shatter_func)(uintptr_t base, const gpi_info_t *gpi_info,
+ uint64_t l1_desc);
+typedef void (*gpt_tlbi_func)(uintptr_t base);
+
+/*
+ * Look-up structure for
+ * invalidating TLBs of GPT entries by Physical address, last level.
+ */
+typedef struct {
+ gpt_tlbi_func function;
+ size_t mask;
+} gpt_tlbi_lookup_t;
+
/* Max valid value for PGS */
#define GPT_PGS_MAX (2U)
@@ -136,8 +200,8 @@
* special case we'll get a negative width value which does not make sense and
* would cause problems.
*/
-#define GPT_L0_IDX_WIDTH(_t) (((_t) > GPT_S_VAL) ? \
- ((_t) - GPT_S_VAL) : (0U))
+#define GPT_L0_IDX_WIDTH(_t) (((unsigned int)(_t) > GPT_S_VAL) ? \
+ ((unsigned int)(_t) - GPT_S_VAL) : (0U))
/* Bit shift for the L0 index field in a PA */
#define GPT_L0_IDX_SHIFT (GPT_S_VAL)
@@ -173,10 +237,11 @@
* the L0 index field above since all valid combinations of PGS (p) and L0GPTSZ
* (s) will result in a positive width value.
*/
-#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - ((_p) + 3U))
+#define GPT_L1_IDX_WIDTH(_p) ((GPT_S_VAL - 1U) - \
+ ((unsigned int)(_p) + 3U))
/* Bit shift for the L1 index field */
-#define GPT_L1_IDX_SHIFT(_p) ((_p) + 4U)
+#define GPT_L1_IDX_SHIFT(_p) ((unsigned int)(_p) + 4U)
/*
* Mask for the L1 index field, must be shifted.
@@ -196,7 +261,10 @@
#define GPT_L1_GPI_IDX_MASK (0xF)
/* Total number of entries in each L1 table */
-#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1U)
+#define GPT_L1_ENTRY_COUNT(_p) ((GPT_L1_IDX_MASK(_p)) + 1UL)
+
+/* Number of L1 entries in 2MB block */
+#define GPT_L1_ENTRY_COUNT_2MB(_p) (SZ_2M >> GPT_L1_IDX_SHIFT(_p))
/* Total size in bytes of each L1 table */
#define GPT_L1_TABLE_SIZE(_p) ((GPT_L1_ENTRY_COUNT(_p)) << 3U)
@@ -206,10 +274,13 @@
/******************************************************************************/
/* Protected space actual size in bytes */
-#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (_t))
+#define GPT_PPS_ACTUAL_SIZE(_t) (1UL << (unsigned int)(_t))
/* Granule actual size in bytes */
-#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (_p))
+#define GPT_PGS_ACTUAL_SIZE(_p) (1UL << (unsigned int)(_p))
+
+/* Number of granules in 2MB block */
+#define GPT_PGS_COUNT_2MB(_p) (1UL << (21U - (unsigned int)(_p)))
/* L0 GPT region size in bytes */
#define GPT_L0GPTSZ_ACTUAL_SIZE (1UL << GPT_S_VAL)
@@ -221,7 +292,8 @@
* This definition is used to determine if a physical address lies on an L0
* region boundary.
*/
-#define GPT_IS_L0_ALIGNED(_pa) (((_pa) & (GPT_L0_REGION_SIZE - U(1))) == U(0))
+#define GPT_IS_L0_ALIGNED(_pa) \
+ (((_pa) & (GPT_L0_REGION_SIZE - UL(1))) == UL(0))
/* Get the type field from an L0 descriptor */
#define GPT_L0_TYPE(_desc) (((_desc) >> GPT_L0_TYPE_SHIFT) & \
@@ -246,16 +318,43 @@
(GPT_L0_TBL_DESC_L1ADDR_MASK << \
GPT_L0_TBL_DESC_L1ADDR_SHIFT))))
+/* Get the GPI from L1 Contiguous descriptor */
+#define GPT_L1_CONT_GPI(_desc) \
+ (((_desc) >> GPT_L1_CONT_DESC_GPI_SHIFT) & GPT_L1_CONT_DESC_GPI_MASK)
+
+/* Get the GPI from L1 Granules descriptor */
+#define GPT_L1_GRAN_GPI(_desc) ((_desc) & GPT_L1_GRAN_DESC_GPI_MASK)
+
+/* Get the Contig from L1 Contiguous descriptor */
+#define GPT_L1_CONT_CONTIG(_desc) \
+ (((_desc) >> GPT_L1_CONT_DESC_CONTIG_SHIFT) & \
+ GPT_L1_CONT_DESC_CONTIG_MASK)
+
/* Get the index into the L1 table from a physical address */
-#define GPT_L1_IDX(_p, _pa) (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & \
- GPT_L1_IDX_MASK(_p))
+#define GPT_L1_IDX(_p, _pa) \
+ (((_pa) >> GPT_L1_IDX_SHIFT(_p)) & GPT_L1_IDX_MASK(_p))
/* Get the index of the GPI within an L1 table entry from a physical address */
-#define GPT_L1_GPI_IDX(_p, _pa) (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & \
- GPT_L1_GPI_IDX_MASK)
+#define GPT_L1_GPI_IDX(_p, _pa) \
+ (((_pa) >> GPT_L1_GPI_IDX_SHIFT(_p)) & GPT_L1_GPI_IDX_MASK)
/* Determine if an address is granule-aligned */
-#define GPT_IS_L1_ALIGNED(_p, _pa) (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - U(1))) \
- == U(0))
+#define GPT_IS_L1_ALIGNED(_p, _pa) \
+ (((_pa) & (GPT_PGS_ACTUAL_SIZE(_p) - UL(1))) == UL(0))
+
+/* Get aligned addresses */
+#define ALIGN_2MB(_addr) ((_addr) & ~(SZ_2M - 1UL))
+#define ALIGN_32MB(_addr) ((_addr) & ~(SZ_32M - 1UL))
+#define ALIGN_512MB(_addr) ((_addr) & ~(SZ_512M - 1UL))
+
+/* Determine if region is contiguous */
+#define GPT_REGION_IS_CONT(_len, _addr, _size) \
+ (((_len) >= (_size)) && (((_addr) & ((_size) - UL(1))) == UL(0)))
+
+/* Get 32MB block number in 512MB block: 0-15 */
+#define GET_32MB_NUM(_addr) ((_addr >> 25) & 0xF)
+
+/* Get 2MB block number in 32MB block: 0-15 */
+#define GET_2MB_NUM(_addr) ((_addr >> 21) & 0xF)
#endif /* GPT_RME_PRIVATE_H */
diff --git a/lib/libfdt/libfdt.mk b/lib/libfdt/libfdt.mk
index 812057d..c7f5404 100644
--- a/lib/libfdt/libfdt.mk
+++ b/lib/libfdt/libfdt.mk
@@ -1,19 +1,23 @@
#
-# Copyright (c) 2016, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-LIBFDT_SRCS := $(addprefix lib/libfdt/, \
- fdt.c \
- fdt_addresses.c \
- fdt_empty_tree.c \
- fdt_ro.c \
- fdt_rw.c \
- fdt_strerror.c \
- fdt_sw.c \
- fdt_wip.c) \
+ifndef libfdt-mk
+ libfdt-mk := 1
-INCLUDES += -Iinclude/lib/libfdt
+ LIBFDT_SRCS := $(addprefix lib/libfdt/, \
+ fdt.c \
+ fdt_addresses.c \
+ fdt_empty_tree.c \
+ fdt_ro.c \
+ fdt_rw.c \
+ fdt_strerror.c \
+ fdt_sw.c \
+ fdt_wip.c)
+
+ INCLUDES += -Iinclude/lib/libfdt
-$(eval $(call MAKE_LIB,fdt))
+ $(eval $(call MAKE_LIB,fdt))
+endif
diff --git a/lib/romlib/Makefile b/lib/romlib/Makefile
index 62cbf3e..1293f06 100644
--- a/lib/romlib/Makefile
+++ b/lib/romlib/Makefile
@@ -4,7 +4,11 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-toolchains := aarch64
+ifeq ($(filter-out clean,$(or $(MAKECMDGOALS),all)),)
+ toolchains :=
+else
+ toolchains := aarch64
+endif
include ../../make_helpers/toolchain.mk
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 2685195..a5c78ae 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -139,6 +139,12 @@
# For Chain of Trust
GENERATE_COT := 0
+# Default number of 512 blocks per bitlock
+RME_GPT_BITLOCK_BLOCK := 1
+
+# Default maximum size of GPT contiguous block
+RME_GPT_MAX_BLOCK := 2
+
# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
# default, they are for Secure EL1.
GICV2_G0_FOR_EL3 := 0
diff --git a/make_helpers/march.mk b/make_helpers/march.mk
index 25bb936..8e73116 100644
--- a/make_helpers/march.mk
+++ b/make_helpers/march.mk
@@ -21,7 +21,7 @@
# armv8.6-a armv8.7-a armv8.8-a armv8-r armv9-a
# [...]
#
-GCC_MARCH_OUTPUT := $(shell $($(ARCH)-cc) -march=foo -Q --help=target -v 2>&1)
+GCC_MARCH_OUTPUT := $(if $($(ARCH)-cc),$(shell $($(ARCH)-cc) -march=foo -Q --help=target -v 2>&1))
# This function is used to find the best march value supported by the given compiler.
# We try to use `GCC_MARCH_OUTPUT` which has verbose message with supported march values we filter that
diff --git a/make_helpers/toolchain.mk b/make_helpers/toolchain.mk
index 8e55619..96e43a8 100644
--- a/make_helpers/toolchain.mk
+++ b/make_helpers/toolchain.mk
@@ -8,355 +8,339 @@
# TF-A uses three toolchains:
#
# - The host toolchain (`host`) for building native tools
-# - The AArch32 toolchain (`aarch32`) for building Arm AArch32 images
+# - The AArch32 toolchain (`aarch32`) for building Arm AArch32 images
# - The AArch64 toolchain (`aarch64`) for building Arm AArch64 images
#
# In the main Makefile only one of the two Arm toolchains is enabled in any
# given build, but individual tools and libraries may need access to both.
#
-toolchains ?= host $(ARCH)
+ifndef toolchain-mk
+ toolchain-mk := $(lastword $(MAKEFILE_LIST))
-include $(dir $(lastword $(MAKEFILE_LIST)))build_env.mk
-include $(dir $(lastword $(MAKEFILE_LIST)))utilities.mk
+ toolchains ?= host $(ARCH)
-include $(addprefix $(dir $(lastword $(MAKEFILE_LIST)))toolchains/, \
- $(addsuffix .mk,$(toolchains)))
+ include $(dir $(lastword $(MAKEFILE_LIST)))build_env.mk
+ include $(dir $(lastword $(MAKEFILE_LIST)))utilities.mk
-#
-# Configure tool classes that we recognize.
-#
-# In the context of this build system, a tool class identifies a specific role
-# or type of tool in the toolchain.
-#
+ include $(addprefix $(dir $(lastword $(MAKEFILE_LIST)))toolchains/, \
+ $(addsuffix .mk,$(toolchains)))
-tool-classes := cc
-tool-class-name-cc := C compiler
+ #
+ # Configure tool classes that we recognize.
+ #
+ # In the context of this build system, a tool class identifies a
+ # specific role or type of tool in the toolchain.
+ #
-tool-classes += cpp
-tool-class-name-cpp := C preprocessor
+ tool-classes := cc
+ tool-class-name-cc := C compiler
-tool-classes += as
-tool-class-name-as := assembler
+ tool-classes += cpp
+ tool-class-name-cpp := C preprocessor
-tool-classes += ld
-tool-class-name-ld := linker
+ tool-classes += as
+ tool-class-name-as := assembler
-tool-classes += oc
-tool-class-name-oc := object copier
+ tool-classes += ld
+ tool-class-name-ld := linker
-tool-classes += od
-tool-class-name-od := object dumper
+ tool-classes += oc
+ tool-class-name-oc := object copier
-tool-classes += ar
-tool-class-name-ar := archiver
+ tool-classes += od
+ tool-class-name-od := object dumper
-tool-classes += dtc
-tool-class-name-dtc := device tree compiler
+ tool-classes += ar
+ tool-class-name-ar := archiver
-#
-# Configure tools that we recognize.
-#
-# Here we declare the list of specific toolchain tools that we know how to
-# interact with. We don't organize these into tool classes yet - that happens
-# further down.
-#
+ tool-classes += dtc
+ tool-class-name-dtc := device tree compiler
-# Arm® Compiler for Embedded
-tools := arm-clang
-tool-name-arm-clang := Arm® Compiler for Embedded `armclang`
+ #
+ # Configure tools that we recognize.
+ #
+ # Here we declare the list of specific toolchain tools that we know how
+ # to interact with. We don't organize these into tool classes yet - that
+ # happens further down.
+ #
-tools += arm-link
-tool-name-arm-link := Arm® Compiler for Embedded `armlink`
+ # Arm® Compiler for Embedded
+ tools := arm-clang
+ tool-name-arm-clang := Arm® Compiler for Embedded `armclang`
-tools += arm-ar
-tool-name-arm-ar := Arm® Compiler for Embedded `armar`
+ tools += arm-link
+ tool-name-arm-link := Arm® Compiler for Embedded `armlink`
-tools += arm-fromelf
-tool-name-arm-fromelf := Arm® Compiler for Embedded `fromelf`
+ tools += arm-ar
+ tool-name-arm-ar := Arm® Compiler for Embedded `armar`
-# LLVM Project
-tools += llvm-clang
-tool-name-llvm-clang := LLVM Clang (`clang`)
+ tools += arm-fromelf
+ tool-name-arm-fromelf := Arm® Compiler for Embedded `fromelf`
-tools += llvm-lld
-tool-name-llvm-lld := LLVM LLD (`lld`)
+ # LLVM Project
+ tools += llvm-clang
+ tool-name-llvm-clang := LLVM Clang (`clang`)
-tools += llvm-objcopy
-tool-name-llvm-objcopy := LLVM `llvm-objcopy`
+ tools += llvm-lld
+ tool-name-llvm-lld := LLVM LLD (`lld`)
-tools += llvm-objdump
-tool-name-llvm-objdump := LLVM `llvm-objdump`
+ tools += llvm-objcopy
+ tool-name-llvm-objcopy := LLVM `llvm-objcopy`
-tools += llvm-ar
-tool-name-llvm-ar := LLVM `llvm-ar`
+ tools += llvm-objdump
+ tool-name-llvm-objdump := LLVM `llvm-objdump`
-# GNU Compiler Collection & GNU Binary Utilities
-tools += gnu-gcc
-tool-name-gnu-gcc := GNU GCC (`gcc`)
+ tools += llvm-ar
+ tool-name-llvm-ar := LLVM `llvm-ar`
-tools += gnu-ld
-tool-name-gnu-ld := GNU LD (`ld.bfd`)
+ # GNU Compiler Collection & GNU Binary Utilities
+ tools += gnu-gcc
+ tool-name-gnu-gcc := GNU GCC (`gcc`)
-tools += gnu-objcopy
-tool-name-gnu-objcopy := GNU `objcopy`
+ tools += gnu-ld
+ tool-name-gnu-ld := GNU LD (`ld.bfd`)
-tools += gnu-objdump
-tool-name-gnu-objdump := GNU `objdump`
+ tools += gnu-objcopy
+ tool-name-gnu-objcopy := GNU `objcopy`
-tools += gnu-ar
-tool-name-gnu-ar := GNU `ar`
+ tools += gnu-objdump
+ tool-name-gnu-objdump := GNU `objdump`
-# Other tools
-tools += generic-dtc
-tool-name-generic-dtc := Device Tree Compiler (`dtc`)
+ tools += gnu-ar
+ tool-name-gnu-ar := GNU `ar`
-#
-# Assign tools to tool classes.
-#
-# Multifunctional tools, i.e. tools which can perform multiple roles in a
-# toolchain, may be specified in multiple tool class lists. For example, a C
-# compiler which can also perform the role of a linker may be placed in both
-# `tools-cc` and `tools-ld`.
-#
+ # Other tools
+ tools += generic-dtc
+ tool-name-generic-dtc := Device Tree Compiler (`dtc`)
-# C-related tools
-tools-cc := arm-clang llvm-clang gnu-gcc # C compilers
-tools-cpp := arm-clang llvm-clang gnu-gcc # C preprocessors
+ #
+ # Assign tools to tool classes.
+ #
+ # Multifunctional tools, i.e. tools which can perform multiple roles in
+ # a toolchain, may be specified in multiple tool class lists. For
+ # example, a C compiler which can also perform the role of a linker may
+ # be placed in both `tools-cc` and `tools-ld`.
+ #
-# Assembly-related tools
-tools-as := arm-clang llvm-clang gnu-gcc # Assemblers
+ # C-related tools
+ tools-cc := arm-clang llvm-clang gnu-gcc # C compilers
+ tools-cpp := arm-clang llvm-clang gnu-gcc # C preprocessors
-# Linking and object-handling tools
-tools-ld := arm-clang arm-link llvm-clang llvm-lld gnu-gcc gnu-ld # Linkers
-tools-oc := arm-fromelf llvm-objcopy gnu-objcopy # Object copiers
-tools-od := arm-fromelf llvm-objdump gnu-objdump # Object dumpers
-tools-ar := arm-ar llvm-ar gnu-ar # Archivers
+ # Assembly-related tools
+ tools-as := arm-clang llvm-clang gnu-gcc # Assemblers
-# Other tools
-tools-dtc := generic-dtc # Device tree compilers
+ # Linking and object-handling tools
+ tools-ld := arm-clang arm-link llvm-clang llvm-lld gnu-gcc gnu-ld # Linkers
+ tools-oc := arm-fromelf llvm-objcopy gnu-objcopy # Object copiers
+ tools-od := arm-fromelf llvm-objdump gnu-objdump # Object dumpers
+ tools-ar := arm-ar llvm-ar gnu-ar # Archivers
-define check-tool-class-tools
- $(eval tool-class := $(1))
+ # Other tools
+ tools-dtc := generic-dtc # Device tree compilers
- ifndef tools-$(tool-class)
- $$(error no tools registered to handle tool class `$(tool-class)`)
- endif
-endef
+ define check-tool-class-tools
+ $(eval tool-class := $(1))
-$(foreach tool-class,$(tool-classes), \
- $(eval $(call check-tool-class-tools,$(tool-class))))
-
-#
-# Default tools for each toolchain.
-#
-# Toolchains can specify a default path to any given tool with a tool class.
-# These values are used in the absence of user-specified values, and are
-# configured by the makefile for each toolchain using variables of the form:
-#
-# - $(toolchain)-$(tool-class)-default
-#
-# For example, the default C compiler for the AArch32 and AArch64 toolchains
-# could be configured with:
-#
-# - aarch32-cc-default
-# - aarch64-cc-default
-#
-
-define check-toolchain-tool-class-default
- $(eval toolchain := $(1))
- $(eval tool-class := $(2))
-
- ifndef $(toolchain)-$(tool-class)-default
- $$(error no default value specified for tool class `$(tool-class)` of toolchain `$(toolchain)`)
- endif
-endef
-
-define check-toolchain-tool-class-defaults
- $(eval toolchain := $(1))
+ ifndef tools-$(tool-class)
+ $$(error no tools registered to handle tool class `$(tool-class)`)
+ endif
+ endef
$(foreach tool-class,$(tool-classes), \
- $(eval $(call check-toolchain-tool-class-default,$(toolchain),$(tool-class))))
-endef
+ $(eval $(call check-tool-class-tools,$(tool-class))))
-$(foreach toolchain,$(toolchains), \
- $(eval $(call check-toolchain-tool-class-defaults,$(toolchain))))
+ #
+ # Default tools for each toolchain.
+ #
+ # Toolchains can specify a default path to any given tool with a tool
+ # class. These values are used in the absence of user-specified values,
+ # and are configured by the makefile for each toolchain using variables
+ # of the form:
+ #
+ # - $(toolchain)-$(tool-class)-default
+ #
+ # For example, the default C compiler for the AArch32 and AArch64
+ # toolchains could be configured with:
+ #
+ # - aarch32-cc-default
+ # - aarch64-cc-default
+ #
-#
-# Helper functions to identify toolchain tools.
-#
-# The functions defined in this section return a tool identifier when given a
-# path to a binary. We generally check a help or version string to more reliably
-# identify tools than by looking at the path alone (e.g. `gcc` on macOS is
-# actually Apple Clang).
-#
-# Each tool-guessing function (`guess-tool-$(tool)`) takes a single argument
-# giving the path to the tool to guess, and returns a non-empty value if the
-# tool corresponds to the tool identifier `$(tool)`:
-#
-# $(call guess-tool-llvm-clang,aarch64-none-elf-gcc) # <empty>
-# $(call guess-tool-gnu-gcc,aarch64-none-elf-gcc) # <non-empty>
-#
-# The `guess-tool` function tries to find the corresponding tool identifier
-# for a tool given its path. It takes two arguments:
-#
-# - $(1): a list of candidate tool identifiers to check
-# - $(2): the path to the tool to identify
-#
-# If any of the guess functions corresponding to candidate tool identifiers
-# return a non-empty value then the tool identifier of the first function to do
-# so is returned:
-#
-# $(call guess-tool,gnu-gcc llvm-clang,armclang) # <empty>
-# $(call guess-tool,gnu-gcc llvm-clang,clang-14) # llvm-clang
-# $(call guess-tool,gnu-gcc llvm-clang,aarch64-none-elf-gcc-12) # gnu-gcc
-#
-# Tools are checked in the order that they appear in `tools-$(tool-class)`, and
-# the first match is returned.
-#
+ define check-toolchain-tool-class-default
+ $(eval toolchain := $(1))
+ $(eval tool-class := $(2))
-# Arm Compiler for Embedded
-guess-tool-arm-clang = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Tool: armclang")
-guess-tool-arm-link = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "Tool: armlink")
-guess-tool-arm-fromelf = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "Tool: fromelf")
-guess-tool-arm-ar = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Tool: armar")
+ ifndef $(toolchain)-$(tool-class)-default
+ $$(error no default value specified for tool class `$(tool-class)` of toolchain `$(toolchain)`)
+ endif
+ endef
-# LLVM Project
-guess-tool-llvm-clang = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "clang version")
-guess-tool-llvm-lld = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "OVERVIEW: lld")
-guess-tool-llvm-objcopy = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "llvm-objcopy tool")
-guess-tool-llvm-objdump = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "llvm object file dumper")
-guess-tool-llvm-ar = $(shell $(call escape-shell,$(1)) --help 2>&1 <$(nul) | grep -o "LLVM Archiver")
+ define check-toolchain-tool-class-defaults
+ $(eval toolchain := $(1))
-# GNU Compiler Collection & GNU Binary Utilities
-guess-tool-gnu-gcc = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "gcc version")
-guess-tool-gnu-ld = $(shell $(call escape-shell,$(1)) -v 2>&1 <$(nul) | grep -o "GNU ld")
-guess-tool-gnu-objcopy = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU objcopy")
-guess-tool-gnu-objdump = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU objdump")
-guess-tool-gnu-ar = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "GNU ar")
+ $(foreach tool-class,$(tool-classes), \
+ $(eval $(call check-toolchain-tool-class-default,$(toolchain),$(tool-class))))
+ endef
-# Other tools
-guess-tool-generic-dtc = $(shell $(call escape-shell,$(1)) --version 2>&1 <$(nul) | grep -o "Version: DTC")
+ $(foreach toolchain,$(toolchains), \
+ $(eval $(call check-toolchain-tool-class-defaults,$(toolchain))))
-guess-tool = $(firstword $(foreach candidate,$(1), \
- $(if $(call guess-tool-$(candidate),$(2)),$(candidate))))
+ #
+ # Helper functions to identify toolchain tools.
+ #
+ # The functions defined in this section return a tool identifier when
+ # given a path to a binary. We generally check a help or version string
+ # to more reliably identify tools than by looking at the path alone
+ # (e.g. `gcc` on macOS is actually Apple Clang).
+ #
+ # Each tool-guessing function (`guess-tool-$(tool)`) takes a single
+ # argument giving the path to the tool to guess, and returns a non-empty
+ # value if the tool corresponds to the tool identifier `$(tool)`:
+ #
+ # $(call guess-tool-llvm-clang,aarch64-none-elf-gcc) # <empty>
+ # $(call guess-tool-gnu-gcc,aarch64-none-elf-gcc) # <non-empty>
+ #
+ # The `guess-tool` function tries to find the corresponding tool
+ # identifier for a tool given its path. It takes two arguments:
+ #
+ # - $(1): a list of candidate tool identifiers to check
+ # - $(2): the path to the tool to identify
+ #
+ # If any of the guess functions corresponding to candidate tool
+ # identifiers return a non-empty value then the tool identifier of the
+ # first function to do so is returned:
+ #
+ # $(call guess-tool,gnu-gcc llvm-clang,armclang) # <empty>
+ # $(call guess-tool,gnu-gcc llvm-clang,clang-14) # llvm-clang
+ # $(call guess-tool,gnu-gcc llvm-clang,aarch64-none-elf-gcc-12) # gnu-gcc
+ #
+ # Tools are checked in the order that they appear in
+ # `tools-$(tool-class)`, and the first match is returned.
+ #
-#
-# Locate and identify tools belonging to each toolchain.
-#
-# Each tool class in each toolchain receives a variable of the form
-# `$(toolchain)-$(tool)` giving the associated path to the program. For example:
-#
-# - `aarch64-ld` gives the linker for the AArch64 toolchain,
-# - `aarch32-oc` gives the object copier for the AArch32 toolchain, and
-# - `host-cc` gives the C compiler for the host toolchain.
-#
-# For each of these variables, if no program path is explicitly provided by the
-# parent Makefile then the C compiler is queried (if supported) for its
-# location. This is done via the `guess-$(tool)-$(tool-class)` set of functions.
-# For example:
-#
-# - `guess-arm-clang-ld` guesses the linker via Arm Clang,
-# - `guess-llvm-clang-as` guesses the assembler via LLVM Clang, and
-# - `guess-gnu-gcc-od` guesses the object dumper via GNU GCC.
-#
-# If the C compiler cannot provide the location (or the tool class is the C
-# compiler), then it is assigned the value of the `$(toolchain)-$(tool)-default`
-# variable.
-#
+ # Arm Compiler for Embedded
+ guess-tool-arm-clang = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armclang")
+ guess-tool-arm-link = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: armlink")
+ guess-tool-arm-fromelf = $(shell $(1) --help 2>&1 <$(nul) | grep -o "Tool: fromelf")
+ guess-tool-arm-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Tool: armar")
-guess-arm-clang-cpp = $(1)
-guess-arm-clang-as = $(1)
-guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
-guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
-guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
-guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
+ # LLVM Project
+ guess-tool-llvm-clang = $(shell $(1) -v 2>&1 <$(nul) | grep -o "clang version")
+ guess-tool-llvm-lld = $(shell $(1) --help 2>&1 <$(nul) | grep -o "OVERVIEW: lld")
+ guess-tool-llvm-objcopy = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm-objcopy tool")
+ guess-tool-llvm-objdump = $(shell $(1) --help 2>&1 <$(nul) | grep -o "llvm object file dumper")
+ guess-tool-llvm-ar = $(shell $(1) --help 2>&1 <$(nul) | grep -o "LLVM Archiver")
-guess-llvm-clang-cpp = $(1)
-guess-llvm-clang-as = $(1)
-guess-llvm-clang-ld = $(shell $(call escape-shell,$(1)) --print-prog-name ld.lld 2>$(nul))
-guess-llvm-clang-oc = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-objcopy 2>$(nul))
-guess-llvm-clang-od = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-objdump 2>$(nul))
-guess-llvm-clang-ar = $(shell $(call escape-shell,$(1)) --print-prog-name llvm-ar 2>$(nul))
+ # GNU Compiler Collection & GNU Binary Utilities
+ guess-tool-gnu-gcc = $(shell $(1) -v 2>&1 <$(nul) | grep -o "gcc version")
+ guess-tool-gnu-ld = $(shell $(1) -v 2>&1 <$(nul) | grep -o "GNU ld")
+ guess-tool-gnu-objcopy = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objcopy")
+ guess-tool-gnu-objdump = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU objdump")
+ guess-tool-gnu-ar = $(shell $(1) --version 2>&1 <$(nul) | grep -o "GNU ar")
-guess-gnu-gcc-cpp = $(1)
-guess-gnu-gcc-as = $(1)
-guess-gnu-gcc-ld = $(1)
-guess-gnu-gcc-oc = $(shell $(call escape-shell,$(1)) --print-prog-name objcopy 2>$(nul))
-guess-gnu-gcc-od = $(shell $(call escape-shell,$(1)) --print-prog-name objdump 2>$(nul))
-guess-gnu-gcc-ar = $(call which,$(call decompat-path,$(patsubst %$(call file-name,$(1)),%$(subst gcc,gcc-ar,$(call file-name,$(1))),$(call compat-path,$(1)))))
+ # Other tools
+ guess-tool-generic-dtc = $(shell $(1) --version 2>&1 <$(nul) | grep -o "Version: DTC")
-define warn-unrecognized-tool
- $(eval toolchain := $(1))
- $(eval tool-class := $(2))
+ guess-tool = $(firstword $(foreach candidate,$(1), \
+ $(if $(call guess-tool-$(candidate),$(2)),$(candidate))))
- $$(warning )
- $$(warning The configured $$($(toolchain)-name) $$(tool-class-name-$(tool-class)) could not be identified and may not be supported:)
- $$(warning )
- $$(warning $$(space) $$($(toolchain)-$(tool-class)))
- $$(warning )
- $$(warning The default $$($(toolchain)-name) $$(tool-class-name-$(tool-class)) is:)
- $$(warning )
- $$(warning $$(space) $$($(toolchain)-$(tool-class)-default))
- $$(warning )
- $$(warning The following tools are supported:)
- $$(warning )
+ #
+ # Locate and identify tools belonging to each toolchain.
+ #
+ # Each tool class in each toolchain receives a variable of the form
+ # `$(toolchain)-$(tool)` giving the associated path to the program. For
+ # example:
+ #
+ # - `aarch64-ld` gives the linker for the AArch64 toolchain,
+ # - `aarch32-oc` gives the object copier for the AArch32 toolchain, and
+ # - `host-cc` gives the C compiler for the host toolchain.
+ #
+ # For each of these variables, if no program path is explicitly provided
+ # by the parent Makefile then the C compiler is queried (if supported)
+ # for its location. This is done via the `guess-$(tool)-$(tool-class)`
+ # set of functions. For example:
+ #
+ # - `guess-arm-clang-ld` guesses the linker via Arm Clang,
+ # - `guess-llvm-clang-as` guesses the assembler via LLVM Clang, and
+ # - `guess-gnu-gcc-od` guesses the object dumper via GNU GCC.
+ #
+ # If the C compiler cannot provide the location (or the tool class is
+ # the C compiler), then it is assigned the value of the
+ # `$(toolchain)-$(tool)-default` variable.
+ #
- $$(foreach tool,$$(tools-$(tool-class)), \
- $$(warning $$(space) - $$(tool-name-$$(tool))))
+ guess-arm-clang-cpp = $(1)
+ guess-arm-clang-as = $(1)
+ guess-arm-clang-ld = # Fall back to `$(toolchain)-ld-default`
+ guess-arm-clang-oc = # Fall back to `$(toolchain)-oc-default`
+ guess-arm-clang-od = # Fall back to `$(toolchain)-od-default`
+ guess-arm-clang-ar = # Fall back to `$(toolchain)-ar-default`
- $$(warning )
- $$(warning The build system will treat this $$(tool-class-name-$(tool-class)) as $$(tool-name-$$($(toolchain)-$(tool-class)-id-default)).)
- $$(warning )
-endef
+ guess-llvm-clang-cpp = $(1)
+ guess-llvm-clang-as = $(1)
+ guess-llvm-clang-ld = $(shell $(1) --print-prog-name ld.lld 2>$(nul))
+ guess-llvm-clang-oc = $(shell $(1) --print-prog-name llvm-objcopy 2>$(nul))
+ guess-llvm-clang-od = $(shell $(1) --print-prog-name llvm-objdump 2>$(nul))
+ guess-llvm-clang-ar = $(shell $(1) --print-prog-name llvm-ar 2>$(nul))
-define locate-toolchain-tool-cc
- $(eval toolchain := $(1))
+ guess-gnu-gcc-cpp = $(1)
+ guess-gnu-gcc-as = $(1)
+ guess-gnu-gcc-ld = $(1)
+ guess-gnu-gcc-oc = $(shell $(1) --print-prog-name objcopy 2>$(nul))
+ guess-gnu-gcc-od = $(shell $(1) --print-prog-name objdump 2>$(nul))
+ guess-gnu-gcc-ar = $(call which,$(call decompat-path,$(patsubst %$(call file-name,$(1)),%$(subst gcc,gcc-ar,$(call file-name,$(1))),$(call compat-path,$(1)))))
- $(toolchain)-cc := $$(or $$($(toolchain)-cc),$$($(toolchain)-cc-default))
- $(toolchain)-cc-id := $$(call guess-tool,$$(tools-cc),$$($(toolchain)-cc))
+ define toolchain-warn-unrecognized
+ $$(warning )
+ $$(warning The configured $$($(1)-name) $$(tool-class-name-$(2)) could not be identified and may not be supported:)
+ $$(warning )
+ $$(warning $$(space) $$($(1)-$(2)))
+ $$(warning )
+ $$(warning The default $$($(1)-name) $$(tool-class-name-$(2)) is:)
+ $$(warning )
+ $$(warning $$(space) $$($(1)-$(2)-default))
+ $$(warning )
+ $$(warning The following tools are supported:)
+ $$(warning )
- ifndef $(toolchain)-cc-id
- $(toolchain)-cc-id := $$($(toolchain)-cc-id-default)
+ $$(foreach tool,$$(tools-$(2)), \
+ $$(warning $$(space) - $$(tool-name-$$(tool))))
- $$(eval $$(call warn-unrecognized-tool,$(toolchain),cc))
- endif
+ $$(warning )
+ $$(warning The build system will treat this $$(tool-class-name-$(2)) as $$(tool-name-$$($(1)-$(2)-id-default)).)
+ $$(warning )
+ endef
- $(toolchain)-cc-path := $$($(toolchain)-cc)
- $(toolchain)-cc := $$(call escape-shell,$$($(toolchain)-cc))
-endef
+ define toolchain-determine-tool
+ $(1)-$(2)-guess = $$(if $$(filter-out cc,$(2)),$\
+ $$(call guess-$$($(1)-cc-id)-$(2),$$($(1)-cc)))
-define locate-toolchain-tool
- $(eval toolchain := $(1))
- $(eval tool-class := $(2))
+ $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-guess))
+ $(1)-$(2) := $$(or $$($(1)-$(2)),$$($(1)-$(2)-default))
- ifndef $(toolchain)-$(tool-class)
- $(toolchain)-$(tool-class) := $$(call guess-$$($(toolchain)-cc-id)-$(tool-class),$$($(toolchain)-cc-path))
+ ifneq ($$(call which,$$($(1)-$(2))),)
+ # If we can resolve this tool to a program on the `PATH`
+ # then escape it for use in a shell, which allows us to
+ # preserve spaces.
- ifndef $(toolchain)-$(tool-class)
- $(toolchain)-$(tool-class) := $$($(toolchain)-$(tool-class)-default)
+ $(1)-$(2) := $$(call escape-shell,$$($(1)-$(2)))
endif
- endif
-
- $(toolchain)-$(tool-class)-id := $$(call guess-tool,$$(tools-$(tool-class)),$$($(toolchain)-$(tool-class)))
- ifndef $(toolchain)-$(tool-class)-id
- $(toolchain)-$(tool-class)-id := $$($(toolchain)-$(tool-class)-id-default)
+ $(1)-$(2)-id := $$(call guess-tool,$$(tools-$(2)),$$($(1)-$(2)))
- $$(eval $$(call warn-unrecognized-tool,$(toolchain),$(tool-class)))
- endif
+ ifndef $(1)-$(2)-id
+ $(1)-$(2)-id := $$($(1)-$(2)-id-default)
- $(toolchain)-$(tool-class) := $$(call escape-shell,$$($(toolchain)-$(tool-class)))
-endef
-
-define locate-toolchain
- $(eval toolchain := $(1))
-
- $$(eval $$(call locate-toolchain-tool-cc,$(toolchain)))
+ $$(eval $$(call toolchain-warn-unrecognized,$(1),$(2)))
+ endif
+ endef
- $$(foreach tool-class,$$(filter-out cc,$$(tool-classes)), \
- $$(eval $$(call locate-toolchain-tool,$(toolchain),$$(tool-class))))
-endef
+ define toolchain-determine
+ $$(foreach tool-class,$$(tool-classes), \
+ $$(eval $$(call toolchain-determine-tool,$(1),$$(tool-class))))
+ endef
-$(foreach toolchain,$(toolchains), \
- $(eval $(call locate-toolchain,$(toolchain))))
+ $(foreach toolchain,$(toolchains), \
+ $(eval $(call toolchain-determine,$(toolchain))))
+endif
diff --git a/package-lock.json b/package-lock.json
index e60c44e..a6bb905 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,12 +1,12 @@
{
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"lockfileVersion": 3,
"requires": true,
"packages": {
"": {
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"license": "BSD-3-Clause",
"devDependencies": {
"@commitlint/cli": "^19.0.0",
diff --git a/package.json b/package.json
index 7ad5c58..e4c6475 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
{
"name": "trusted-firmware-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"license": "BSD-3-Clause",
"type": "module",
"private": true,
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index 30f1760..9fba4af 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -92,8 +92,9 @@
memory@1 {
device_type = "ns-memory";
- reg = <0x00008800 0x80000000 0x0 0x7f000000>,
- <0x0 0x88000000 0x0 0x10000000>;
+ reg = <0x0 0x80000000 0x0 0x7c000000>,
+ <0x8 0x80000000 0x1 0x80000000>,
+ <0x00008800 0x80000000 0x0 0x7f000000>;
};
memory@2 {
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index c0bba30..033eb7c 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -24,7 +24,7 @@
FVP_DT_PREFIX := fvp-base-gicv3-psci
-# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
+# Size (in kilobytes) of the Trusted SRAM region to utilize when building for
# the FVP platform. This option defaults to 256.
FVP_TRUSTED_SRAM_SIZE := 256
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index f15c137..4cd514b 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2024, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -68,10 +68,6 @@
arm_console_boot_init();
#if RESET_TO_SP_MIN
- /* There are no parameters from BL2 if SP_MIN is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
-
/* Populate entry point information for BL33 */
SET_PARAM_HEAD(&bl33_image_ep_info,
PARAM_EP,
diff --git a/plat/imx/common/imx_common.c b/plat/imx/common/imx_common.c
new file mode 100644
index 0000000..01f354a
--- /dev/null
+++ b/plat/imx/common/imx_common.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024, Pengutronix, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <errno.h>
+#include <stdint.h>
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+
+#include <plat_common.h>
+
+/*
+ * This function checks if @arg0 can safely be accessed as a pointer
+ * and if it does, it fills in @bl32_info and @bl33_info with data
+ * found in @arg0.
+ *
+ * Returns 0 when @arg0 can be used as entry point info and a negative
+ * error code otherwise.
+ */
+int imx_bl31_params_parse(uintptr_t arg0, uintptr_t ocram_base,
+ uintptr_t ocram_size,
+ entry_point_info_t *bl32_info,
+ entry_point_info_t *bl33_info)
+{
+ bl_params_t *v2 = (void *)(uintptr_t)arg0;
+
+ if (arg0 & 0x3) {
+ return -EINVAL;
+ }
+
+ if (arg0 < ocram_base || arg0 >= ocram_base + ocram_size) {
+ return -EINVAL;
+ }
+
+ if (v2->h.version != PARAM_VERSION_2) {
+ return -EINVAL;
+ }
+
+ if (v2->h.type != PARAM_BL_PARAMS) {
+ return -EINVAL;
+ }
+
+ bl31_params_parse_helper(arg0, bl32_info, bl33_info);
+
+ return 0;
+}
diff --git a/plat/imx/common/include/plat_common.h b/plat/imx/common/include/plat_common.h
new file mode 100644
index 0000000..6f41222
--- /dev/null
+++ b/plat/imx/common/include/plat_common.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024, Pengutronix, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_COMMON_H
+#define PLAT_COMMON_H
+
+#include <stdint.h>
+#include <common/bl_common.h>
+
+int imx_bl31_params_parse(uintptr_t arg0, uintptr_t ocram_base,
+ uintptr_t ocram_size,
+ entry_point_info_t *bl32_info,
+ entry_point_info_t *bl33_info);
+
+#endif /* PLAT_COMMON_H */
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index bff8fb4..f6e46eb 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -30,6 +30,7 @@
#include <imx8m_ccm.h>
#include <imx8m_csu.h>
#include <imx8m_snvs.h>
+#include <plat_common.h>
#include <plat_imx8.h>
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
@@ -154,7 +155,7 @@
{
unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
- int i;
+ int i, ret;
/* Enable CSU NS access permission */
for (i = 0; i < 64; i++) {
@@ -207,6 +208,13 @@
bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
#endif
#endif
+ ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE,
+ &bl32_image_ep_info, &bl33_image_ep_info);
+ if (ret != 0) {
+ ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE,
+ &bl32_image_ep_info,
+ &bl33_image_ep_info);
+ }
#if !defined(SPD_opteed) && !defined(SPD_trusty)
enable_snvs_privileged_access();
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index 349233a..2fa6199 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -118,6 +118,8 @@
#define IMX_ROM_SIZE U(0x40000)
#define IMX_NS_OCRAM_BASE U(0x900000)
#define IMX_NS_OCRAM_SIZE U(0x20000)
+#define IMX_TCM_BASE U(0x7E0000)
+#define IMX_TCM_SIZE U(0x40000)
#define IMX_CAAM_RAM_BASE U(0x100000)
#define IMX_CAAM_RAM_SIZE U(0x10000)
#define IMX_DRAM_BASE U(0x40000000)
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 6136820..d5c553a 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -30,7 +30,8 @@
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
-BL31_SOURCES += plat/imx/common/imx8_helpers.S \
+BL31_SOURCES += common/desc_image_load.c \
+ plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/gpc_common.c \
plat/imx/imx8m/imx_hab.c \
plat/imx/imx8m/imx_aipstz.c \
@@ -46,6 +47,7 @@
plat/imx/common/imx8_topology.c \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
+ plat/imx/common/imx_common.c \
plat/imx/common/imx_uart_console.S \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/tzc/tzc380.c \
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index f9e430b..befa769 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -29,6 +29,7 @@
#include <imx8m_csu.h>
#include <imx8m_snvs.h>
#include <platform_def.h>
+#include <plat_common.h>
#include <plat_imx8.h>
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
@@ -126,7 +127,7 @@
unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
unsigned int val;
- int i;
+ int i, ret;
/* Enable CSU NS access permission */
for (i = 0; i < 64; i++) {
@@ -192,6 +193,13 @@
#endif
#endif
+ ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE,
+ &bl32_image_ep_info, &bl33_image_ep_info);
+ if (ret != 0) {
+ imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE,
+ &bl32_image_ep_info, &bl33_image_ep_info);
+ }
+
#if !defined(SPD_opteed) && !defined(SPD_trusty)
enable_snvs_privileged_access();
#endif
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index 8e7be98..569432d 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -140,6 +140,8 @@
#define OCRAM_S_SIZE U(0x8000)
#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
#define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE
+#define IMX_TCM_BASE U(0x7E0000)
+#define IMX_TCM_SIZE U(0x40000)
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 6036b6a..87b3a6f 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -25,7 +25,8 @@
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
-BL31_SOURCES += plat/imx/common/imx8_helpers.S \
+BL31_SOURCES += common/desc_image_load.c \
+ plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/gpc_common.c \
plat/imx/imx8m/imx_hab.c \
plat/imx/imx8m/imx_aipstz.c \
@@ -41,6 +42,7 @@
plat/imx/common/imx8_topology.c \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
+ plat/imx/common/imx_common.c \
plat/imx/common/imx_uart_console.S \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/tzc/tzc380.c \
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index 8e35219..ffad3d1 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -29,6 +29,7 @@
#include <imx8m_csu.h>
#include <imx8m_snvs.h>
#include <platform_def.h>
+#include <plat_common.h>
#include <plat_imx8.h>
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
@@ -156,6 +157,7 @@
static console_t console;
unsigned int val;
unsigned int i;
+ int ret;
/* Enable CSU NS access permission */
for (i = 0; i < 64; i++) {
@@ -213,6 +215,13 @@
bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
#endif
#endif
+ ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE,
+ &bl32_image_ep_info, &bl33_image_ep_info);
+ if (ret != 0) {
+ ret = imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE,
+ &bl32_image_ep_info,
+ &bl33_image_ep_info);
+ }
#if !defined(SPD_opteed) && !defined(SPD_trusty)
enable_snvs_privileged_access();
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 4a03830..84a7e00 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -172,6 +172,9 @@
#define MAX_CSU_NUM U(64)
+#define IMX_TCM_BASE U(0x7E0000)
+#define IMX_TCM_SIZE U(0x40000)
+
#define OCRAM_S_BASE U(0x00180000)
#define OCRAM_S_SIZE U(0x8000)
#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 40764b1..631dd29 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -26,7 +26,8 @@
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
-BL31_SOURCES += plat/imx/common/imx8_helpers.S \
+BL31_SOURCES += common/desc_image_load.c \
+ plat/imx/common/imx8_helpers.S \
plat/imx/imx8m/gpc_common.c \
plat/imx/imx8m/imx_hab.c \
plat/imx/imx8m/imx_aipstz.c \
@@ -42,6 +43,7 @@
plat/imx/common/imx8_topology.c \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
+ plat/imx/common/imx_common.c \
plat/imx/common/imx_uart_console.S \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/tzc/tzc380.c \
diff --git a/plat/imx/imx93/imx93_bl31_setup.c b/plat/imx/imx93/imx93_bl31_setup.c
index a7d0f65..d997e9a 100644
--- a/plat/imx/imx93/imx93_bl31_setup.c
+++ b/plat/imx/imx93/imx93_bl31_setup.c
@@ -20,6 +20,7 @@
#include <plat/common/platform.h>
#include <imx8_lpuart.h>
+#include <plat_common.h>
#include <plat_imx8.h>
#include <platform_def.h>
@@ -90,6 +91,9 @@
bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
#endif
+
+ imx_bl31_params_parse(arg0, OCRAM_BASE, OCRAM_SIZE,
+ &bl32_image_ep_info, &bl33_image_ep_info);
}
void bl31_plat_arch_setup(void)
diff --git a/plat/imx/imx93/include/platform_def.h b/plat/imx/imx93/include/platform_def.h
index 7efbf1c..f0d53cd 100644
--- a/plat/imx/imx93/include/platform_def.h
+++ b/plat/imx/imx93/include/platform_def.h
@@ -31,6 +31,9 @@
#define BL31_BASE U(0x204E0000)
#define BL31_LIMIT U(0x20520000)
+#define OCRAM_BASE U(0x20480000)
+#define OCRAM_SIZE U(0xA0000)
+
/* non-secure uboot base */
/* TODO */
#define PLAT_NS_IMAGE_OFFSET U(0x80200000)
diff --git a/plat/imx/imx93/platform.mk b/plat/imx/imx93/platform.mk
index ed7e81f..f506d8b 100644
--- a/plat/imx/imx93/platform.mk
+++ b/plat/imx/imx93/platform.mk
@@ -19,9 +19,11 @@
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
-BL31_SOURCES += plat/common/aarch64/crash_console_helpers.S \
+BL31_SOURCES += common/desc_image_load.c \
+ plat/common/aarch64/crash_console_helpers.S \
plat/imx/imx93/aarch64/plat_helpers.S \
plat/imx/imx93/plat_topology.c \
+ plat/imx/common/imx_common.c \
plat/imx/common/lpuart_console.S \
plat/imx/imx93/trdc.c \
plat/imx/imx93/pwr_ctrl.c \
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
index ef7134c..329a45e 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu.h
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu.h
@@ -18,7 +18,7 @@
#define FORBIDDEN (5)
#define SEC_R_NSEC_RW (6)
-#define LOCK (1)
+#define LOCK (1UL)
#define UNLOCK (0)
#if (EMI_MPU_DGROUP_NUM == 1)
@@ -69,6 +69,7 @@
int emi_mpu_optee_handler(uint64_t encoded_addr, uint64_t zone_size,
uint64_t zone_info);
int emi_mpu_set_protection(struct emi_region_info_t *region_info);
+int emi_mpu_clear_protection(unsigned int region);
void set_emi_mpu_regions(void);
int set_apu_emi_mpu_region(void);
#endif
diff --git a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
index 8810be3..1e732f0 100644
--- a/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
+++ b/plat/mediatek/drivers/emi_mpu/emi_mpu_common.c
@@ -39,13 +39,13 @@
}
#if ENABLE_EMI_MPU_SW_LOCK
- if (region_lock_state[region] == 1) {
+ if (region_lock_state[region] == LOCK) {
WARN("invalid region\n");
return -1;
}
if ((dgroup == 0) && ((apc >> 31) & 0x1)) {
- region_lock_state[region] = 1;
+ region_lock_state[region] = LOCK;
}
apc &= EMI_MPU_APC_SW_LOCK_MASK;
@@ -73,6 +73,50 @@
return 0;
}
+int emi_mpu_clear_protection(unsigned int region)
+{
+ unsigned int dgroup;
+
+ if (region >= EMI_MPU_REGION_NUM) {
+ WARN("invalid region number\n");
+ return -1;
+ }
+
+#if ENABLE_EMI_MPU_SW_LOCK
+ if (region_lock_state[region] == LOCK) {
+ WARN("SW:region is locked\n");
+ return -1;
+ }
+#endif
+ if (mmio_read_32(EMI_MPU_APC(region, 0)) & (LOCK << 31UL)) {
+ WARN("HW:EMI-MPU region is locked\n");
+ return -1;
+ }
+
+#if defined(SUB_EMI_MPU_BASE)
+ if (mmio_read_32(SUB_EMI_MPU_APC(region, 0)) & (LOCK << 31UL)) {
+ WARN("HW:SUB EMI-MPU region is locked\n");
+ return -1;
+ }
+#endif
+
+ for (dgroup = 0; dgroup < EMI_MPU_DGROUP_NUM; dgroup++)
+ mmio_write_32(EMI_MPU_APC(region, dgroup), 0x0);
+
+ mmio_write_32(EMI_MPU_SA(region), 0x0);
+ mmio_write_32(EMI_MPU_EA(region), 0x0);
+
+#if defined(SUB_EMI_MPU_BASE)
+ for (dgroup = 0; dgroup < EMI_MPU_DGROUP_NUM; dgroup++)
+ mmio_write_32(SUB_EMI_MPU_APC(region, dgroup), 0x0);
+
+ mmio_write_32(SUB_EMI_MPU_SA(region), 0);
+ mmio_write_32(SUB_EMI_MPU_EA(region), 0);
+#endif
+ return 0;
+}
+
+
static void dump_emi_mpu_regions(void)
{
int region, i;
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
index e8882f0..f7ed5e6 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu.c
@@ -14,11 +14,33 @@
{
struct emi_region_info_t region_info;
+ /* BL31 address */
+ region_info.start = TZRAM_BASE;
+ region_info.end = TZRAM_BASE + TZRAM_SIZE - 1;
+ region_info.region = BL31_EMI_REGION_ID;
+ SET_ACCESS_PERMISSION(region_info.apc, LOCK,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+ emi_mpu_set_protection(®ion_info);
+
+ /* BL32 address */
+ region_info.start = BL32_REGION_BASE;
+ region_info.end = BL32_REGION_BASE + BL32_REGION_SIZE - 1;
+ region_info.region = BL32_REGION_ID;
+ SET_ACCESS_PERMISSION(region_info.apc, LOCK,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, SEC_RW, SEC_RW);
+ emi_mpu_set_protection(®ion_info);
+
/* SCP core0 DRAM */
- region_info.start = 0x50000000ULL;
- region_info.end = 0x528FFFFFULL;
- region_info.region = 2;
- SET_ACCESS_PERMISSION(region_info.apc, 1,
+ region_info.start = SCP_CORE0_REGION_BASE;
+ region_info.end = SCP_CORE0_REGION_BASE + SCP_CORE0_REGION_SIZE - 1;
+ region_info.region = SCP_CORE0_REGION_ID;
+ SET_ACCESS_PERMISSION(region_info.apc, LOCK,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -26,10 +48,10 @@
emi_mpu_set_protection(®ion_info);
/* SCP core1 DRAM */
- region_info.start = 0x70000000ULL;
- region_info.end = 0x729FFFFFULL;
- region_info.region = 3;
- SET_ACCESS_PERMISSION(region_info.apc, 1,
+ region_info.start = SCP_CORE1_REGION_BASE;
+ region_info.end = SCP_CORE1_REGION_BASE + SCP_CORE1_REGION_SIZE - 1;
+ region_info.region = SCP_CORE1_REGION_ID;
+ SET_ACCESS_PERMISSION(region_info.apc, LOCK,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -37,10 +59,10 @@
emi_mpu_set_protection(®ion_info);
/* DSP protect address */
- region_info.start = 0x60000000ULL;
- region_info.end = 0x610FFFFFULL;
- region_info.region = 4;
- SET_ACCESS_PERMISSION(region_info.apc, 1,
+ region_info.start = DSP_PROTECT_REGION_BASE;
+ region_info.end = DSP_PROTECT_REGION_BASE + DSP_PROTECT_REGION_SIZE - 1;
+ region_info.region = DSP_PROTECT_REGION_ID;
+ SET_ACCESS_PERMISSION(region_info.apc, LOCK,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROTECTION,
@@ -48,10 +70,10 @@
emi_mpu_set_protection(®ion_info);
/* All default settings */
- region_info.start = 0x40000000ULL;
- region_info.end = 0x1FFFF0000ULL;
- region_info.region = 31;
- SET_ACCESS_PERMISSION(region_info.apc, 1,
+ region_info.start = DRAM_START_ADDR;
+ region_info.end = DRAM_START_ADDR + DRAM_MAX_SIZE - 1;
+ region_info.region = ALL_DEFAULT_REGION_ID;
+ SET_ACCESS_PERMISSION(region_info.apc, LOCK,
FORBIDDEN, FORBIDDEN, NO_PROTECTION, NO_PROTECTION,
NO_PROTECTION, FORBIDDEN, NO_PROTECTION, NO_PROTECTION,
NO_PROTECTION, SEC_R_NSEC_RW, NO_PROTECTION, FORBIDDEN,
@@ -65,7 +87,7 @@
region_info.start = (unsigned long long)APUSYS_SEC_BUF_PA;
region_info.end = (unsigned long long)(APUSYS_SEC_BUF_PA + APUSYS_SEC_BUF_SZ) - 1;
- region_info.region = APUSYS_SEC_BUF_EMI_REGION;
+ region_info.region = APUSYS_SEC_BUF_EMI_REGION_ID;
SET_ACCESS_PERMISSION(region_info.apc, UNLOCK,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -86,12 +108,18 @@
return ((info & 0xFFFF0000) >> MPU_PHYSICAL_ADDR_SHIFT_BITS);
}
+static inline uint32_t get_decoded_set_clear_info(uint32_t info)
+{
+ return (info & 0x0000FFFF);
+}
+
int emi_mpu_optee_handler(uint64_t encoded_addr, uint64_t zone_size,
uint64_t zone_info)
{
uint64_t phys_addr = get_decoded_phys_addr(encoded_addr);
struct emi_region_info_t region_info;
enum MPU_REQ_ORIGIN_ZONE_ID zone_id = get_decoded_zone_id(zone_info);
+ uint32_t is_set = get_decoded_set_clear_info(zone_info);
INFO("encoded_addr = 0x%lx, zone_size = 0x%lx, zone_info = 0x%lx\n",
encoded_addr, zone_size, zone_info);
@@ -101,17 +129,21 @@
return MTK_SIP_E_INVALID_PARAM;
}
- /* SVP DRAM */
- region_info.start = phys_addr;
- region_info.end = phys_addr + zone_size;
- region_info.region = 4;
- SET_ACCESS_PERMISSION(region_info.apc, 1,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
- FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+ if (is_set > 0) {
+ /* SVP DRAM */
+ region_info.start = phys_addr;
+ region_info.end = phys_addr + zone_size - 1;
+ region_info.region = SVP_DRAM_REGION_ID;
+ SET_ACCESS_PERMISSION(region_info.apc, UNLOCK,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, SEC_RW, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, SEC_RW, SEC_RW);
- emi_mpu_set_protection(®ion_info);
+ emi_mpu_set_protection(®ion_info);
+ } else { /* clear region protection */
+ emi_mpu_clear_protection(SVP_DRAM_REGION_ID);
+ }
return 0;
-}
\ No newline at end of file
+}
diff --git a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h
index cc7f7f1..18acb9c 100644
--- a/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h
+++ b/plat/mediatek/drivers/emi_mpu/mt8188/emi_mpu_priv.h
@@ -7,7 +7,7 @@
#ifndef EMI_MPU_PRIV_H
#define EMI_MPU_PRIV_H
-#define ENABLE_EMI_MPU_SW_LOCK (1)
+#define ENABLE_EMI_MPU_SW_LOCK (0)
#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000)
#define EMI_MPU_DBG (EMI_MPU_BASE + 0x004)
@@ -38,13 +38,34 @@
#define EMI_MPU_DOMAIN_NUM (16)
#define EMI_MPU_REGION_NUM (32)
#define EMI_MPU_ALIGN_BITS (16)
-#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
+#define DRAM_START_ADDR (0x40000000ULL)
+#define DRAM_OFFSET (DRAM_START_ADDR >> EMI_MPU_ALIGN_BITS)
+#define DRAM_MAX_SIZE (0x200000000ULL)
+#define BL32_REGION_BASE (0x43000000ULL)
+#define BL32_REGION_SIZE (0x4600000ULL)
+#define SCP_CORE0_REGION_BASE (0x50000000ULL)
+#define SCP_CORE0_REGION_SIZE (0x800000ULL)
+#define SCP_CORE1_REGION_BASE (0x70000000ULL)
+#define SCP_CORE1_REGION_SIZE (0xa000000ULL)
+#define DSP_PROTECT_REGION_BASE (0x60000000ULL)
+#define DSP_PROTECT_REGION_SIZE (0x1100000ULL)
#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
/* APU EMI MPU Setting */
-#define APUSYS_SEC_BUF_EMI_REGION (21)
#define APUSYS_SEC_BUF_PA (0x55000000)
#define APUSYS_SEC_BUF_SZ (0x100000)
+enum region_ids {
+ BL31_EMI_REGION_ID = 0,
+ BL32_REGION_ID,
+ SCP_CORE0_REGION_ID,
+ SCP_CORE1_REGION_ID,
+ DSP_PROTECT_REGION_ID,
+ SVP_DRAM_REGION_ID,
+
+ APUSYS_SEC_BUF_EMI_REGION_ID = 21,
+
+ ALL_DEFAULT_REGION_ID = 31,
+};
#endif
diff --git a/pyproject.toml b/pyproject.toml
index 0fe2383..7814497 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
[tool.poetry]
name = "trusted-firmware-a"
-version = "2.10.0"
+version = "2.11.0"
description = "Trusted Firmware-A (TF-A) Python dependencies."
authors = ["Arm Ltd."]
license = "BSD-3-Clause"
diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index d0efab8..56cb21a 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json
@@ -1,6 +1,6 @@
{
"name": "conventional-changelog-tf-a",
- "version": "2.10.0",
+ "version": "2.11.0",
"license": "BSD-3-Clause",
"private": true,
"main": "index.js",