rockchip/rk3399: Add watchdog support in pmusram
To catch early hangs in resume, this sets up the watchdog before
anything else in the pmusram code (ignoring setting up the stack...).
This uses hard coded settings for the watchdog until the proper
watchdog restore later on in the firmware/kernel.
This also restores the old watchdog register values before the PLLs
are restored to make sure we don't temporarily switch over to a 1/3s
timeout on the watchdog when the pclk_wdt goes from 4MHz to 100MHz.
Change-Id: I8f7652089a88783271b17482117b4609330abe80
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
diff --git a/plat/rockchip/rk3399/drivers/soc/soc.c b/plat/rockchip/rk3399/drivers/soc/soc.c
index 7dd0b72..741adde 100644
--- a/plat/rockchip/rk3399/drivers/soc/soc.c
+++ b/plat/rockchip/rk3399/drivers/soc/soc.c
@@ -43,6 +43,9 @@
/* sleep data for pll suspend */
static struct deepsleep_data_s slp_data;
+/* sleep data that needs to be accessed from pmusram */
+__pmusramdata struct pmu_sleep_data pmu_slp_data;
+
static void set_pll_slow_mode(uint32_t pll_id)
{
if (pll_id == PPLL_ID)
@@ -229,9 +232,9 @@
uint32_t rstnhold_cofig0;
uint32_t rstnhold_cofig1;
- slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +
+ pmu_slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +
PMUCRU_RSTNHOLD_CON0);
- slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +
+ pmu_slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +
PMUCRU_RSTNHOLD_CON1);
rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) |
BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) |
@@ -257,12 +260,33 @@
mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1);
}
+void pmu_sgrf_rst_hld(void)
+{
+ mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
+ CRU_PMU_SGRF_RST_HOLD);
+}
+
-void restore_pmu_rsthold(void)
+/*
+ * When system reset in running state, we want the cpus to be reboot
+ * from maskrom (system reboot),
+ * the pmusgrf reset-hold bits needs to be released.
+ * When system wake up from system deep suspend, some soc will be reset
+ * when waked up,
+ * we want the bootcpu to be reboot from pmusram,
+ * the pmusgrf reset-hold bits needs to be held.
+ */
+__pmusramfunc void pmu_sgrf_rst_hld_release(void)
+{
+ mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),
+ CRU_PMU_SGRF_RST_RLS);
+}
+
+__pmusramfunc void restore_pmu_rsthold(void)
{
mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0,
- slp_data.pmucru_rstnhold_con0 | REG_SOC_WMSK);
+ pmu_slp_data.pmucru_rstnhold_con0 | REG_SOC_WMSK);
mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1,
- slp_data.pmucru_rstnhold_con1 | REG_SOC_WMSK);
+ pmu_slp_data.pmucru_rstnhold_con1 | REG_SOC_WMSK);
}
/**